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What is the need for level shifter in operational amplifier *? 

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Proceedings ArticleDOI
Bo Zhang, Li-Ping Liang, Xing-Jun Wang 
01 Jan 2006
40 Citations
The simulation results showed that the proposed level shifter circuit has 36% leakage power dissipation reduction compared to the conventional level shifter
Proceedings ArticleDOI
Amir Hasanbegovic, Snorre Aunet 
01 Nov 2009
34 Citations
The level shifter employs an enable/disable feature, allowing for power saving when the level shifter is not in use.
Results in technology UTBB FD-SOI 28 nm show the proposed architecture would be controllable by subcircuits of systems operating at 0.19 V, which is lower than the minimum voltage (0.32 V) reachable by the most effective state-of-the-art level shifter cell simulated under the same conditions.
Proceedings ArticleDOI
Amir Hasanbegovic, Snorre Aunet 
01 Nov 2009
34 Citations
The level shifter makes use of MTCMOS design technique which gives more design flexibility, especially in low power systems.
This technique simplifies the user-end power supply requirement of the system, thus the proposed level shifter design is applicable in many low-power and power-constraint applications such as in mobile and portable devices application.
In addition, the proposed level shifter realizes a wide operation margin with a lower VDD compared to conventional implementations.
The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations.
The proposed level shifter with a depletion-mode device would be an important building block for an oxide TFT display.
This paper examines the performance of a conventional voltage level shifter and describes a novel high performance level shifter that is more robust under adapting voltage scaling.
Hence, the proposed level shifter is suited for low power, high speed applications.

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