Showing papers on "Adder published in 1971"

Fast modulo threshold operator binary adder for multi-number additions

Abstract: A fast adder for adding more than three words, the correspondingly weighted bits of which are applied to respective bit column adders. The column adders simultaneously produce respective sum and carry result bits of overlapping positional significance or weight. The maximum number of result bits having the same weight is determined by the quantity of words to be added at the same time (which establishes the number of bits in each bit column). In the disclosed embodiment, seven words are added at a given time and no more than three of the generated result bits have the same weight. In effect, the seven operand words are reduced to a subtotal of three result operand words in one computational cycle irrespective of the bit length of the words being added. The subtotal operands are reduced to a final sum by application to conventional carry save and carry look-ahead adders. Equal weighted wire-ORing and matrix memory techniques are employed in the respective column adders to conserve required computational hardware and to facilitate large scale circuit integration.

A 40-ns 17-Bit by 17-Bit Array Multiplier

Abstract: A high-speed array multiplier generating the full 34-bit product of two 17-bit signed (2's complement) numbers in 40 ns is described. The multiplier uses a special 2-bit gated adder circuit with anticipated carry. Negative numbers are handled by considering their highest order bit as negative, all other bits as positive, and adding negative partial products directly through appropriate circuits. The propagation of sum and carry signals is such that sum delays do not significantly contribute to the overall multiplier delay.

Determination of number of ones in a data field by addition

Abstract: An arrangement for counting the number of a given data such as ones in a data field. The system employs full adders which count the number of ones in basic three element subsets of the data field. Additional full adders total the results of the first series of full adders and also count any additional ones of the data field.

Counting Responders in an Associative Memory

Abstract: A method of determining the number of responders to a search in an associative memory is presented. It is shown that less than one full adder per memory cell is required and that the maximum delay in establishing the count is proportional to n, where n is the log to the base 3 of the number of memory cells.

Digital binary multiplier employing sum of cross products technique

Abstract: A high-speed digital multiplier which includes a plurality of functionally and structurally similar multiplier modules which are independent and operate in parallel. The multiplicand and multiplier bits are ANDed and selectively applied to the multiplier modules in accordance with a geometrically similar partitioning of the multiplication matrix. The multiplier modules provide partial products which are then added together to form the final product. The disclosed multiplier may be expanded for longer word lengths by using additional multiplier modules. The multiplier may be fabricated from a plurality of single type gated full adder circuits which is advantageous for large scale integration techniques.

Expandable sum of cross product multiplier/adder module

Abstract: A high speed digital multiplier which includes a plurality of functionally and structurally identical multiplier modules. Each multiplier module is adapted to perform an N X N bit multiplication. In addition, each module accepts product bits and carry bits from other multiplier modules and adds them to the N X N bit product according to the appropriate bit weights. Several modules are interconnected for M X M bit multiplications where M is greater than N. The modules contain all the circuitry necessary for performing the multiplication.

Parallel binary carry look-ahead adder system

Abstract: A multiple bit binary parallel adder system including a plurality of multiple bit group parallel adders with the output carry from the highest-bit of each group adder constituting the input carry of the next highest order group adder. The output carry of the highest order bit of each group adder is rapidly formed by means of logic switching circuits which compile values corresponding to all of the input values to the group adder while the remaining output carries within the group adders are formed as conventional propogated carries.

Modular bcd and binary arithmetic and logical system

Abstract: An arithmetic and logical unit for receiving four bit portions (quartets) of two input operands, a carry-in and several function control signals generates selectively several functions of the operands, including decimal and binary addition and subtraction functions or a desired logical function and provides carry lookahead and carry signals. A set of conversion gates selectively provides either a true or an excess-6 form of the first operand quartet while a complementation set of gates selectively provides a true or 1''s complement form of the second operand quartet. Bit pairs, from the corresponding positions in the resulting quartets, are combined to produce elementary logical functions, including the AND, inclusive OR and exclusive OR functions. In parallel, these elementary functions, an input carry bit, a set of carry look-ahead gates, a set of adder gates and a pair of control signals respectively provide carry signals and the selected function of the operands. A set of decimal correction gates, responsive to the carry signals, are used to correct the adder gate output for decimal addition and subtraction, when necessary.

A Cellular Array for the Nonrestoring Extraction of Square Roots

Abstract: An alternative cellular array design is described for nonrestoring extraction of square roots. The array uses a single type of adder/ subtractor cell with a near-iterative connection pattern.

Voltage controlled oscillator

Abstract: An oscillation circuit loop includes two phase shifters for advancing and delaying the phase of an input signal respectively, an adder for obtaining the vector sum of the output signals of these two phase shifters, and feedback means for the positive feedback of the output signal of the adder to an oscillation amplifier through a tank circuit. An external control voltage is applied to the adder so as to continuously vary the relative magnitude of the two signals added to each other by the adder. With an oscillator having such a construction, the degree of phase shift by the phase shifters and the value of Q of the tank circuit can be freely selected, and as a result, any desired sensitivity and phase control range can be freely obtained.

Digital sorter and ranker

Abstract: A digital sorter and ranker in which pairs of binary words are subtracted from each other in adders by feed-in in one word of the pair together with the adjacent word one''s complement. A carry output indicates which word is the lowest and this output is fed through coincidence logic circuits to additional series of address and logic circuits in pyramid fashion until a single output is obtained from a final adder. The adder logic circuits, the carry output and the output of the final adder are fed through minimum value logic circuits to a series of minimum value flip-flops with the outputs thereof being fed back to the adders and their logic circuits. To record the rank of each word, a series of flip-flop groups with each group corresponding to a binary word is set according to the word''s rank, the flip-flops being controlled by gating circuits fed by preceding logic circuits, the final adder, and a binary counter.

Threshold logic digital filter

Abstract: A threshold logic digital filter converts an input sequence of sets of bits representing amplitudes of a continuous signal at predetermined sample times into another sequence of sets of bits representing the input sequence of sets transformed by a predetermined difference equation. Storage-processor elements are used for implementing threshold logic adder, multiplier, two''scompartment, and overflow detector circuits in the digital filter.

High-speed binary multiplier

Abstract: A multiplier is described which uses a ‘tree’ of adders to add the partial products, resulting in a considerable increase in speed when the adders have a carry-propagation delay per bit which is appreciably less than the addition delay.

Binary full adder-subtractors

Abstract: A binary full adder-subtractor includes a first logic circuit which is supplied with binary digital signals respectively corresponding to an operand and an operator; a second logic unit which is supplied with the outputs of the first logic unit and a first carrying or borrowing signal of a preceding digit; and a gating circuit including AND gate circuits and OR gate circuits and which is supplied with binary digital signals respectively corresponding to the operand, the first carrying or borrowing signal, the output of the first logic unit and an operating signal for starting an addition or subtraction operation, to provide a second carrying or borrowing signal for a succeeding digit.

Electronic musical instrument with a keyboard device capable of producing special musical effects upon key depression

Abstract: In an electronic musical instrument, a keyboard device comprises a flexible and substantially non-extensible tape elastically supported on a keyboard frame below playing keys, and a first and a second detectors at both ends of the tape to generate electrical signals each having an amplitude corresponding to the amount of displacement of each tape end. The electric signals from the first and second detectors are supplied to a signal adder and a signal substractor, the adder giving out signals when the both tape ends move inward and the substractor giving out signals when one tape end moves inward and the other end outward. The output from the adder is supplied to a volume control circuit, while the output from the substractor is supplied to a vibrato effect producing circuit. On this instrument, a downward depression of the key produces an expression control effect, and a lateral movement of the key produces a vibrator effect.

Parallel adder using a carry propagation bus

Abstract: A PARALLEL ADDER IS IMPLEMENTED USING LOW LOSS, DIODE SWITCHES IN THE CARRY PROPAGATION BUS OF THE MULTISTAGE ADDER. ONE SWITCH IS ASSOCIATED WITH AN ADDER STAGE AND EACH SWITCH PRESENTS A SHUNT IMPEDANCE TO THE CARRY PROPAGATION BUS THAT IS A FUNCTION OF THE NUMERICAL SIGNIFICANCE OF THE ADDER STAGE WITH WHICH IT IS ASSOCIATED.

Carry ripple network for conditional sum adder

Abstract: A high-speed carry ripple or propagation circuit including a network of gates and load devices for use with a conditional sum adder. The transmission gates and load devices comprise semiconductor elements. The transmission gates are combined in series and parallel paths to effect desired signal control. The carry ripple circuit generates the required propagated carry signal for the conditional sum adder more rapidly than many prior art networks.

Binary synchronous up/down counter

Abstract: A binary counter consisting of a binary adder and flip-flops, the Q outputs of the flip-flops being connected to the A inputs of the adder, the Sigma outputs of the adder being connected to the D inputs of the flip-flops. By connecting the B input of the adder to any of several combination of source voltages, the counter may be used as a down counter or an up counter wherein the sequence of steps up or down is selectively variable. A count pulse may be provided for pulsing in the new count to the flip-flops. In addition, a set signal may be provided to load the flip-flops and a reset signal may be provided to clear the flip-flops.

Dimension comparator for machine tools

Abstract: A dimension comparator for machine tools is disclosed wherein a first comparator compares a theoretical numerical dimension with an actual dimension as determined by a position measurer. After it is determined that the actual dimension is greater or less than the theoretical dimension, a second comparator compares the actual dimension to a numerical value representing the theoretical dimension plus or minus the numerical value of an aiming interval. This representative numerical value is determined by an adder controlled by the output of the first comparator. In an alternative embodiment, means are provided for controlling the adder to add predetermined increments to the theoretical dimension for comparison in the second comparator.

A high-speed adder using Gunn diodes

Abstract: A high-speed adder employing Gunn diodes is proposed. The system is constructed by using the threshold logic technique for high-speed carry propagation. Since all inputs of n stages with each weight are simultaneously applied to the anode of each Gunn diode to generate the nth carry at once, the operating speed of the adder should be considerably improved.

Timing recovery circuit for use in modified duobinary transmission system

Abstract: A circuit for producing a timing signal from a modified duobinary data signal. This data signal is capacitively coupled through four full-wave rectifiers that are connected in series. The outputs of the third and fourth rectifiers are DC coupled through an adder to a bandpass filter which passes a timing signal that has a fixed phase relationship with respect to the timing signal that was originally employed to produce the modified duobinary signal. The filtered signal is delayed, squared in a limiter, and applied to a zero crossing detector which produces a train of clock timing pulses.

Design of large high-speed binary multiplier units

Abstract: An attempt has been made to review the methods of multiplication available for use in a large high-speed computing machine. Number lengths of 50 to 60 bits and multiplicatiion times of less than 0.5 μs were the design aims. Suitable multiplier units will make use of carry-save adders to reduce the time for each addition cycle, and will decode several multiplier bits in each cycle to reduce the number of cycles required. The number of carry-save adders to be used is set largely by economic considerations. The number of multiplier bits to be decoded in each cycle is determined by the time required to form multiples of the multiplicand prior to cycling. It is shown that the best compromise between cost and speed is achieved if two or three carry-save adders are used in a serial-parallel configuration, and three or two multiplier bits are decoded in each cycle, respectively. A comparison with several other multipliers is made. A method for incorporating carry assimilation at the less significant end of the product is described, thus requiring the final propagate addition to be only single length, while still retaining the full double-length result. An indication of the effect of number length on the conclusions is inclued, but is not worked out in complete detail.

All pass network for phase equalizers of wide band communication systems

Abstract: A phase equalizer has a portion with two channels; an incoming signal is split into two signals for application to the channels so that the phase of the signals differ by 180° and the ratio of their amplitudes is 2:1. The channel with the signal of greater amplitude includes an adjustable resonant circuit for changing phase of its signal, and the signals of both channels are recombined in a succeeding adder circuit. By simply adjusting the resonant circuit, the phase characteristic of the equalizer can be changed readily without changing the amplitude characteristics.

Improvements in directionally selective energy receiving systems

Abstract: 1,222,518. Aerials. L. T. V. ELECTROSYSTEMS Inc. 8 Feb., 1968, No. 6261/68. Heading H4A. Signals from receptors providing broad beam reception patterns inclined in relation to one another are combined to produce two signals having dissimilar virtual reception patterns, one of which has a substantially zero portion over a narrow angle. The other of the said two signals is attenuated outside said narrow angle, so that an equivalent narrow beam reception pattern is obtained from it. In a first embodiment, signals from an omnidirectional whip aerial A4, Fig. 4, are combined with signals from one loop of a rotatable crossedloop aerial 10 in an adder 20, so that signals conforming to an equivalent cardioid directional pattern E CN are obtained as output which are fed to one input of a correlator 30. The signals from the other loop of the crossed-loop aerial 10 are fed to the other input of the correlator 30, which only gives output when both its inputs are of the same phase. A half-cardioid type directional pattern E H results, having half of a narrow beam along the null line of the cardioid E CN . Signals from the said other loop are also fed through a phase inverter 50 to one input of a correlator 40, whose other input is fed by output from the correlator 30. A narrow beam equivalent directional diagram P r4 is thus obtained. In a second embodiment (Fig. 3, not shown) a single rotatable loop aerial is used in conjunction with a whip aerial. Signals from the latter are fed direct to one input of a correlator and also in combination with those from the loop aerial, and subsequent phase inversion, to the other input of said correlator, from which an output equivalent to that from a narrow beam aerial is obtained. In a third embodiment, which is an elaboration of the first embodiment, signals from the two loops of a fixed crossedloop aerial B5, Fig. 5, and from a whip aerial A5 are pre-amplified and are transmitted to a remote control chassis. The signals from the loops are fed via emitter follower amplifiers 4, 5 to the respective rectangularly disposed stator coils 8A1, 8A2 of a resolver 7. The rotor has two rectangularly disposed coils 9A1, 9A2, which give respective outputs corresponding to those from two separate loop aerials, i.e., with figure-ofeight directional patterns at 90 degrees to each other. Both outputs are taken through phase shifting integrating networks 11, 14, and that from the rotor coil 9A1 is fed to one input terminal of an adder 20. The amplified whip aerial signal is fed through a differentiator 12 to the other input terminal of the adder 20, the output from which corresponds to a cardioid directional pattern, and which after passing through a tuned circuit 22, an emitter follower circuit 24, an optional interference rejection circuit 70, a gain control 26, and an amplifier 28, is taken to respective input terminals d1 and d of a correlator 30 and of a selector switch 60. Output from the network 14, which is fed from the other rotor coil 9A2 of the resolver 7, is taken through an additional amplifier 21, a tuned circuit 23, an emitter follower circuit 25, a gain control 27, and an amplifier 29 to an input terminal c1 of the correlator 30, and through a phase inverting circuit 50 to one input terminal of a correlator 40. The output from the correlator 30, corresponding to a half-cardioid directional pattern, is taken through a correction circuit 51 to the other input of the correlator 40. Output from the latter, corresponding to a narrow beam directional pattern, is taken to an input terminal of the selector switch 60, by means of which it may be coupled through an output driver 61 for utilization. The switch 60 also allows the choice as alternative outputs of signals originating in either rotor coil of the resolver 7, or originating in both coils and combined in an adder 15, or originating in the whip aerial A5. In a fourth embodiment (Fig. 13, not shown), signals from a single rotatable loop aerial are combined with those from a whip aerial in two adders, the input from the whip aerial being phase inverted in one case. The outputs from the adders are fed to a correlator, whose output then corresponds to a narrow beam directional pattern. Ganged tunable tracking filters may be inserted in the output lines from the adders and the correlator. In a fifth embodiment (Fig. 14, not shown) signals from a crossed-loop aerial are fed to a resolver (which is similar to the resolver 7, Fig. 5) outputs from which are added and are fed to one input terminal of a first correlator. A signal from a whip aerial is fed to the other input terminal of said first correlator, which provides an output corresponding to a cardioid patterned directional signal. Said output signal is phase reversed, and is then fed to one input terminal of a second correlator, which has as second input the signal from the whip aerial. The output of the second correlator corresponds to a narrow beam directional pattern. In a sixth embodiment (Fig. 15, not shown), also using a crossed-loop aerial with resolver and a whip aerial, signals from one rotor coil of the resolver are combined in an adder with those from the whip aerial to produce signals corresponding to a cardioid directional pattern, which are fed to two correlators and to a first inverter. Signals from the other rotor coil of the resolver are fed directly to the input of one correlator, and through a second inverter to the other input of the other correlator. The outputs of the correlators correspond to halfcardioid directional patterns of opposite hands, and these are combined in an adder to give an output corresponding to a pear-shaped directional pattern, which is then combined in a final adder with the output from said first inverter to give an output corresponding to a narrow beam directional pattern. Correlating means are described in which one signal is fed to the primary of a transformer (T), Fig. 7 (not shown), which has a centre-tapped secondary connected to opposite junctions (J1), (J2) of a bridge comprising four diodes (D1), (D2), (D3), (D4). The other signal is connected between the centre point of the secondary of the transformer (T) and earth, and output is taken from a point (m) which is connected to the other opposite junctions (J3), (J4) of said bridge by diodes (D5), (D6), respectively (see Specification 1,222,519). An interference rejection circuit 70, Fig. 5, may comprise an adder placed in circuit between the emitterfollower circuit 24 and the gain control 26, and having a second input from the slider of a potentiometer which is connected across the inverter 50, said potentiometer having an earthed centre-point. In this way, the cardioid directional pattern to which the signals at the terminal d1 of the correlator 30 correspond, may be effectively rotated (Fig. 11, not shown). In a preferred arrangement, output from the amplifier 29, Fig. 5, is connected to a potentiometer via a para-phase amplifier and cathode follower stages (Fig. 12, not shown). (See Specification 1,222,520).

Threshold logic circuits

Abstract: The invention is a threshold logic circuit including a pair of busses and a plurality of storage-processor elements connected to the busses. Each element is arranged to decide which one of a pair of double-rail input signals has a higher potential and to store the result of that decision. Information read out of storage directs a unit of current alternatively to one or the other of the two busses. A threshold logic adder circuit and a threshold logic two''scomplement circuit are included.

Review of high-speed addition techniques

Abstract: A new large computing machine, the MU5, is under construction at Manchester University. As one aspect of the design of this machine, a review of available addition techniques was undertaken. This included both the use of special circuits for improving carry-propagation speeds, and the effects of restricted fan out and fan in on logical adders. The fastest adder uses a combination of block-carry and conditional-sum approaches and may be further improved by use of the sequential-state technique; emitter-coupled logic being used. Where economy is more important than speed, transistor-transistor medium-scale-integrated logic had advantages. Other techniques discussed include the saturated-transistor carry-path and serial-parallel adders.

Digital Analyzer for Statistical Moments: Design and Error Characteristics

Abstract: A digital instrument is described that provides decimal readouts of the first four time-averaged moments and of the cumulative amplitude probability of a randomly varying voltage. There is no low-frequency limit, the upper-frequency being limited to about 6 kHz for a 99 percent confidence interval of 1 percent error. Measurements can be made in a one-cycle mode (for periodic inputs) or in a fixed-time or fixed-sample-size mode. Readouts of all the moments are available immediately at the end of the measurement time so that the instrument can be used for real-time applications. The voltage under measurement is sampled systematically and the samples are processed immediately using a weighted-feed logic system. The principles of operation and the design of the instrument are described. For many commonly encountered signals the overall error is within 1 percent for all four moments.

Serial Adders with Overflow Correction

Abstract: A method of implementing two single-bit adders is discussed. These adders can be used individually to realize the conventional functions of serial addition and serial multiplication on a pair of operands, or they can be cascaded to allow the serial addition of three operands for forming the product of complex numbers. In either case, the circuits will detect the occurrence of an overflow or the generation of the number minus one, and they will allow an addition to be rescaled by outputting the correct bits during the additional shifts, whether the addition overflowed or not.

Circuit arrangement for converting a decimal number coded in the bcd code into a pure binary number

Abstract: A circuit arrangement, for converting a decimal number expressed in the BCD code into a pure binary number, comprises plural binary full adder circuits arranged successively in ascending binary digit order and each having signal inputs and binary digit outputs. Plural BCD code input terminals have applied thereto the decimal number to be converted, and lines connect each code input terminal commonly to all those signal inputs of the adder circuits which are associated, in correct decimal column position, with those 2n numbers which yield, as their sum, the decimal number, expressed in the BCD code, and indicated, with consideration of its decimal column position, at their respective code input terminals. The adder circuits are interconnected in such a manner that the carryover and output signals of each binary full adder circuit are supplied in correct decimal column position to the signal inputs of the respective succeeding binary full adder circuit.

Error detection circuit

Abstract: A logic circuit having nine input terminals uses four full adders and a NAND-gate to provide an output signal when signals are applied to any two or more of the input terminals.