Showing papers on "AND gate published in 1979"

High-voltage circuit for insulated gate field-effect transistor

Abstract: A high-voltage circuit for insulated gate field-effect transistors (MOSFETs) is provided wherein two MOSFETs are connected in series, the source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the high-voltage circuit, the drain of the second MOSFET being used as a drain terminal of the circuit. First and second resistors are connected in series between the source terminal and the drain terminal, and a biasing voltage supply is connected between the juncture of both the resistors and the gate of the second MOSFET. By virtue of these connections the "on" resistance of the high-voltage circuit is improved due to the effect of the biasing voltage effect in bringing the second MOSFET into an "on" condition.

Speed control apparatus for railroad trains

Abstract: A pair of on-board processing units, operating in parallel, are supplied with input signals representing actual train speed, advance traffic conditions, and selected train parameters. Each unit continuously calculates a maximum train speed from which emergency braking will stop the train within the indicated clear track distance ahead. Each unit also compares the calculated maximum speed with actual train speed and emits a preselected distinctive frequency signal or a d.c. signal as actual speed is less than, or equals, or exceeds maximum speed, respectively. A logic network with parallel filter-rectifier circuit paths passes the unit outputs, if of the preselected frequencies, to a two-input AND gate whose output holds emergency braking released. If a preselected frequency output is absent from either or both units, due to actual speed equaling or exceeding maximum speed or to a fault condition in the apparatus, the corresponding lack of an AND gate output actuates emergency braking. Each processing unit monitors operation of the other unit so that, if a malfunction is detected, the operable unit, when input speed signals are within limits, also emits a second signal of the other unit frequency. This is passed through a separate filter rectifier circuit within the logic network and applied to the second input of the AND gate to maintain train movement.

The prospects for ultrahigh-speed VLSI GaAs digital logic

Abstract: Recent advances of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. The authors evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. GaAs IC fabrication and logic circuit approaches is reviewed. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits.

A Programmable Logic Approach for VLSI

Abstract: This paper explores the use of a proposed programmable storage/logic array (SLA) chip as a general purpose universal logic element for digital computers. The SLA is compared to other programmable logic arrays in implementation and utilization, showing how it permits construction of complete digital subsystems on one chip without sacrifice in programmability. When compared with other contending very large-scale integrated technology (VLSI) approaches, such as microprogrammed processors and gate arrays, the SLA offers an attractive combination of cost, performance, and ease of implementation.

The effects of two-dimensional charge sharing on the above-threshold characteristics of short-channel IGFETS

Abstract: In a short-channel Insulated Gate Field Effect Transistor (IGFET), a significant fraction of the electric field lines associated with the depleted region under the gate are terminated on the source and drain junctions. In this situation the two-dimensional sharing of the depleted substrate charge between the source, drain and gate terminals, has a dramatic effect on the device behaviour. A model is presented to describe the above-threshold characteristics of short-channel IGFETS when they are affected by the proximity of the source and drain junctions. The analytical forms allow a continuous description of the drain current from subthreshold to above threshold conduction. The model takes into account the fact that the device may be turned on by the drain voltage rather than by the gate voltage; in addition, it describes naturally the enhanced drain conductance commonly encountered in short-channel devices. The description includes both the linear and saturation regions over the complete range of drain and substrate voltages and for gate voltages below the value where channel-drain junction interactions become important or velocity saturation sets in. The model therefore provides an analytical description for a short-channel IGFET in the voltage regime where high-field effects in the channel do not significantly effect the current flow. The results indicate that the dominant effects for this region of operation in a short-channel device may be represented by the use of a drain-voltage and geometry-dependent threshold voltage. In the saturation region, the effects of the threshold variations are reflected in the parameter VSAT, the saturation voltage. The principle features of the model are verified by a detailed comparison with short-channel devices.

Method of forming self-registering source, drain, and gate contacts for FET transistor structures

Abstract: The present invention provides a silicon gate FET and associated integrated circuit structure in which a second level of polysilicon is selectively oxidized to provide insulating regions where desired. Regions of the polysilicon which were not oxidized are suitably doped to function as electrical interconnects to the source and drain regions in the substrate and to the gate. In the preferred embodiment, a metallic interconnection is made between the gate and drain or source region with the second level of polysilicon.

Rewritable programmable logic array

Abstract: A Rewritable Programmable Logic Array (R-PLA) which can alter dynamically logic functions during processing by loading a word pattern of bit personalities to realize the specific logic functions into memory cells of Current Mode Logic (CML) is constructed by splitting a conventional Random Access Memory (RAM) of CML into two parts (SEARCH and READ parts). Each cell structure of the new R-PLA is identified with that of the conventional RAM, differing from a complicated cell structure of a flip-flop and AND gate proposed in the past. SEARCH and READ parts of the new R-PLA can operate AND functions without using special AND gates in each cell in the READ mode and can enter WRITE data from a word direction in the WRITE mode. Each part of the R-PLA comprises a two-channel selector to select READ inputs or WRITE inputs, a CML memory array and sense-drive circuits. The selector and the sense-drive circuits are controlled by means of READ/WRITE control circuits. The logic-in-memory for the AND functions on the array can be conducted by using one of multi-emitters of a transistor in each CML memory cell and an emitter of a reference transistor in each of the sense-drive circuits in the READ mode of the new R-PLA. The new READ/WRITE control circuits let a word pattern of the bit personalities load into the CML memory cells in the word direction.

Circuit optimization of the taper isolated dynamic gain RAM cell for VLSI memories

Abstract: A one transistor only, ROM like dynamic RAM cell, whose operation depends on the modulation of the threshold of a buried channel device by a hole packet, derived from the channel stop region will be covered. Tapered oxide between the field and gate oxide is used to form a potential barrier for holes.

Digital logic simulation at the gate and functional level

Abstract: Simulation, in several forms, is used extensively in present day circuit design. The various forms of simulation can be categorized in terms of level of detail offered, ranging from circuit level (transistors, capacitors, etc.) to timing level (e.g., MOTIS (1)) to logic gate level (NAND, NOR, etc.) to register transfer level. As with a microscope, increasing the resolution decreases the field of view. This 'law' imposes a constraint on the size of circuit a designer can simulate at any one level of detail, and most simulation programs are rigidly defined to operate at only one level. This leads to obvious problems, for example, when a circuit is mixed analog/digital, although some progress has been made on incorporating circuit level and gate level detail in one program(2). However, digital circuit sizes keep increasing and even now the gate level often offers too much resolution. To keep simulation costs down and to avoid overwhelming the macroscopic features of a circuit with irrelevant data another level of digital logic simulation is required. The various Hardware Description Languages(3) are too far removed from the gate level to be of much use here as they represent a very large, discrete jump from the gate level, when we would prefer a continuum of simulation resolution.

Dynamics of an asymmetric nondestructive read out memory cell

Abstract: In single flux quantum interferometer memory cells the information can be stored without bias current, if the interferometer inductance L is chosen sufficiently large ( \lambda = 2\piLI_{0}/\Phi_{0} = 2\pi ) to allow for three stable states (-1-, 0-, 1-mode) at zero control and gate current. In this case the binary informations are represented by the -1- and 0-mode of the interferometer. The nondestructive read out operation of a binary "1" is performed without a transition into another mode or into the voltage state. The binary "1" corresponds to no sense signal. Nondestructive read out of the binary "0" is achieved in switching to the voltage state and in returning to the 0-mode after the end of the drive currents. In this paper the dynamics of switching back into the zero voltage state are investigated by simulations of trajectories in the order parameter phase plane. It is shown that for realistic fabrication tolerances the interferometer settles in the wanted 0-mode and not in the -1- or 1-mode even under severe gate or control current disturbs, if the maximum Josephson currents of the two Josephson junctions are unequal (2:1) and if the McCumber damping factor is sufficiently large ( \beta \approx 100 ).

Control of access to semiconductor memories - uses access controller requiring validating inputs before opening and gate linking address bus and address decoder circuits

Abstract: Unauthorised access to electronic memories containing confidential information is prevented by placing an access control circuit between the address bus and the address decoder circuits. The access control circuit (19) requires validating input signals (28,29) before it will supply a signal (17) to one input (16) of an AND gate (15) whose other input (14) is from the address bus (11). Thus, the required address will only be passed to the address decoder (26) when the AND gate (15) has signals from both the address bus and the access controller. This prevents access to the memory for either reading or writing. The required access code may be extracted by the controller from the memory in a preliminary cycle. The access controller program is stored in fusible link semiconductor read only memory (ROM).

Nonvolatile semiconductor memory device

Abstract: PURPOSE:To prevent completely error deletion of memory information by enabling IC itself to function to prevent the memory information from being erased by mistake. CONSTITUTION:When source terminal 3 is applied externally with an erasing voltage, memory transistor Q operates as a transistor in a depletion mode, so that information in memory cell array 1 can be rewritten. When gate terminal 4 is applied externally with the above-mentioned write voltage, on the other hand, memory transister Q operates as a transistor in an enhancement mode, so that information rewriting operation of memory cell array 1 will become impossible. When resistances R2 and R3 are set to values between several and tens KOMEGA, input impedance between source terminal 3 and gate terminal 4 lowers and the binary state of memory transistor Q never changes with an exception of artificial operation. Therefore, error deletion of memory information can be prevented.

Voltage-to-frequency converter having a constant frequency mode of operation

Abstract: A combination of integrating and logic means in an electrical circuit responds to inputs from a variable analog control signal and from a constant frequency train of digital pulses. The magnitude of the control signal is variable between predetermined low and high extremes. The logic means periodically generates discrete output signals in synchronism with the digital pulses. When the control signal is lower than a predetermined intermediate magnitude, the integrating means is saturated and the logic means is able to produce the output signals at a constant frequency. When the control signal is between its intermediate and high extreme magnitude, the integrator is active and governs the operation of the logic means in such a manner that the average frequency of the output signals varies between its constant magnitude and zero as an inverse linear function of the control signal magnitude.

Method of making implant programmable metal gate MOS read only memory

Abstract: An MOS read only memory or ROM is formed by a process compatible with standard P or N channel metal gate manufacturing methods. The ROM is programmed at a late stage of the process after the metal level of contacts and interconnections has been deposited and patterned. Address lines and gates are polysilicon with an overlying patterned metal layer and output and ground lines are defined by elongated heavily doped regions. Thin gate oxide is formed for every gate position, rather than for only the selected gates as in the prior standard programming method. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates where metal has been removed, using photoresist as a mask.

Electronically controlled automatic washing machine

Abstract: PURPOSE:To provide a washing machine which is made easy to use by information operation conditions correctly to the users with a buzzar which has different input systems for alarming the programme completion and the abnormal condition occurence. CONSTITUTION:When the programme reaches the final course, the output of the NAND gate 32 becomes of a logical level 1 and thirty seconds before the completion of the programme, the output of the NAND gate 34 becomes of a logical level 1. As a result, AND gates 33 and 36 open and a transistor 38 becomes ON intermittently, whereby a buzzar 40 is exited to sound. On the other hand, in the case that the lid is opened or some abnormal vibration occurs, a dehydration signal FR2 is sent out of an F resistor and the water level signal SN2 or SN3 becomes of a logical level 1, thereby opening an AND gate 43 and reversing a monostable multivibrator 46 for a certain time to actuate the buzzar 40. In this instance, a light emitting diode 53 is adapted to emit light preliminarily, in the normal operation, after the completion of a predetermined course. The buzzar 40 is adapted, in the abnormal occation, to have electric current flow therethrough and sound with adjusted volume and frequency.

Mos type semiconductor device

Abstract: PURPOSE:To obtain a protective circuit which can prevent a short between a drain and gate and has low PN-junction dielectric strength and high discharge performance. CONSTITUTION:Input terminal 3 is connected to N-type drain layer 12 of MOSFET9 via N layer 6 in a P-type substrate, and Al wiring 11 is led to input gate 1. The gate electrode of protective FET9 is connected to earth line 17. Source 14 and poly-Si resistance 10 are connected together via the Al wiring and then connected to earth line 17 at opening part 16. Source and drain terminals are pointeed. When a large electrostatic voltage is applied, an avalanche breakdown starts in the pointed region at a low voltage and produced positive holes decrease the potential of the substrate to discharge static charges. By this current and resistance 10, the source potential risis, so that the discharge will stop. Since those are carried out momently, charges are not injected until a short occurs between the drain and gate. In this way, MOSFET1 can be protected.

Static induction type semiconductor device with multiple doped layers for potential modification

Abstract: In a static induction type semiconductor device comprising a semiconductor region having one conductivity type and a low impurity concentration and gate regions having an opposite conductivity type and a high impurity concentration formed in the semiconductor region to thereby define a channel region between these gate regions, there is provided a subsidiary semiconductor region having the one conductivity type and a relatively high impurity concentration either around each gate region to leave an effective channel region in the semiconductor region, or adjacent to the effective channel region in the entire channel region on the drain side. By so constructing the device, this effective channel region has a relatively low potential difference even when the channel region is completely depleted, and provides a relatively wide current path. The subsidiary semiconductor regions establish a relatively high potential difference near the gate regions so that the distance between the gate regions can be made substantially small. In case the subsidiary semiconductor regions are provided around the gate regions, the built-in potential at the junction will become large so that, even at the time of forward biasing, the minority carrier injection from the gate to the channel will become small. Also, this composite channel structure can be effectively applied to recessed gate device and split gate device as well.

A Self-Oscillating Dual Gate MESFET X-Band Mixer with 12 DB Conversion Gain

Abstract: An x-band receiver stage including preamplifier, mixer and local oscillator has been realized by a dual gate GaAs MESFET in common source configuration. The conversion gain for a signal frequency of 10 GHz and an I.F. of 1GHz was 12 dB by appropriate matching the input (gate 1) and output (drain) port. A variable short, connected to gate 2 controlled the L.O. x-band oscillation. The isolation between drain and gate 1 was 16 dB. Using disc and BaTi4O9 resonator matching on Al2O3 substrate with only I.F. external tuning enabled conversion gain of 5dB. The tuner matched circuit had DSB noise figure of 5.5dB and associated conversion gain of 4dB at an I.F. of 1GHz whereas the best noise figure achieved by the disc-tuned circuit was 7.7dB at an I.F. of 300MHz and associated conversion gain of ?1.5dB.

Small-signal nonlinear curcuit model of GaAs MESFET

Abstract: Simple analytical expressions are derived for the drain-to-gate feedback capacitance, for the gate-to-source input capacitance, for the equivalent domain capacitance and the equivalent domain resistance for a GaAs metal-semiconductor field-effect transistor (MESFET). The equivalent circuit parameters are related to the material parameters such as the doping density, the dielectric constant, the low-field mobility, the diffusion coefficient, the built-in voltage and to the design parameters such as the gate length, the gate periphery, the active layer thickness, etc. The results which are in good agreement with the results of Willing et al. [4] may be used for a computer-aided design of GaAs power amplifiers and logic circuits.

Original leaving warning device in copying machine

Abstract: PURPOSE: To surely detect original leaving by deciding the presence or not of the original leaving through the movement of the moving body of an automatic original feeder. CONSTITUTION: An AND gate 39 is connected via AND gate 31, changeover relay 36, self-holding relay 37, etc. to the flip-flop 30 connected with an OR gate 33. The copying operation signal S 1 and copying operatable state signal S 2 are inputted to the flip-flop 30 and the signal S 3 when the moving body 5 of the automatic original feeder is lifted is inputted to the OR gate 33. Then, when the lifting of the moving body 5 is not done before the next copying operation enable signal S 2 is given after the copying operation has been done and the flip-flop 30 has been set, then the original forget signal S 4 is outputted from the AND gate 31 and the lifting of the moving body 5 is done by the operation of the relay 37. At the same time, the original leaving warning signal S 6 is outputted from the AND gate 39. COPYRIGHT: (C)1980,JPO&Japio

An Experimental Input System of Hand-Drawn Logic Circuit Diagram for LSI CAD

Abstract: This paper outlines a computer input system that reads hand-drawn LSI logic circuit diagrams. The system discriminates between connection lines and gate symbols and identifies the gate type. The input device can read diagrams drawn on sheets of paper up to size A2 (40 x 55 cm). Simple algorithms for discriminating between connection lines and gate symbols are also presented. These algorithms enable rapid processing of input data because there is no preliminary processing such as thinning or smoothing of lines. A performance test was made using a circuit diagram drawn on a size A4 (18 x 25 cm) sheet of paper. The results show that the input device can be put into practical use and, when combined with an interactive graphic system, can contribute to more efficient LSI circuit design.

Digital signal conversion circuit

Abstract: Circuit for converting input signals at TTL voltage levels to output signals at voltage levels for use with MOS logic circuits. The circuit employs an arrangement of NMOS FET's. Six FET's are arranged in pairs to form three inverters. Another FET is connected in series between the input terminal and different portions of the first and second of the three inverters. The output of the second inverter is fed back to the gate electrode of one of the FET's of the first inverter and to the gate electrode of the series connected FET. The output of the second inverter is also applied to the third inverter. The excursion between voltage levels representing logic 1 and logic 0 at the output of the third inverter is greater than the excursion between voltage levels representing logic 1 and logic 0 at the input to the circuit.

Delay measurement of experimental 2.5‐μm Josephson current injection logic (CIL)

Abstract: Switching speeds of experimental Josephson interferometer circuits are measured on chains of current injection logic (CIL) gates fabricated using 2.5‐μm minimum features. Logic delay of 32 ps per gate is measured for a four‐input OR gate with a fan‐out of 2. The average power dissipation of the four‐input OR gate is 4 μW and the corresponding power‐delay product is 1.28×10−16 J. For four‐input AND gates the measured logic delay is 60 ps, the power dissipation is 6 μW, and the power‐delay product is 3.6×10−16 J. The results are found to be in excellent agreement with estimates based on computer simulations.

Mis memory circuit

Abstract: PURPOSE:To speed up the write-in operation, by avoiding the application of the write-in signal to the readout circuit and enabling to set the mutual conductance of MISFET greatly through the separation of digit line and sense line. CONSTITUTION:The memory storage MIS transistors TrQ1 to Q4 constitute the memory storage FF11, and the gate of the readout MIS TrQ7, Q8 is connected to the A word line AWL and the B word line BWL, and the drain is connected to the A sense line SA and the B sense line SB respectively. Further, when the mutual conductances gm 1,2,5,6 of MISTrQ1, Q2 and gate MISTrQ5, Q6 have the relation of gm5/gm1=K1 and gm6/gm2=K2, K1 and K2 are equal to 1 or greater than 1. With this circuit constitution, when Q1 is non-conductive, the junction T1 is of high potential, and Q9 is conductive, then the potential of SA is changed from high voltage to 0 and the information of logical value 0 is read out. On the other hand, when Q1, T1, and Q9 are in opposite state, the information of logical value 1 is read out, and the similar readout is enable as to the B sense line.

Gate assembly and control assembly therefor

Abstract: An improved gate assembly and gate control assembly for operatively controlling the movement of the gate assembly in material discharging equipment is provided wherein the gate assembly comprises a first and second clamshell gate member, a connecting assembly for pivotably connecting the first and second clamshell gate members to the equipment and substantially synchronizing the movement of the first and second clamshell gate members between a closed position, and an open position, a gate moving assembly operably connected to the first and second clamshell gate members for moving the first and second gate members between the closed and the open position, and the gate control assembly operably connected to the gate moving assembly, the gate control assembly selectively activating the gate moving assembly such that the first and second gate clamshell members are moved between the closed position and the open position. The gate control assembly is further characterized as having a first operational mode and a second operational mode. In the first operational mode the gate control assembly is acutated for positive closure of the first and second clamshell gate members. In the second operational mode the gate control assembly selectively moving the first and second clamshell gate members between the closed position and the open position.

Voltage controlled oscillator

Abstract: PURPOSE:To obtain an oscillation frequency signal with high precision by connecting current control transistors TRs to respective power terminals of each inverter stage and making gate voltage symmetrical with respect to the center value of a supply voltage. CONSTITUTION:A control voltage VC is applied to a control terminal 311, and TRs 309 and 310 where threshold voltages and current transfer rates are practically equally set are connected as shown in the figure. Consequently, the voltage between the gate and the source of the TR 309 is VC, and gate voltages of a VDD-side current control TR 305 and a VSS-side current control TR 308 are controlled as voltages having levels practically symmetrical with respect to the center value of the supply voltage. Thus, oscillation of a ring oscillator is stably operated within the range of the supply voltage because equal cirrents flow into each inverter stage from VDD-side current control TRs and equal currents flow out from VSS-side current control TRs, the oscillation output waveform is not deflected to one side and is not distorted.

Internal combustion engine ignition system test apparatus

Abstract: To permit tests of: ignition timing; dwell angle; engine speed; and voltage levels, a pulse train is provided derived from the ignition system of the engine; the pulse train is applied to a frequency multiplier, preferably a phase locked loop (PLL) which provides a sequence of output pulses having a pulse repetition rate which is a multiple of the frequency of the signals or pulses of the pulse train. An AND gate has the multiplied signals applied thereto and is enabled, selectively, in accordance with the desired test. The output of the AND gate is applied to a counter which counts multiplied pulses within the interval of enabling of the AND gate, the output being applied to a digital indicator to provide a direct readable digital output; preferably, the multiplication rate is selected to provide a digital output indication which is directly readable in desired units. To determine dwell angle, enabling pulses are applied to the AND gate from the ignition system; to determine spark timing, derived enabling pulses are applied to the AND gate, derived from the ignition system upon being compared with a reference signal, for example an upper dead center (TDC) signal; to determine speed, the enabling pulses are applied with respect to a clock reference; and to determine a voltage test level, the input to the system is disconnected and the test voltage applied to a voltage controlled oscillator of the PLL.

Digital display type vehicle speedometer

Abstract: PURPOSE: To eliminate extraneous feel for the display of time whtn a vehicle stops from a running state by forcefully making the content of a display register zero when the generation intervals of vehicle speed pulses exceed predetermined time. CONSTITUTION: Vehicle speed pulses 100 are inputted to a vehicle speed counter 12 via an AND gate 10, and are counted only while the AND gate 10 is being opened by the gate signal 101 of a timing pulse generating circuit 20. After the gate signal 101 goes to 0, the latch signal 102 is outputted in a dispaly register 14, and the content of the dispaly register 14 is rewritten according to the output signal 107 of the vehicle speed counter 12 and is dispalyed 16. On the other hand, the vehicle speed pulses 100 and an initial value setting signal 104 are inputted as reset signals to a time counter 32, and when the clock pulses 106 counted by the time counter 32 exceed a set value, the ouput of a bistable multivibrator 34 is made 1, whereby the dispaly register 14 and the vehicle speed counter 12 are forcefully made 0. COPYRIGHT: (C)1981,JPO&Japio