Showing papers on "Arithmetic logic unit published in 1982"

Floating point addition architecture

Abstract: Parallel shifter architecture in an arithmetic unit of a digital computer for processing floating point mantissas. An arithmetic-logic unit (ALU) in series with shifting means functions in parallel with a barrel shifter. Both paths are executed simultaneously and the output of one path is selected for storage at the end of a microcycle based on machine status and the actual floating point numbers manipulated. This architecture provides a significant reduction in floating point addition execution time.

Error correcting system

Abstract: An error correcting system uses an error location polynominal defined by double correction BCH codes each consisting of the elements of Galois field GF(2m), thereby to generate error locations σ1 and σ2 and error patterns e, and e2. The system has a first data processing system (401) for performing only additions and multiplications to generate error locations σ1 and σ2 and a second data processing system (402) for performing only additions and mutiplica- tions to generate error patterns e1 and e2. The first data processing system (401) comprises a syndrome generator (41), a memory (43), an arithmetic logic unit (44), registers (45A) to (45C), latch circuits (46A) to (46F), registers (47A) to (47F), adder circuits (48A) and (48B) and a zero detector (49). The second data processing system (402) comprises a gate circuit (50), latch circuits (46H) and (46G), an arithmetic logic unit (44), registers (45A) to (45C) and a memory (43).

Single-chip semiconductor unit and key input for variable function programmed system

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, decoders, key input logic, a data storage array, an arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.

Associative processor with variable length fast multiply capability

Abstract: An associative processor is described wherein an array of associative processing cells is configured to achieve variable length multiplication of numbers, such as binary two's complement numbers, under mask control. A configuration suitable for signal multiplication is described wherein the processing sequences in all cells are compatable, each to the other, whether the cells are at the edges or the middle of an array row, and regardless of the computational sequences required to be performed. An associative cell structure is described, including an improved arithmetic logic unit having separate carry and borrow save paths which may be enabled and active simultaneously or alternately.

Digital processing system with self-test capability

Abstract: A digital processing system includes a memory for the storage of both data and instructions of M binary digit widths a N (N≠M) binary digit parallel arithmetic and logic unit and self-test circuitry connected to the memory and connected to the arithmetic and logic unit for summing the numeric value of the contents of the memory into a set of sums that are N binary digit width and for comparing these sums with corresponding checksum constants to determine the integrity of the instructions stored in memory and the integrity of the arithmetic and logic unit operation.

Masked arithmetic logic unit

Abstract: An improved masked arithmetic logic unit is disclosed which incorporates at least three principle unique features to optimize implementation in a high speed environment. These features are (1) the inclusion of a mask operand to facilitate mask compares and mask substitute operations without adding logic levels to the arithmetic logic unit; (2) the inclusion of a sum minus one network to speed up system performance by minimizing the delay usually associated with group borrow input to final sum output and (3) the inclusion of a mode control register internal to the arithmetic logic unit to minimize or camouflage the delay always found in the mode switching control of contemporary arithmetic logic units.

Programmable arithmetic logic unit

Abstract: A programmable arithmetic logic unit for performing high speed bit sliced, pipelined computations at very low power is fabricated as an LSI component using CMOS/SOS technology. It is microprogrammable and operates in conjunction with a fast microprogram store program memory and controller. Dual input ports which supply data from eight sources are latched and operated on while new data is simultaneously fetched. Instruction bits shift data in either port left or right, select complements and select an operand between device input and output data in one port. The data processed in each port is compared and is added to provide a latched tri-state output to an external device.

Arithmetic logic unit

Abstract: An arithmetic logic unit processes a variable operand length instruction such as a decimal arithmetic operation instruction, a plurality of bytes at a time using a multi-byte depth arithmetic operation unit. Multi-byte data including first and second operands are supplied to the arithmetic logic unit through a suppressing circuit. The suppressing circuit suppresses unnecessary bytes other than operand bytes and suppresses all of the bytes of one of the operands when the one operand has been exhausted.

Microprocessor parallel additive execution of a computer count ones instruction

Abstract: A data word of less than or equal to 2 N bits is counted for the number of binary "1's" contained therein in log 2 2 N =N cycles of 3 steps each in a microprocessor. As a first step the data in a first register is logically ANDed in an arithmetic logic unit (ALU) with a mask constant from a first read only memory (ROM), with a first logical product result placed in a second register. As a second step the data from the first register is logically ANDed in the ALU with the same mask constant complemented, and a second logical product result is placed in the first register. Meanwhile, the first logical product result in the second register is shifted in a shift matrix in accordance with a shift count constant obtained from a second ROM. As a third step the shifted first logical product result from the shift matrix is ADDed in the ALU with the second logical product result from the first register, and a sum result is placed in the first register as data. During the N iterative cycles the mask constants of 2 N bits progress (alternate 1's and 0's), (alternate pairs of 1's and 0's), . . . , (half 1's and half 0's) while the shift constants progress 2 0 , 2 1 , 2 2 , . . . , 2 N-1 . After N iterative cycles of 3 steps each, the number of binary 1's in the original data word of 2 N bits is in the first register.

Computing system with multifunctional arithmetic logic unit in single integrated circuit

Abstract: A computing system includes a central processor unit (CPU) in combination with external memory units. The CPU includes an arithmetic logic (ALU), an instruction register, a random access memory, and a control system for interconnecting the functional elements of the CPU via sequential use of a common parallel buss, enabling the CPU to be defined on a single chip. The ALU is capable of performing eight separate arithmetic and logic functions utilizing common logic gates.

Variable function programmed system

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, digit and FLAG mask decoders, key input logic, a register and FLAG data storage array, a decimal and FLAG arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc.. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.

Integrated floating point signal processor

Abstract: Recent advances in technology of VLSI circuits enable economical hardware implementation of highly sophisticated signal processing algorithms. This provides the capability of realising a signal processor with uniform hardware for wide real-time applications. The adaption of the VLSI circuits to special application is possible by appropriate microprograms. The processor speed is determined by the arithmetic unit, particularly if floating point arithmetic is necessary. The processing speed can be increased by decreasing the operation time of the arithmetic unit and by the use of several adders, several multipliers, multiport memory and pipeline technique.

Typewriter having calculating capability

Abstract: A typewriter having a calculating function, comprising: a keyboard having a plurality of character keys including letter, numeral and arithmetic symbol keys; an arithmetic unit for performing an arithmetic operation designated by at least one of the arithmetic symbol keys, based on plural sets of numeric data each representing a numerical value and entered through the numeral keys; a main control unit for selecting the plural sets of numeric data as operands from among successive sets of data entered corresponding to the sequential operation of the character keys, such that only the set of numeric data which is entered last prior to each operation of any one of the arithmetic symbol keys is regarded as one of the plural sets of numeric data representing the operands, the main control unit directing the arithmetic unit to perform the arithmetic operation based on the selected plural sets of numeric data or operands, and reading out a result of the arithmetic operation from the arithmetic unit; and a printing device printing a succession of characters entered by the character keys, and the result of arithmetic operation read out by the main control unit, the result being printed following the succession of characters entered through the keyboard. There is also disclosed a method of printing on a typewriter a succession of characters including a statement representing an arithmetic operation. The printing method includes a step of judging whether a set of numeric data is to represent an operand of the arithmetic operation or not.

Arithmetic logic unit of a sequence controller

Abstract: An arithmetic logic unit for a stored program sequence controller stores a program equivalent to a relay sequence in a program memory and executes sequence control in accordance with the stored program. A first push-down storage register for sequentially storing logical operation results at branch start points of the relay sequence and a second push-down storage register for sequentially storing logical operation results for branches connected to the branch points based on the logical operation results stored in the first push-down storage register are provided. The arithmetic logic unit carries out the operations based on the logical operation results stored in the first and second push-down storage registers.

Apparatus for providing measurement of central processing unit activity

Abstract: Apparatus and method for measurement of the activity of a central processing unit of a data processing system resulting from the execution of a program or series of programs. A value is initially entered in an arithmetic circuit. Each time an instruction is executed, a quantity related to the amount of activity required to execute the instruction is decremented from the arithmetic circuit. When value in the arithmetic circuit reaches zero, the operating system is notified and a decision whether to continue the program or initiate some other activity in the data processing unit is made. The usage of the machine is therefore determined by the number of times the arithmetic circuit has reached zero during the execution of a program and by the quantity remaining in the arithmetic circuit when execution of the program is complete. Provision is made for other measurement modes such as decrementing the quantity in the arithmetic circuit by a clock.

N-Port arithmetic unit for DSP

Abstract: A new concept in general purpose digital signal processor (DSP) design will be proposed which makes it possible to exhibit the advantages of algorithms optimized for minimum number of addition operations. The proposed architecture is specified by an N-port arithmetic unit and N separate memories. The avoidance of all memory conflicts while the memories are simultaneously bandwidth limited, is discussed. It is shown how moderate control and overhead circuitry can be found. Further a discussion about the optimal choice of the arithmetic unit is given. Examples are presented comparing the use of wave digital (Fettweis) implementations and more conventional implementations of fixed point digital filters.

Combinatorial digital logic using charge-coupled devices

Abstract: Describes a new approach to circuit design that allows charge-coupled devices to perform combinatorial digital logic. These circuits use charge packets, floating gates, and conventional NMOS circuitry in a way that combines the low power, high packing density of CCDs with some of the high-speed combinatorial logic capabilities of conventional NMOS circuits. Since only a few transfers are involved in the operation of these circuits, charge transfer efficiency is not a critical parameter. A CCD ripple adder is described that has been designed, fabricated, and tested, and a charge control analysis has been used to estimate its ultimate speed capabilities. An arithmetic logic unit design is also described. The combinatorial CCD circuits are particularly well suited to previous digital CCD logic approaches in that they allow elimination of power and space-consuming storage registers. These circuits are most useful in applications requiring large, regular, pipelined architectures such as systolic arrays where the critical performance parameter is throughput per unit power.

Operation control system for central processing device of computer

Abstract: PURPOSE:To make it possible to perform always the reprocessing of instructions, by storing always contents of the first storage device in the second small-size and cheap storage device and returning contents of the second storage device to the first storage device to restore the state before the execution of instructions when an error occurs. CONSTITUTION:In a step T0, data alpha and beta are transferred to work registers 31 and 32. In a step T1, data alpha and beta are operated in an arithmetic logic unit 3. In a step T2, an operation result delta is stored in a general register 11, and simultaneously, data delta before the execution of the instruction is held in a corresopnding storage element 21 of a register contents holding device 2. In a step T3, the operation result is checked. Operation results in steps T4 and T5 are stored only in an operation register device 1. Data delta before the execution in the storage element 21 is inputted to an AND circuit 7 by research of a flag bit 21F. Operations of the logic unit 3 and the register device 1 are interrupted. Data delta is returned into the general register 11.

Arithmetic unit in a data processing system with rounding of floating point results

Abstract: A data processing system uses improved procedures for handling various arithmetic operations. Thus, in floating point arithmetic mantissa calculations the system uses a novel technique for inserting a round bit ROUND into the appropriate bit (bit 23) of the floating point result wherein a look-ahead carry bit generator stage (13) is used for such purpose to reduce the overall mantissa calculation time. Further, the system utilizes logic which operates in parallel with the floating point exponent calculation logic for effectively predicting whether or not an overflow or underflow condition will be present in the final exponent result and for informing the system which such conditions have occurred. Moreover, the system utilizes a simplified technique for computing the extension bits which are required in multiply and divide computations, wherein a programmable array logic unit and a four-bit adder unit are combined for such purposes.

Arithmetic and logic unit processor chips

Abstract: A multi-stage, multi-function, arithmetic and logic unit for a data processing system is formed with only a small number of components on a chip. The basic circuitry (12, to 29) for each bit slice comprises the logic (12, 13, 16 to 19) for the basic arithmetic function feeding a shift stage (14, 15). Control signals (SO SNO Sx SHIFT) selectively disable sections of the basic circuitry so that the result bits for basic arithmetic and one logic function (SUM and XOR) are generated within the bit slice and appear at the output of that bit slice while other logic functions (AND and OR) appear at the output of the next adjacent bit slice (22, 23, 26 to 29) and are bit realigned by the shift stage.

VHSIC Vector Arithmetic Logic Unit (ALU) As An Image Processing Element

Abstract: The VHSIC Vector Arithmetic Logic Unit (VALU) is a particularly powerful computational resource which has been optimized for signal and image processing. The device features a sixteen bit parallel multiplier, a sixteen bit full capability ALU, a thirty-six bit adder/subtractor, sixteen words of multi-port register file, and a user specified 96K Read Only Memory for storage of sixty-two bit microinstructions. The versatility of the VALU architecture and its associated support devices permit the construction of various image processing configurations including: single VALU array processors, arrays of array processors, and systolic array structures for extremely high speed image processing requirements. The different image processor architectural configurations are reviewed and examples of specific algorithm executions are given to demonstrate the applicability of each approach when related to algorithm partitioning, throughput requirements, flexibility requirements, size requirements, and power requirements.