Showing papers on "Asynchronous communication published in 1976"

Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus

Abstract: Data transfer synchronization is achieved in a data processing system by a transferring unit enabling a clock cycle stall mechanism each time a transfer is attempted, disabling such mechanism upon receipt of a predetermined response from the receiving unit, the mechanism actually producing a clock cycle stall if such predetermined response is delayed beyond the duration of the clock cycle. Further, such stall mechanism is enabled in a receiving unit before the expected receipt of information, and actually produces a clock cycle stall if such response is so delayed.

Synchronisation and arbitration circuits in digital systems

Abstract: Synchronisation of two independently clocked processor units, or arbitration between two asynchronous units requesting access to a common resource, can cause serious time losses in a computer system. The ways in which these problems arise are considered, and a theoretical basis for calculation of the time losses is presented. The theory is then correlated with measurements on practical devices, and currently available methods for minimising the time loss are evaluated. Conditions necessary for prediction of the performance of synchronisers and arbiters are established and it is shown that design principles exist which allow the construction of systems with known reliability.

Time diversity data transmission apparatus

Abstract: An asynchronous, time diversity transmission apparatus including a data encoder at a transmitting location and an error-correcting data decoder at a receiving location for overcoming the effects of signal fading, impulsive noise and interference. The asynchronous data encoder encodes a single input data stream into three or more redundant, parallel data outputs having time diversity introduced by successive delays. The data outputs are frequency multiplexed and propagated over a transmission circuit. Received data is demultiplexed and input to the data decoder where it is processed to remove the time diversity. Three or more outputs from the decoder are combined to form a single, error-corrected data output.

Contention-resolving circuits for computer interrupt systems

Abstract: In computer input-output systems contention occurs when two or more peripheral devices make interrupt requests simultaneously. The currently used methods for resolving this contention are outlined, and an improved method which avoids their drawbacks is presented. Synchronous and asynchronous implementations are described, and the effects of bus propagation time are discussed.

Asynchronous-to-synchronous data concentration system

Abstract: ASYNCHRONOUS-TO-SYNCHRONOUS DATA CONCENTRATION SYSTEM Abstract of the Disclosure Asynchronous character-oriented (start-stop) data are transmitted through a synchronous transmission channel at a rate which can exceed the synchronous rate. The excess data rate is accomplished in an input buffer at the transmitter by suppressing occasional stop bits in proportion to the difference between synchronous and asynchronous rates. An output buffer at the receiver detects start bits and thereafter monitors the presence or absence of stop bits. When a stop bit is absent, the output buffer restores it before delivering the character to the data user. Special control signals not organized into charac-ters, such as all-space signals, are also monitored at both transmitter and receiver to insure that stop bits are not spuriously inserted.

Asynchronous digital locking system

Abstract: An asynchronous digital electronic combination locking system including a hand-held transmitter means for providing timed and coded transmission data, and a receiver for providing timed and coded receiver data and comparing the receiver data with the incoming transmission data. The door locking apparatus is opened only when said timed and coded data matches.

Asynchronous self timed queue

Abstract: An asynchronous system includes a plurality of cascaded asynchronous cells in which data is transferred through the system according to the presence of data in the cells. Each cell contains two latches for storing binary data. Means are provided for feeding back to the previous cell a signal indicative of data stored in either of the latches. Transfer gate means cooperating with the latches and the feedback data presence signal provides a means by which data is sequentially transferred through the queue according to the presence or absence of data in the cells.

Annunciator communication system

Abstract: An annunciator communications system in which any one of a plurality of identical transmitting-receiving units can communicate to the rest through minimum communication links, such as power transmission lines, piping, building structures, or the like. Each unit contains a keyboard encoder controlling the transmitting section of a universal asynchronous receiver/transmitter integrated circuit to generate a modulated 200 Khz output. The receiver section of the integrated circuits in all units on the communications link receives the binary encoded data and passes it to a decoder and multiplexer that controls the input to a six-digit calculator integrated circuit that generates data output signals to a six-digit numeric display.

Self-Synchronization of Asynchronous Sequential Circuits Employing a General Clock Function

Abstract: A self-synchronization model is developed It is based on a general clock function which depends only on the state variables This function is associated with the flip-flop type to be used and is independent of the flow table A modular implementation which uses integrated circuits is obtained With this technique, the synthesis procedures for synchronous machines can be directly applicable to asynchronous circuits without taking care of the critical races and essential hazards

Hardware support for inter-process communication and processor sharing

Abstract: The abstraction of a computer system as a set of asynchronous communicating processes is an important system concept This paper indicates how the concept could be supported at a low hardware level A new inter-process communication mechanism called a mailbox is introduced Examples of its use as a programming tool are given This is followed by a description of hardware features that use this mechanism as the basis of communication between the components of a complete system These features include processor-sharing hardware capable of handling process selection and switching with high efficiency It is also indicated how these features can take the place of conventional input/output structures

Processes and their interactions

Abstract: Coordination of processes may be explicit through logical control signals (asynchronous) or implicit through the use of a specified time base (synchronous). In addition, these interprocess communications can be neighborhood restricted or global in space. These interactions are explored and significant developments and problems are reviewed in this paper.

Fail-Safe Asynchronous Machines with Multiple-Input Changes

Abstract: Several synthesis methods for fail-safe asynchronous sequential machines have been reported recently. All of these methods solve the race problem by using noncritical race state assignments. This approach generally results in large number of state variables, relatively complicated design, and the limitation of single-input change.

A design tool for the multilevel description and simulation of systems of interconnected modules

Abstract: We suggest a methodology and a language to permit the study of a system's behavior (functional validation, evaluation of global performances, critical situations). Every system is regarded as an interconnection of communicating modules functioning in a synchronous or asynchronous manner. The control section and the data section of each module are described separately in terms of respectively non-procedural and procedural sub-languages.

Synchronous circuit connecting system

Abstract: PURPOSE:To make it possible to output a plural number of data informations in asynchronous states one another being synchronized to one clock one by one in a data transmitting-receiving system.

Performance evaluation of some computer organisations

Abstract: Recent trends in computer architecture studies tend to classify various configurations from the instruction and data stream point of view. Thus we have single instruction/single data stream (s.i.s.d.), single instruction/multiple data stream (s.i.m.d.) and finally multiple instruction/multiple data stream (m.i.m.d.) structures. Performance parameters are defined and analysed for these configurations. In the case of m.i.m.d. organisations, a simplified model has been analysed for both synchronous and asynchronous request arrivals. Results indicate the possibility of selecting an optimum amount of resource replication so that the cost utilisation is optimised.

Programming in a viable data flow language

Abstract: Author(s): Arvind; Gostelow, Kim P.; Plouffe, Wil | Abstract: Current solid state technology suggests that future computers will be highly asynchronous machines comprising small intercommunicating processors, each processor contributing its effort to some part of the ongoing computation. The functional basis of such a machine demands a totally different foundation than that of current machines and languages. Data flow has been suggested as an alternative approach to vonNe mann type machines and associated sequential languages. A major cricism of data flow in the past has been the lack of a suitable higher-level programming language for coding programs. We feel that the sketch of a higher-level language presented here not only answers the criticism but also brings an asynchronous control structure into programming languages, as well as a strong theoretical basis for such properties as modularity and verifiability of programs. The paper contains a description of the Irvine Data Flow language ID. Three complete examples of programs in ID are included in section 3. For sake of reference, a BNF grammar for ID has been included in Appendix A.

Digital device for synchronous data communication

Abstract: An integrated circuit synchronous data adaptor (SSDA) provides a bidirectional interface for synchronous data interchange. Internal control and interface logic including first-in-first-out (FIFO) buffer memory enables simultaneous transmitting and receiving of standard synchronous communication characters to allow data transfer between serial data channels and the parallel bidirectional data bus of a bus organized system such as a microprocessor (MPU) system. Parallel data from the bus system is serially transmitted and received by the SSDA with synchronization character insertion and deletion, fill character insertion and deletion, parity generation and error checking. The functional configuration of the SSDA is programmed via the MPU system data bus during system initialization and can be reconfigured via program control during subsequent system operation. Programmable control registers provide control for variable word lengths, transmit control, receive control, synchronization control, and interrupt control. Status, timing and control lines provide peripheral unit or modem control.

Asynchronous speed-independent arbiter in a form of a hardware control module

Abstract: The attained parameters and the development trends of LSI circuits make possible the realization of untraditional computer structures with higher number of cooperating processor and control units or modules. The parallel processes realized in these modules are in majority mutually asynchronous and the length of duration of individual parts of these processes and their mutual time relation cannot be determined in advance. In hardware realization of such systems it is often most convenient when the individual modules behave toward each other like asynchronous speedindependent automata. For interconnection of such modules and for synchronizing the processes realized in them it is advantageous to use so-called arbiters (also called semaphores) whose formal description has been introduced in the theories of parallel processes.The text contains a detailed description of a hardware construction of the arbiter having the character of a universal control module guaranteeing the reliable function at arbitrary time sequence of input requests. This quality is important in view of the danger of metastability so that an arbiter cannot be excluded. In the design of the circuit the simplicity and speed of function have been especially considered and the measured time parameters of the arbiter are quoted.

Low power asynchronous latch

Abstract: The output of a fast-acting ratioless logic circuit is monitored by a sensing device, and when one selected logic output is sensed, a voltage is applied to the output node to latch the output to that state. To effect rapid return to the other state, a switch is provided to deactivate the applied voltage when the output node is established at the other state. The latching is made permanent by the further application of a refresh clock which periodically pulses the output node whenever the one selected state is latched.

Series and asynchronous mode - counteracts data loss or erroneous data transfer to receiver

Abstract: Device for numerical data transfer in series and asynchronous mode is used as an interface between the output of a data transmission channel and a receiver having a clock non synchronised with that of the transmitter. It uses a clock regenerator-recuperator at the transmission channel output. A group of three series registers is for sequentially storing the numerical data from the regenerator. A logic circuit, in series with a Schmitt trigger, is for controlling the transfer of data from the second register to the third register as a function of the respective time bases of the recuperator clock and the receiver clock.

Asynchronous data reception control system

Abstract: PURPOSE:Synchronous reception of the asynchronous fata by arranging the skew with the clock signal of the synchronous fata processing equipment.

Signal transmission system

Abstract: PURPOSE:Signal transmission operating asynchronous between equipments is done synchronous to bestow advantages the synchronous system offers.

Synthesis of p-valued asynchronous sequential circuits by using a general clock function

Abstract: A self synchronization method for implementing p-valued asynchronous sequential machines is given. The general clock function of each multistable type is developed. This function is the kernel of the proposed adaptive synchronism. An implementation of this function is given which does not depend on the number of logic levels. Constraints and advantages are discussed.

Asynchronous polling arbiter

Abstract: Details of a simple polling arbiter used to control the access of a common resource by n independently clocked digital systems (processors) are given. The design, which minimises the number of asynchronous circuits needed, requires only n+2 interconnection lines.