Showing papers on "Asynchronous communication published in 1990"

Parallel discrete event simulation

Abstract: Parallel discrete event simulation (PDES), sometimes called distributed simulation, refers to the execution of a single discrete event simulation program on a parallel computer. PDES has attracted a considerable amount of interest in recent years. From a pragmatic standpoint, this interest arises from the fact that large simulations in engineering, computer science, economics, and military applications, to mention a few, consume enormous amounts of time on sequential machines. From an academic point of view, parallel simulation is interesting because it represents a problem domain that often contains substantial amounts of parallelism (e.g., see [59]), yet paradoxically, is surprisingly difficult to parallelize in practice. A sufficiently general solution to the PDES problem may lead to new insights in parallel computation as a whole. Historically, the irregular, data-dependent nature of PDES programs has identified it as an application where vectorization techniques using supercomputer hardware provide little benefit [14].A discrete event simulation model assumes the system being simulated only changes state at discrete points in simulated time. The simulation model jumps from one state to another upon the occurrence of an event. For example, a simulator of a store-and-forward communication network might include state variables to indicate the length of message queues, the status of communication links (busy or idle), etc. Typical events might include arrival of a message at some node in the network, forwarding a message to another network node, component failures, etc.We are especially concerned with the simulation of asynchronous systems where events are not synchronized by a global clock, but rather, occur at irregular time intervals. For these systems, few simulator events occur at any single point in simulated time; therefore parallelization techniques based on lock-step execution using a global simulation clock perform poorly or require assumptions in the timing model that may compromise the fidelity of the simulation. Concurrent execution of events at different points in simulated time is required, but as we shall soon see, this introduces interesting synchronization problems that are at the heart of the PDES problem.This article deals with the execution of a simulation program on a parallel computer by decomposing the simulation application into a set of concurrently executing processes. For completeness, we conclude this section by mentioning other approaches to exploiting parallelism in simulation problems.Comfort and Shepard et al. have proposed using dedicated functional units to implement specific sequential simulation functions, (e.g., event list manipulation and random number generation [20, 23, 47]). This method can provide only a limited amount of speedup, however. Zhang, Zeigler, and Concepcion use the hierarchical decomposition of the simulation model to allow an event consisting of several subevents to be processed concurrently [21, 98]. A third alternative is to execute independent, sequential simulation programs on different processors [11, 39]. This replicated trials approach is useful if the simulation is largely stochastic and one is performing long simulation runs to reduce variance, or if one is attempting to simulate a specific simulation problem across a large number of different parameter settings. However, one drawback with this approach is that each processor must contain sufficient memory to hold the entire simulation. Furthermore, this approach is less suitable in a design environment where results of one experiment are used to determine the experiment that should be performed next because one must wait for a sequential execution to be completed before results are obtained.

Multistage detection in asynchronous code-division multiple-access communications

Abstract: A multiuser detection strategy for coherent demodulation in an asynchronous code-division multiple-access system is proposed and analyzed. The resulting detectors process the sufficient statistics by means of a multistage algorithm based on a scheme for annihilating successive multiple-access interference. An efficient real-time implementation of the multistage algorithm with a fixed decoding delay is obtained and shown to require a computational complexity per symbol which is linear in the number of users K. Hence, the multistage detector contrasts with the optimum demodulator, which is based on a dynamic programming algorithm, has a variable decoding delay, and has a software complexity per symbol that is exponential in K. An exact expression is obtained and used to compute the probability of error is obtained for the two-stage detector, showing that the two-stage receiver is particularly well suited for near-far situations, approaching performance of single-user communications as the interfering signals become stronger. The near-far problem is therefore alleviated. Significant performance gains over the conventional receiver are obtained even for relatively high-bandwidth-efficiency situations. >

Near-far resistance of multiuser detectors in asynchronous channels

Abstract: We consider an asynchronous code-division multiple-access environment in which the receiver has knowledge of the signature waveforms of all the users. Under the assumption of white Gaussian background noise, we compare detectors by their worst case bit error rate in a low background noise near-far environment where the received energies of the users are unknown to the receiver and are not necessarily similar.

The limitations to delay-insensitivity in asynchronous circuits

Abstract: Asynchronous techniques —that is, techniques that do not use clocks to implement sequencing— are currently attracting considerable interest for digital VLSI circuit design, in particular when the circuits produced are delay-insensitive (DI). A digital circuit is DI when its correct operation is independent of the delays in operators and in the wires connecting the operators, except that the delays are finite and positive.

Renaming in an asynchronous environment

Abstract: This paper is concerned with the solvability of the problem of processor renaming in unreliable, completely asynchronous distributed systems. Fischer et al. prove in [8] that “nontrivial consensus” cannot be attained in such systems, even when only a single, benign processor failure is possible. In contrast, this paper shows that problems of processor renaming can be solved even in the presence of up to t

Real-time behaviour of asynchronous agents

Abstract: In this paper, we present a calculus for real-time communicating systems. The calculus is an extension of Milner's CCS with explicit time. In SCCS, Open image in new window means that if P exists at time r, it will proceed to Q at time r + 1. The time delay is exactly one unit. We extend this idea to asynchronous agents by allowing arbitrary delays. We write Open image in new window to mean that aftert units of time, P will become Q, where e stands for idling. Based on the notion of bisimulation, two equivalence relations over agents are defined. It has been shown that the strong equivalence is a congruence and the weak one is preserved by all operators except summation and recursion [W90]. Various examples are given to illustrate the approach.

Specification and Verification of Concurrent Systems

Abstract: 1. The Interplay of Theory and Practice in a Parallel Object-Oriented Language.- 2. Object-Oriented Process Specification.- 3. Formal Object Oriented Specification of Distributed Systems.- 4. The Design and Development of Ada Real-Time Embedded Systems.- 5. Protocol Analysis and Implementation using NPNs and SDL.- 6. A Tool for the Performance Analysis of Concurrent Systems.- 7. Winston: A Tool for Hierarchical Design and Simulation of Concurrent Systems.- 8. A Specification-Verification Framework for Distributed Applications Software.- 9. Dynamic Communication Links.- 10. Formal Environment and Tools Description for the Analysis of Real Time Concurrent Systems.- 11. An Equivalence Decision Problem in Systolic Array Verification.- 12. Should Concurrency be Specified?.- 13. Semantics for Specifying Real-Time Systems (extended abstract only).- 14. Specifying Processes in Terms of their Environments.- 15. Hennessy-Milner Logic with Recursion as a Specification Language, and a Refinement Calculus based on It.- 16. A Functional Programming Approach to the Specification and Verification of Concurrent Systems.- 17. Synchronization in Network Protocols.- 18. From Synchronous to Asynchronous Communication.- 19. Formal Specification and Verification of Asynchronous Processes in Higher-Order Logic.- 20. Temporal Specifications Directed by Grammar and Design of Process Networks.- 21. Analysis of Estelle Specifications.- 22. Concurrency in Modula-2: Properties of the Language Primitives.- 23. Specification and Implementation of Concurrent Systems using PARLOG.- 24. Specification and Verification in Communications Standards.- 25. Experience with LOTOS and Environment LOTTE on an ISDN Protocol.- 26. The Specification and Design of a Nondeterministic Data Structure Using CCS.- 27. A High-Level Petri Net Specification of the Cambridge Fast Ring M-Access Service.- Poster Sessions.- 1. Modelling of Distributed Problem Solving using Logic Modified Petri Nets.- 2. An Animator for CSP Implemented in HOPE.- 3. A Concurrent Approach to the Towers of Hanoi.- Author Index.

Sharing memory robustly in message-passing systems

Abstract: Emulators that translate algorithms from the shared-memory model to two different message-passing models are presented. Both are achieved by implementing a wait-free, atomic, single-writer multi-reader register in unreliable, asynchronous networks. The two message-passing models considered are a complete network with processor failures and an arbitrary network with dynamic link failures.These results make it possible to view the shared-memory model as a higher-level language for designing algorithms in asynchronous distributed systems. Any wait-free algorithm based on atomic, single-writer multi-reader registers can be automatically emulated in message-passing systems, provided that at least a majority of the processors are not faulty and remain connected. The overhead introduced by these emulations is polynomial in the number of processors in the system.Immediate new results are obtained by applying the emulators to known shared-memory algorithms. These include, among others, protocols to solve the following problems in the message-passing model in the presence of processor or link failures: multi-writer multi-reader registers, concurrent time-stamp systems, l-exclusion, atomic snapshots, randomized consensus, and implementation of data structures.

A methodology for implementing highly concurrent data structures

Abstract: A concurrent object is a data structure shared by concurrent processes. Conventional techniques for implementing concurrent objects typically rely on critical sections: ensuring that only one process at a time can operate on the object. Nevertheless, critical sections are poorly suited for asynchronous systems: if one process is halted or delayed in a critical section, other, non-faulty processes will be unable to progress. By contrast, a concurrent object implementation is non-blocking if it always guarantees that some process will complete an operation in a finite number of steps, and it is wait-free if it guarantees that each process will complete an operation in a finite number of steps. This paper proposes a new methodology for constructing non-blocking and wait-free implementations of concurrent objects. The object's representation and operations are written as stylized sequential programs, with no explicit synchronization. Each sequential operation is automatically transformed into a non-blocking or wait-free operation using novel synchronization and memory management algorithms. These algorithms are presented for a multiple instruction/multiple data (MIMD) architecture in which n processes communicate by applying read, write, and compare&swap operations to a shared memory.

The UAN: a user-oriented representation for direct manipulation interface designs

Abstract: Many existing interface representation techniques, especially those associated with UIMS, are constructional and focused on interface implementation, and therefore do not adequately support a user-centered focus. But it is in the behavioral domain of the user that interface designers and evaluators do their work. We are seeking to complement constructional methods by providing a tool-supported technique capable of specifying the behavioral aspects of an interactive system–the tasks and the actions a user performs to accomplish those tasks. In particular, this paper is a practical introduction to use of the User Action Notation (UAN), a task- and user-oriented notation for behavioral representation of asynchronous, direct manipulation interface designs. Interfaces are specified in UAN as a quasihierarchy of asynchronous tasks. At the lower levels, user actions are associated with feedback and system state changes. The notation makes use of visually onomatopoeic symbols and is simple enough to read with little instruction. UAN is being used by growing numbers of interface developers and researchers. In addition to its design role, current research is investigating how UAN can support production and maintenance of code and documentation.

Synchronization in digital system design

Abstract: A unified framework and terminology is presented for synchronization design in digital systems, borrowing techniques and terminologies from digital system and digital communication design disciplines. The throughput of synchronous and asynchronous interconnect is compared, emphasizing how it is affected by interconnect delay. A discussion is presented of opportunities to apply principles long used in digital communications to the design of digital systems, with the goal of reducing the dependence on interconnect delay. >

Four-slot fully asynchronous communication mechanism

Abstract: The paper is concerned with communication mechanisms in which a record in shared memory is maintained by a writer to provide a coherent and up-to-date data reference which may be accessed at any time by a reader. The dynamic properties of several possible designs are briefly discussed before concentrating on a fully asynchronous form called a four-slot mechanism. This takes its name from the four-element array through which data is routed. Coherence is maintained by means of an orthogonal avoidance strategy without recourse to conventional synchronisation techniques such as semaphores, rendezvous, monitors or critical sections. Various implementation options are considered including software and hardware designs. It is seen that the fully asynchronous mechanism completes the range of basic communications options available to digital system designers.< >

Hardware interface to a high-speed multiplexed link

Abstract: A link interface to a high-speed asynchronous multiplexed ATM telecommunication link includes a data segmenter for forming ATM cells out of data frames, and a data assembler and state memory for assembling data frames out of received multiplexed (interleaved)ATM cells. A novel architecture implemented in hardware, and characterized by absence of intermediate storage of data in the data segmenter and pipelined operation of the data assembler, allows the link interface to operate at hundreds of Megabits and Gigabits per second.

Metaring-a full-duplex ring with fairness and spatial reuse

Abstract: The design principles of a ring network with spatial reuse are described. The goal is to provide the same functions as designs that do not permit spatial reuse and concurrent transmission. A distributed fairness mechanism for this architecture is presented. The basic fairness mechanism can be extended for implementing multiple priority levels and integrating asynchronous with synchronous traffic. The ring is full-duplex and has two basic modes of operation: a buffer insertion mode for variable-size packets and a slotted mode for fixed-size packets. As a result, this architecture is suitable for a wide range of applications and environments. Concurrent access and spatial reuse permit simultaneous transmissions over disjoint segments of a bidirectional ring and, therefore, can increase the effective throughput by a factor of four or more. The efficiency of this architecture does not degrade as the bandwidth and physical size of the system increase. The combination of a full-duplex ring, spatial reuse, a reliable fairness mechanism, and the exploitation of recent advances in fiber-optic technology are the basis for the Metaring network architecture. >

Network synchronization with polylogarithmic overhead

Abstract: The synchronizer is a simulation methodology for simulating a synchronous network by an asynchronous one, thus enabling the execution of a synchronous algorithm on an asynchronous network. Previously known synchronizers require each processor in the network to participate in each pulse of the synchronization process. The resulting communication overhead depends linearly on the number n of network nodes. A synchronizer with overhead only polylogarithmically dependent on n is introduced. This synchronizer can also be realized with polylog(n) space. The polylog-overhead synchronizer is based on involving only the relevant portions of the network in the synchronization process. >

Wait-free data structures in the asynchronous PRAM model

Abstract: A wad-free implementation of a data object in shared memory is one that guarantees that any process can complete any operation in a finite number of steps, regardless of the execution speeds of the other processes. Much of the literature on wait-free synchronization has focused on the construction of atomic registers, which are memory locations that can be read 01 written instantaneously by concurrent processes. This model, in which a set of asynchronous processes communicate through shared atomic registers, is sometimes known as asynchronous PRAM. It is known, however, that the asynchronous PRAM model is not sufficiently powerful to construct wait-free implementations of many simple data types such as lists, queues, stacks, test-and-set registers, and others. In this paper, we give an algebraic characterization of a large class of objects that do have wait-free implementations in asynchronous PRAM, as well as a general algorithm for implementing them.

Optimized synthesis of asynchronous control circuits from graph-theoretic specifications

Abstract: Synthesis support for the design of asynchronous circuits is crucial. The synthesis method proposed starts from a graph-theoretic specification called a signal transition graph (STG). This work deals with the theoretical foundations of a method to transform a given STG into an STG that satisfies the original timing behavior and that in addition obeys the unique state coding requirement. It is shown that in general, many valid solutions to this problem are possible. The authors find a transformed STG that can be realized in a circuit with optimized speed and area. >

Battery saver for a tdm system

Abstract: A power saving method and apparatus in a time division multiplexed system (10) capable of providing a synchronous full duplex communication between a telephone network (12) and a plurality of remote communication units (18). A communication resource controller (14) provides system synchronization, by periodically transmitting synchronization messages through one or more remote sites (11). The communication units (18) attempt to acquire synchronization during a synchronization acquisition interval. If synchronization is acquired, the communication units (18) enter a synchronous battery saving mode (515). In the synchronous battery saving mode (515), the communication units (18) can detect a call request either to their own address or to the address of another communication unit. If no call request is detected, the communication units (18) reduce power consumption for a synchronous power saving time interval, and thereafter merely verify synchronization. However, if synchronization is not acquired, the communication units enter an asynchronous power saving mode (525), wherein they reduce power consumption for an asynchronous power saving interval.

Large fault tolerant packet switch particularly suited for asynchronous transfer mode (ATM) communication

Abstract: Apparatus, and accompanying methods for use therein, for a large (e.g. approximately 1 Terabit/second), fault tolerant packet switch (200), particularly suited for asynchronous mode transfer (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel planes of self-routing cross-points (550), staggered time phased contention resolution and shared memory based input and output modules (260 and 270, respectively). An ATM cell applied to an input port of an interface module contains a data field and a virtual channel identifier (VCI) field. The VCI is translated by the interface module into a new VCI, to identify an output of the virtual channel for the switch and appends to the cell an additional routing header which will be used strictly for internal use in routing the entire cell through the switch and which includes distinct first and second portions.

Functional lockstep arrangement for redundant processors

Abstract: N redundant processors operating in functional lockstep synchronization for maintaining system integrity. Comparison and synchronization logic are connected between N processors in redundant configuration and peripheral devices. The comparison and synchronization logic act to insure that the redundant processors are performing the same read/write operations. Calculation or processing not requiring access to peripherals may take place in an asynchronous manner. Processors are halted from performing further operations until all appropriate read or write operations are synchronized. The processors are then allowed to proceed. An overall watchdog timer provides for detecting an error condition for non-responsive or lead responding processors.

Bus interface synchronization circuitry for reducing time between successive data transmission in a system using an asynchronous handshaking

Abstract: Bus interfacing circuitry provides for high speed communication of signals on a bus by using circuitry that synchronizes data transfers to a single reference point, executes commands from a dual-ranked buffer in order to reduce time consumed by external interrupts, and stores multiple bytes in a FIFO buffer to allow rapid sequential transfers; while also providing a flexible input/output configuration allowing both single-ended and differential mode connections.

A fully-asynchronous digital signal processor using self-timed circuits

Abstract: Self-timed circuits with an appropriate handshake protocol can be used to eliminate the requirement for a global clock in a system. At the board level, asynchronous interfaces already make use of this approach. The natural extension of this concept is to use the same communication between blocks within an IC. To demonstrate this approach, self-timed circuits, or circuits which generate a completion signal, were used, along with interconnection circuits, following a four-cycle handshaking protocol, to design and fabricate a complete general-purpose digital signal processor (DSP). Internally, stages communicate at their own speed, which is an advantage because the speed of operation no longer is constrained by the slowest block in the system. The design methodology becomes modular, the blocks being decoupled with respect to their timing considerations. The DSP contains a full data path, with several feedback paths requiring synchronization between words at different stages of the pipe. Self-timed circuits are used throughout and all communication follows a handshaking protocol. >

Asynchronous remote operation execution in distributed systems

Abstract: The authors present the design and implementation of an asynchronous remote operation execution facility, futures, that retains the benefits of the remote procedure call (RPC) abstraction but allows execution to proceed locally in parallel with remote execution and provides extensive support for managing replies. It is shown how this facility can be easily used to support many common interprocess communication styles, including RPC, multicast, broadcast, returning incremental results, and the multiplexing of multiple remote computations. A flow control mechanism for futures is described. >

Method and apparatus for communicating a plurality of asynchronous signals over a digital communication path

Abstract: Multiple asynchronous signals are transmitted and received through a digital link. Each of a plurality of information signals is digitized at a digitizing rate derived from a component of the signal. For example, the color subcarrier of a television signal can be used to establish the digitizing rate for video and audio signal portions. Each digitized signal is packetized for communication at a transmission rate greater than and asynchronous with its digitizing rate. A variable time interval results between successive transmitted packets for each signal. The time interval between each successive packet for each signal is filled with a variable number of pad bits to provide a continuous data stream. The data streams for all of the signals are multiplexed to provide a combined data stream for transmission. Each packet for each of the signals contains a fixed number of data bits digitized over a fixed time interval related to the digitizing rate for the signal. The transmitted combined data stream is received, and the receipt of successive packets is monitored for each signal to determine the fixed time interval for that signal. The digitizing rate for each signal is computed from its fixed time interval. The received data packets for each signal are then converted to an analog form at the signal's digitizing rate to reconstruct the original information signals.

Asynchronous PRAMs are (almost) as good as synchronous PRAMs

Abstract: A PRAM (parallel random-access-machine) model that allows processors to have arbitrary asynchronous behavior is introduced. The main result shows that any n-processor CRCW (concurrent-read, concurrent-write) PRAM program can be simulated on an asynchronous CRCW PRAM using O(n) expected work per parallel step and up to n/log n log*n asynchronous processors. It is shown that a synchronization primitive for n parallel instructions can be computed using O(n) expected work by a system of asynchronous processors. Since a special case of asynchronous behavior is a fail-stop error, the simulation technique described above can convert any PRAM program into a PRAM program that is resistant to all fail-stop errors and has the same expected work as the original program. >

A logic of concrete time intervals

Abstract: A description is given of: (1) a finite-state model for asynchronous systems in which the time delays between the scheduling and occurrence of the events that cause state changes are constrained to fall between fixed numerical upper and lower time bounds; (2) a branching-time temporal logic suitable for describing the temporal and logical properties of asynchronous systems, for which the structures of (1) are the natural models; and (3) a functional verification system for asynchronous circuits which generates, from a Boolean circuit with general feedback and specified min/max rise and fall times for the gates, a finite-state structure as in (1), and then exhaustively checks a formal specification of that circuit in the language (2) against that finite-state model. >