Showing papers on "Bus network published in 1993"

Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array

Abstract: A structured logic array is divided into hierarchical levels At a highest level (the chip level), blocks are interconnected by a system of chip busses A block interface couples each block to the chip bus system to allow the blocks to communicate with each other At a lower level, each block includes sectors, each sector being coupled to a block bus system by a sector interface The block bus system interconnects the sectors in each block to allow the sectors to communicate with each other The block bus system is also coupled to the block interface to allow signals to be transferred between the block bus system and the chip bus system At a lowest level, each sector includes a plurality of logic elements The logic elements are interconnected by a sector bus system The sector bus system is coupled to the sector interface to allow for the transfer of signals between the sector bus system and the block bus system

Method and circuitry for minimizing clock-data skew in a bus system

Abstract: A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnaround at one end of the data bus. The clockline ensures that clock and data signals travel in the same direction. Synchronization circuitry within transmitting devices synchronizes data signals to be coupled onto the data bus with the clock signal used by other devices to receive the data.

Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus

Abstract: An information processing system, comprising a central processing unit (CPU); a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; a second system bus connected to the CPU; a host bridge connecting the second system bus to a peripheral bus having at least one peripheral device attached thereto, the host bridge including register space for storing information related to transactions occurring over the peripheral bus; and error capture logic incorporated into the host bridge. The error capture logic monitors the transactions occurring over the peripheral bus, detects parity errors occurring during any of the transactions, and generates an interrupt routine over the second system bus to the CPU. The CPU reads the register space and performs necessary recovery operations.

System for counting the number of peripheral buses in each hierarch connected to primary bus for creating map of peripheral buses to locate peripheral devices

Abstract: The present invention provides a program that creates a preliminary map of a multiple bus network used to connect peripheral devices to the central processing unit of an information handling system. This preliminary map is then used by configuration software of the information handling system to locate the peripheral devices in the multiple bus network to configure them. If the physical configuration of the multiple bus network should change in any way, the inventive program can make corresponding changes in the preliminary map without having to rewrite or change the program.

Configuration data loopback in a bus bridge circuit

Abstract: A method and apparatus for reducing cost and complexity of devices in a bus bridge circuit by dividing address and data paths between separate devices to reduce pin count, and by looping back "bridged" configuration data to access configuration registers. The host bridge circuit "bridges" all I/O accesses received over a host bus directly to a peripheral component bus without any decoding. The CDC is both initiator and target on the peripheral component bus for I/O access cycles generated by the host bridge circuit that are targeted for a host bridge configuration register.

Multicast communications method

Abstract: Distributed LANs are connected to a wide area network through terminal adapters, which are interconnected by virtual circuits to form a logical bus network. Each terminal adapter copies cells received through the virtual circuit that is allocated for multicasting, and transfers the copied cells to the adjacent terminal adapters via preset virtual circuits. The terminal adapters assemble a part or all of the transmitted message from the received cells and, according to the contents of the assembled message, transfer the copies of the cells to the adjacent terminal adapters through predetermined virtual circuits.

Environment monitoring system for standard interface bus computer systems

Abstract: An apparatus and method for monitoring the environment of remote components attached to a host processor by means of a standard interface bus having a limited number of address ports. The invention includes a host adapter incorporating a standard bus repeater component and an environment monitoring component. The environment monitoring component has a standard bus interface and is selectably coupled to the standard interface bus, and hence to a host processor. The host interface transceiver is coupled by means of a standard bus to the host processor, and is also selectably coupled to a drive interface transceiver by means of the standard bus. The drive interface transceiver is coupled by the standard bus to one or more storage devices. The host adapter is selectably switchable between two modes, such that either the drive interface transceiver is coupled through the host interface transceiver to the host processor, or the environment monitoring component is coupled to the host processor. The inventive system reduces the overhead of an environment monitoring system in terms of address ports on a standard bus having a limited number of address ports. In addition, the bus repeater component of the inventive system permits doubling the cable length limit imposed on certain standard buses, thereby permitting more remote location of one or more storage devices from a host processor.

Communications highway network system

Abstract: A communications highway network system for the interactive communication of digital and analog information that incorporates LAN, MAN, and CATV technology to provide an information pathway of metropolitan size that has a spanning tree topology The system is multiple drop that operates according a network protocol The network protocol is based on modified TDM techniques, compensation for round trip loop delay, dynamic allocation of time slots on the network bus, and global synchronization The protocol also permits concatenation of data packets to reduce overhead Access to the network bus is controlled by a system allocator operating according to the network protocol The allocator may allocate network bus bandwidth to simultaneously provide three levels of service for the system nodes to access the network bus, namely, isochronous, demand-based dedicated, and contention bandwidth allocation This allocation method incorporates fairness to give all nodes sufficient bus access opportunities

Communications bus and controller

Abstract: The present invention provides for a communication bus (52) and controller (54) which can control communication in more than one communication mode on a TDM bus by inhibiting or interrupting communication in a first mode during communication in a second mode. The bus (52) includes a allocate channel for controlling the bandwidth allocation of the bus amongst the different communication modes.

Systems for informing users about waiting times for buses at stops in a network

Abstract: A system for informing users of a bus network about waiting times for buses at stops of the network comprises means (3-6) for generating and transmitting electrical signals representative of the distance (d) between each bus (1) and the "next" stop (2), and means (7) associated with each stop and organized to receive said signals, to select therefrom those signals that concern said stop, and to display at said stop data relating to the waiting times for the "approaching" buses. The system also includes means for generating electrical signals representative of two past real average bus speeds relating to two different periods immediately before the instant at which the signals are generated, and means for using the average speeds in order to determine the waiting times to be displayed.

Multisite trunked RF communication system with reliable control messaging network

Abstract: A distributed switching network (switch) routes audio and control signals throughout the switch from various audio sources to one or more audio destinations. Audio sources such as mobile/portable radio units (via RF repeater transmitters), dispatch consoles, and landline telephone subscribers (via the central telephone switching network) are preassigned and routed onto an audio channel (i.e. a time slot) on a time division multiplexed (TDM) audio bus through a corresponding node. Each microprocessor controlled node is connected to plural control message buses provided for transferring control messages between nodes. A first supervisory node is physically connected at one end of the message buses and an end node is connected at the other end. If the end node fails to respond to a polling message from the supervisory node within a predetermined time period, the supervisory node assumes that the current messaging bus is faulty and initiates a bus switching operation to an alternate messaging bus. The supervisory and end nodes thereafter coordinate switching of all nodes in the switch to the alternate control messaging bus to insure reliable trunked RF communications over the multisite network.

CPU-independent and device-driver transparent system for translating a computer's internal bus signals onto an intermediate bus and further translating onto an expansion bus

Abstract: A bus interface system for expanding the I/O capability of a portable computer utilizes a parallel port connector with master interface circuitry connected to the internal ISA I/O bus of the portable computer and driving a 25-conductor Centronics-type cable as an intermediate bus. The master interface circuitry is device-driver-transparent, and multiplexes address, data, and control information over a byte-wide avenue of the intermediate bus according to premapped state translation tables. In a preferred embodiment a single peripheral I/O device comprising a slave circuitry may be connected to the 25-pin port, and the slave circuitry demultiplexes the intermediate bus states, providing a synthesized sub-set of ISA states to drive the peripheral device. In another embodiment a docking box comprises a bus with multiple I/O ports, such as a network port, a COM serial port, and additional floppy and hard disk drives. Power circuitry is provided for driving a single connected peripheral device, and for recharging a docked portable computer.

Automatic bus setting, sensing and switching interface unit

Abstract: An integrated automatic bus setting, sensing and switching interface unit is manufactured on board an integrated circuit to interface between the integrated circuit and the system bus. The interface unit can support a plurality of bus structures utilizing the same pins on the integrated circuit for different functions. Several modes of establishing an interface structure are available in the unit. An Address Strobe pin on the integrated circuit is used to automatically detect a signal level representative of the bus structure to be used. A code representative of the parameters of the bus structure is also stored in a configuration register for controlling the interface unit and configuring the pins on the integrated circuit for the specific bus structure to be used. The Basic Input Output System (BIOS) as its first operation stores the code in a register whose contents are then written to the configuration register of the integrated circuit for controlling and configuring the integrated circuit. A combination of these modes is also available.

Prioritization of microprocessors in multiprocessor computer systems

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

High-speed dominant mode bus for differential signals

Abstract: A bus circuit for implementing a high speed dominant logic bus for a differential signal. The bus circuit is useful in a communication network having a plurality of multi-port nodes that are coupled by point-to-point links that communicate differential signals. Each port (30) in the node includes a bus driver (150) that receives the differential signal received at the port. The bus driver supplies a differential current signal to a first bus (40). A terminator circuit (50) is coupled to the first differential bus, to receive the differential current signals supplied from the ports. The terminator circuit, responsive to the differential current signal, outputs a differential voltage signal indicative of either a dominant state or a non-dominant state to a second differential bus (42), which is coupled to the plurality of ports for transmission. A biasing circuit (80) for the bus drivers allows operation at low voltages, and furthermore insures that the zero crossing of the differential input signals is equivalent to the zero crossing of the differential voltage signal on the second differential bus.

Method and apparatus for bus bandwidth management

Abstract: A computer system includes bus bandwidth management for operation of a high-speed bus. The high-speed bus is coupled to a plurality of modules. A plurality of client applications operate on the computer system, and request services from the high-speed bus to transfer data from a source module to at least one destination module. The bus bandwidth management system contains a bus manager, a dispatcher, a global controller, and a local controller contained on each module. Transfer requests for data transfer on the high-speed bus are made from the client applications to the bus manager. The bus manager takes the requested information and, based on a bus management policy management in effect, schedules a transfer order for the transfer requests. The bus manager then transfers the ordered transfer requests to the dispatcher. The dispatcher decomposes the ordered transfer requests into individual bus transfer operations. For each individual bus transfer operation, the dispatcher loads a command packet into the global controller, the source module, and the destination module(s). After the dispatcher dispatches all individual bus transfer operations, the dispatcher returns to the bus manager to receive the next transfer request. The global controller executes the individual bus transfer operations in the transfer order.

Microcomputer system for accessing hierarchical buses

Abstract: In a microcomputer system, an access operation is executed in a pipeline mode via buses to which bus masters are connected, and a control of the pipeline execution is performed by a bus controller. Furthermore, an access for delaying this pipeline operation is carried out by low-level of hierarchical buses connected by a buffer and a low-level bus controller.

Multi-media computer architecture

Abstract: A computer system is comprised of at least one of a main bus and an attached expansion bus, a CPU connected to the main bus, peripherals connected to one of the main bus or to the expansion buses, a subsystem connected to a bus for receiving control, address and data signals from the CPU comprising a graphics controller, a data compression circuit, a video controller, a memory connected to data input ports of the circuits and controllers via a subsystem bus having a bandwidth sufficient to carry video and graphics display signals, a first arbiter for determining which controller is permitted access the memory, a link bus connecting each of the controllers, and apparatus for providing polling signals to each of the controllers and circuits on the link bus and for receiving acknowledgement signals therefrom, and thereby synchronizing and allowing exchange of control information between the controllers and circuits.

Local area network between an elevator system building controller, group controller and car controller, using redundant communication links

Abstract: A LAN elevator network includes (a) a pair of redundant car buses for exchanging signals with car control system elements, (b) a pair of redundant group buses for exchanging signals with the redundant car buses through a car-group bridge, and (c) a pair of redundant building buses, which exchange messages with a building controller, through a group-building bridge. Communication among all nodes on the car bus, group bus, and building bus occurs using a single protocol. Each communications element on a bus communicates with the bus using a communications coprocessor including a transmitter and a receiver.

Wavelength-division-multiplexed distributed optical fiber amplifier bus network for data and sensors

Abstract: A wavelength-division-multiplexed data-gathering network that uses a distributed fiber amplifier bus is demonstrated. A prototype, which is suitable for simultaneous data transmission and wavelength multiplexing of sensors, has been constructed based on lightly doped erbium fiber and fiber Bragg reflection gratings. The potential size to which such a network can be extended is discussed.

Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Microsequencer bus controller system

Abstract: A microsequencer bus controller system provides a flexible and efficient mechanism for controlling multiple gate arrays called stations embedded within a larger computer system. A control store memory, loaded at system initialization time, holds fixed-length instructions simultaneously executed by dual reduced instruction set (RISC) microprocessors which interface with the multiple stations over a bi-directional bus. The master microprocessor compares the result of the processing of each instruction with the slave microprocessor's result to detect any differences, thereby minimizing error latency. Master and slave microprocessors each control half of the stations on the bus. Data widths of 32-bit and 36-bit words are supported by the microprocessors, bus, and stations.

SCSI bus extension system for controlling individual arbitration on interlinked SCSI bus segments

Abstract: This digital communication method and system permits extended distance communication on a SCSI bus despite the time constraints imposed on certain bus operations such as arbitration. The bus system is comprised of discrete bus segments each having a portal node and one or more devices interfaced thereon. All nodes are connected together by a serial link. Each node seizes control of its bus segment and imposes a pseudo-busy condition to prevent bus operations such as arbitration. A token message passed over the serial link between nodes allows one node at a time to release control of its segment to permit arbitration among the devices interfaced on its segment. A source device on the released segment that gains control of the segment as a result of arbitration may communicate with a destination device anywhere on the bus system.

Method and apparatus for entering a low-power mode and controlling an external bus of a data processing system during low-power mode

Abstract: A method and apparatus for placing a data processor (12) into a low-power mode of operation using a system (10). The system (10) has a processor (12). The processor (12) has access to a bus (18). The bus (18) is coupled to a bus controller (14). The processor (12) sends a broadcast cycle out through the bus (18) when the processor (12) desires to enter a low-power mode of operation. The bus controller (14) determines that the broadcast cycle has been sent on the bus (18). The bus controller (14) waits a predetermined amount of time to process the low-power request and grants permission to the processor (12) to enter the low-power mode via the communication of a transmission termination signal. The processor (12) conditionally drives either logic ones or a tri-state value onto the bus (18) depending upon whether or not the processor (12) has been granted ownership of the bus (18).

Process control communications: Token bus, CSMA/CD, or token ring?

Abstract: This paper discusses the features of the token bus network, with special consideration given to its suitability for use as the communications backbone for process control applications. Comparisons are given between the token bus network and its chief rivals for use in process control, the token ring and the popular Carrier Sense Multiple Access with Collision Detection (CSMA/CD) network, commonly implemented as Ethernet.

Multiple cluster signal processor architecture

Abstract: A signal processor architecture that comprises a data network having multiple ports, a control bus, and a plurality of signal processing clusters connected to at least two ports and the control bus. Each signal processing cluster comprises a system control processor connected to the control bus, a second control bus, and a global bulk memory having multiple ports. A plurality of functional processing elements are connected to the system control processor by way of the second control bus, and each are connected to a port of the global bulk memory. The global bulk memory comprises a subdata flow network having multiple gateways and full crossbar interconnectivity between each of the multiple gateways. The data network and subdata flow network allow data to be transferred between functional processing elements in the signal processing cluster and any functional processing element and global bulk memory in another signal processing cluster, and allow data to be transferred from any functional processing element into and out of the processor architecture. The first control bus is arbitrated for access on a message by message basis and the data network is arbitrated on a message by message basis for transfers between ports. This results in a relatively loose coupling between the signal processing clusters. The second control bus is arbitrated for access on a word by word basis and the global bulk memory is arbitrated for port access on each global bulk memory cycle. This results in tight coupling within each signal processing cluster.

Structure and method for combining PCM and common control data on a backplane bus

Abstract: A method for transporting common control data on a backplane bus under the SONET standard uses the section and line overhead bytes. A unit is assigned a predefined number of time slots during in the STS-1 synchronous payload envelope to assert a data transmission request on a request/acknowledge bus. Each unit keeps queue and count-down counters for monitoring, respectively, the total number of pending packets in the system and the number of packets ahead of the unit's own queued transmission. This method is implemented on a PCM bus using a transmission circuit and a receiving circuit.

Network hub for maintaining node bandwidth in a single-node network

Abstract: A hub network system is provided for communication between nodes. The system can be used, e.g., when one node can be configured for baseband bus topology communication, such as LocalTalk™ communication. The node can communicate using the entire bandwidth of the medium, such as 230 Kbps bandwidth, even though other nodes are connected to the network using the hub card. Preferably, the hub card includes a multiprocessor system with a shared memory for providing high internal effective bandwidth communication, such as 15 Mbps communication. A proxy scheme is provided so that the hub topology is transparent to any node which can operate as though it were configured in a bus topology.

Method and apparatus for monitoring and switching over to a back-up bus in a redundant trainline monitor system

Abstract: A method A and apparatus for monitoring and switching over from a primary bus to a back-up bus in a network having a master node and at least one slave node, the primary bus and the back-up bus each interconnecting the master node and the at least one slave node. The method includes periodically sending via the back-up bus from the master node to each of the slave nodes a master test packet containing a master address of the master node on the back-up bus and sending on the back-up bus from the at least one slave node to the master node and in response to receiving the master test packet, a slave test packet containing a slave address of the at least one slave node on the back-up bus. The method further includes indicating failures on the primary and back-up bus and disconnecting the primary bus from the master node and the at least one slave node and resuming communications between the master node and the at least one slave node via the back-up bus when a failure occurs on the primary bus and no failures occur on the back-up bus.

Circuit for providing automatic SCSI bus termination

Abstract: Disclosed are a circuit and method for providing automatic termination for a small computer systems interface ("SCSI") bus. The circuit resides within a bus controller comprising (1) a control circuit for controlling transmission of data on a bus and for providing an interface between the bus and a computer system for communication of the data therebetween and (2) a first bus port and a second bus port, each of the first and second bus ports permitting a device to be coupled thereto for communication with the control circuit via the bus, the bus controller being at an end of the bus when a single one of the first and second bus ports is coupled to a device and being in a middle of the bus when both the first and second bus ports are coupled to devices. The circuit of the present invention is coupled to the first and second bus ports and is capable of coupling a terminating circuit to the bus as a function of a presence of devices coupled to the first and second bus ports, the bus requiring coupling of the terminating circuit when the bus controller is at the end of the bus.