Showing papers on "Carry flag published in 2015"

All-Optical Binary Full Adder Using Logic Operations Based on the Nonlinear Properties of a Semiconductor Optical Amplifier

Abstract: We propose a new and potentially integrable scheme for the realization of an all-optical binary full adder employing two XOR gates, two AND gates, and one OR gate. The XOR gate is realized using a Mach-Zehnder interferometer (MZI) based on a semiconductor optical amplifier (SOA). The AND and OR gates are based on the nonlinear properties of a semiconductor optical amplifier. The proposed scheme is driven by two input data streams and a carry bit from the previous less-significant bit order position. In our proposed design, we achieve extinction ratios for Sum and Carry output signals of 10 dB and 12 dB respectively. Successful operation of the system is demonstrated at 10 Gb/s with return-to-zero modulated signals.

Power and area efficient carry select adder

Abstract: Carry select adder (CSLA) is one of the fastest adders used in many data processing systems. By eliminating the redundant logic operations in the conventional CSLA the area and power can be reduced. Logic optimization is done by providing a separate carry generator for final carry bit of each block in the SQRT CSLA. Using this logic optimization technique an area and power efficient architecture is obtained for carry select adder. The carry select operation is scheduled prior to the final sum calculation. This CSLA design has less area and power consumption among the existing CSLA system.

Error control on spectral data of four-wave mixing based on a-SiC technology

Abstract: In this paper we exploit the nonlinear property of the SiC multilayer devices to design an optical processor for error detection that enables reliable delivery of spectral data of four-wave mixing over unreliable communication channels. The SiC optical processor is realized by using double pin/pin a-SiC:H photodetector with front and back biased optical gating elements. Visible pulsed signals are transmitted together at different bit sequences. The combined optical signal is analyzed. Data show that the background acts as selector that picks one or more states by splitting portions of the input multi optical signals across the front and back photodiodes. Boolean operations such as EXOR and three bit addition are demonstrated optically, showing that when one or all of the inputs are present, the system will behave as an XOR gate representing the SUM. When two or three inputs are on, the system acts as AND gate indicating the present of the CARRY bit. Additional parity logic operations are performed using four incoming pulsed communication channels that are transmitted and checked for errors together. As a simple example of this approach, we describe an all-optical processor for error detection and then provide an experimental demonstration of this idea. (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Low power pipelined 8-bit RISC processor design and implementation on FPGA

Abstract: RISC is a design technique used to reduce the amount of area required, complexity of instruction set, instruction cycle and cost during the implementation of the design. This article presents a simple 8-bit RISC processor design and implementation on Spartan-6 SP605 Evaluation Platform FPGA using Verilog Hardware Description Language (HDL). The processor is designed using Harvard architecture, having separate instruction and data memory. Its most important feature is that its instruction set is very simple, contains only 29 instructions, which is easy to learn. Another important feature is pipelining, used for improving performance, such that on every clock cycle one instruction will be executed. In RTL coding one can reduce the dynamic power by using clock gating technique, is used for specific modules which be clocked only when it is required. The proposed processor has 8-bit ALU, Two 8-bit I/O ports and Eight 8-bit general purpose registers and 4-bit flag register having zero flag, carry flag, borrow flag and parity flag and will work on 2.5 voltage supply. The interrupt module contains two interrupts, which are priority based and one of the interrupt is mask able. Another advantage of the proposed processor is that it executes programs with up to 262,144 instructions, such that any practical programs can be fitted into it. The proposed processor is physically verified on Xilinx Spartan-6 SP605 Evaluation Platform with 0.0564µs instruction cycle.

Error Detection on a Spectral Data Using an Optical Processor Based on a-SiC Technology

Abstract: In this paper, we exploit the nonlinear property of the SiC multilayer devices to design an optical processor for error detection that enables reliable delivery of spectral data of four-wave mixing over unreliable communication channels. The SiC optical processor is realized by using double pi'n/pin a-SiC:H photodetector with front and back biased optical gating elements. Visible pulsed signals are transmitted together at different bit sequences. The combined optical signal is analyzed. Data show that the background act as selector that pick one or more states by splitting portions of the input multi optical signals across the front and back photodiodes. Boolean operations such as EXOR and three bit addition are demonstrated optically, showing that when one or all of the inputs are present, the system will behave as an XOR gate representing the SUM. When two or three inputs are on, the system acts as AND gate indicating the present of the CARRY bit. Additional parity logic operations are performed using four incoming pulsed communication channels that are transmitted and checked for errors together. As a simple example of this approach, we describe an all-optical processor for error detection and then provide an experimental demonstration of this idea. Copyright © 2015 IFSA Publishing, S. L.

Design and Analysis of a High Speed Carry Select Adder

Abstract: An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each sum bit, which are then used to select the respective multiplexer (MUX) which adds the carry bit to the sum accordingly. The proposed adder has been synthesized with bulk 40 nm standard CMOS library on Synopsys Design Compiler. Analysis has indicated the superiority of proposed adder over CLAA and CSA. As compared to CSA and CLAA, the proposed Carry Select Ahead Adder (CSAA) provides shorter average path and a simpler hardware. This has led to faster processing speed by increasing the complexity of circuit on the chip. The proposed adder finds its applications in various Arithmetic and Logic Units (ALU) of CPUs for faster arithmetic results. Keywords—Carry Look Ahead Adder (CLAA), Carry Select Adder (CSA), Multiplexer (MUX), Carry Select Ahead Adder (CSAA), Arithmetic and Logic Unit (ALU).

High performance 8bit cascaded carry look ahead adder with precise power consumption

Abstract: Multiple bit adders like ripple carry adder make the propagation of carry bit very slow and this is the reason why it must be replaced with fast adders as carry-look-ahead adder CLA. Power consumption in digital circuits depends on the number of metal-oxide-semiconductor field-effect transistor employed and various other parameters. If number of metal-oxide-semiconductor field-effect transistor is reduced the power consumption would definitely be reduced. Conventional CLAs would consume significant amount of power that still needs to be improved. The paper here deals with the implementation of 8bit CLA with the aim of reducing the size and to precise the power consumption within nanowatt range, by improving the fundamental components of the circuit. All the parameters have been calculated by using Cadence Virtuoso tool at 45nm technology. Copyright © 2014 John Wiley & Sons, Ltd.

Method for producing pixel color level value

Abstract: A method for generating pixel color level value performed by a timing controller is disclosed. The method divides the pixel level value of a first color into the most significant bit part as well as the least significant bit part. The least significant bit part is divided into several value types, and a number of the original binary tables are produced based on the value types, each of which contains several carry bit and several non-carry bit. Next, part of the original binary tables are inverted to produce an intermediate state binary table, the rest part of the original binary tables remain unchanged. After that, the intermediate state binary table is transformed in order to obtain a final binary table. The MSB part of the pixel color level value is adjusted according to the rest part of the original binary tables and the final binary table.

Multi-core processor, system on chip, and mobile phone

Abstract: PROBLEM TO BE SOLVED: To provide a new rotate instruction which is different from the prior art and excellent in speed and/or efficiency without reading an arithmetic flagSOLUTION: An instruction decoder 104 receives and decodes a rotate instruction The rotate instruction indicates a source operand and a rotate amount An execution unit 106 stores result in a destination operand indicated by the rotate instruction The result has the source operand rotated by the rotate amount Execution of the rotate instruction is completed without reading a carry flag 116SELECTED DRAWING: Figure 1