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Showing papers on "Channel length modulation published in 1977"


Journal ArticleDOI
TL;DR: In this paper, a new MOSFET structure with a trapezoidal U-shaped channel defined by anisotropic etching is described, which results in very short channel devices almost free of short channel effects and achieves higher speed.
Abstract: A new MOSFET structure with a trapezoidal U-shaped channel defined by anisotropic etching is described. The structure results in very short channel devices almost free of short channel effects and achieves higher speed without the use of submicron photolithography. A simplified theory for the structure is presented and compared with experimental results obtained on 1–10 μm channel length devices. This structure may prove useful in the study of conduction in short channel MOSFETs without introducing the complicating two dimensional short channel effects.

30 citations


Journal ArticleDOI
TL;DR: In this paper, the effects of the source and drain depletion regions on the energy band configuration and the effective depletion layer charge under the channel were modeled for short channel effects in MOS transistors.
Abstract: We present a theory which models short-channel effects in MOS transistors (MOST) Our approach accounts for the effects of the source and drain depletion regions on the energy band configuration and the effective depletion layer charge under the channel We derive an equation for low drain bias threshold voltage which accurately predicts the measured threshold on devices ranging in size from very small (15 μm) to very large (100 μm) effective channel lengths The equation reliably predicts the phenomenon of decreasing threshold voltage and body effect observed experimentally from devices of decreasing channel length The equation is valid for any bulk silicon MOS technology provided that the substrate doping is approximately uniform (ie ion-implantation has not been used to adjust the threshold) Our approach can be applied directly to the modeling of the short-channel drain to source current This application of the theory will be presented in a later paper

20 citations


Patent
Albert Watson Vinal1
01 Jul 1977
TL;DR: In this paper, a high sensitivity, low noise, broad bandwidth channel conduction field sensor device is described, where the conductive channel is configured to create an exceptionally narrow, undepleted conduction channel of approximately filamentary form.
Abstract: A high sensitivity, low noise, broad bandwidth channel conduction field sensor device is described. The conductive channel is configured to create an exceptionally narrow, undepleted conduction channel of approximately filamentary form. The filamentary conductive channel so formed is provided with a source at one end of the channel and two or more laterally spaced drains at the other end thereof. Electric or magnetic fields may be utilized to deflect a stream of charge carriers traversing the conductive channel from the source toward the drains utilizing the depletion width modulation effect of the fields upon the boundaries defining the conductive channel portion. Modulation of the depletion zone width and depth along the channel sides effectively moves the stream of carriers and the conductive channel area to overlap one drain more than another. This develops a differential drain current balance which can be utilized to provide an output signal. Width and length criteria for defining a filamentary channel structure are described for the ultimate desired configuration and size which are to be obtained. As noted, operation of the device is based upon modulation of the width and depth of the depletion zone boundaries defining the conductive channel. An increased signal output is obtained by reducing the width of the channel to eliminate excess carriers normally found in wide channel devices and, further, by making the depletion zones as large a portion of the total channel width as can be obtained.

20 citations


Patent
10 Aug 1977
TL;DR: In this article, a stable temperature-insensitive constant reference voltage circuit is provided which can be implemented in either MOS or bipolar technology, where the circuit is implemented by MOSFET devices on a single chip with another circuit such as an A/D converter.
Abstract: A stable temperature-insensitive constant reference voltage circuit is provided which can be implemented in either MOS or bipolar technology The circuit may be implemented by MOSFET devices on a single chip with another circuit such as an A/D converter to provide a monolithic A/D converter with its own internal reference voltage circuit The reference voltage circuit consists of a series-connected long channel MOSFET and short channel MOSFET which produce, at their junction, a temperature-independent voltage A differential circuit containing three MOSFET devices is then provided with one of the devices serving as a current source which carries the current of the other two MOSFET devices which are in parallel The gates of the two parallel MOSFET devices are connected respectively to the junction between the long channel and short channel device and to the output voltage Current divides between the two parallel MOSFET devices in such a way as to cause a constant output voltage to be produced regardless of the variations of the supply voltage sources Vdd or Vgg The various MOSFET devices are formed on the same substrate containing the circuit components being connected to the constant stable voltage reference source

18 citations


Journal ArticleDOI
TL;DR: It is found that conventional models inadequately simulate the output conductance of the devices in saturation, and the new channel length modulation model is accurately simulated for channel lengths ranging from 0.6 to 2.0 /spl mu/m.
Abstract: Double-diffused MOS (DMOS) and V-groove MOS (VMOS) transistors have been simultaneously fabricated in order to investigate the effects of impurity profiles on device performance. Processing parameters are varied to achieve a range of channel lengths and peak channel dopings. The resulting impurity profiles are measured by the two point probe spreading resistance method. Properties of the lateral DMOS impurity profile are inferred from a comparison of the electrical characteristics of the VMOS and DMOS devices. It is found that conventional models inadequately simulate the output conductance of the devices in saturation. An expression for channel length modulation is derived from a one-dimensional solution of Poisson's equation in the region surrounding the channel-drain junction. When measured impurity profile data are incorporated into the new channel length modulation model, the output conductance of the devices is accurately simulated for channel lengths ranging from 0.6 to 2.0 /spl mu/m.

12 citations


Patent
19 Jul 1977
TL;DR: In this paper, a field effect transistor has the property that the product of its series resistance and true transconductance is less than one throughout the entire range of drain voltage in the operative state of the transistor, the series resistance being the sum of the resistance from source to channel and the resistance of this channel.
Abstract: A field effect transistor has the property that the product of its series resistance and its true transconductance is less than one throughout the entire range of drain voltage in the operative state of the transistor, the series resistance being the sum of the resistance from source to channel and the resistance of this channel. In order to prevent an excessive increase in the active resistance of the channel, the channel is made to have an impurity concentration as low as less than 1015 atoms/cm3, preferably less than 1014 atoms/cm3, so that the depletion layers extending from the gates grow extensively to become contiguous in response to a small increase in the reverse gate voltage applied. As a result, the field effect transistor of this invention has an unsaturated drain current versus drain voltage characteristic.

11 citations


Patent
Ernest A. Carter1
06 Jun 1977
TL;DR: In this paper, the authors describe a MOS circuit with a first MOSFET having its gate connected to an input and a second depletion mode having its drain connected to the source of the first one and its source connected to ground.
Abstract: An MOS circuit possessing hysteresis and positive feedback for fast switching includes a first MOSFET having its gate connected to an input. A second depletion mode MOSFET has its drain connected to the source of the first MOSFET and its source connected to ground. A third depletion mode MOSFET has its drain connected to the source of the first MOSFET and its gate and source connected to the drain of a fourth MOSFET and to the gate of a fifth MOSFET. The gate of the fourth MOSFET is connected to the gate and source of a sixth depletion mode MOSFET and to the drain of the fifth MOSFET. The fifth MOSFET has its source connected to ground.

8 citations


Proceedings ArticleDOI
E.A. Valsamakis1
01 Jan 1977
TL;DR: The MOSFET equivalent circuit model described in this article incorporates short channel and temperature effects and includes expressions for the device current in the subthreshold, triode and saturation regions and uses a field dependent mobility and a drain voltage dependent threshold voltage.
Abstract: The MOSFET equivalent circuit model described incorporates short channel and temperature effects. It includes expressions for the device current in the subthreshold, triode and saturation regions and uses a field dependent mobility and a drain voltage dependent threshold voltage. The drain current-voltage characteristic and its first derivative are continuous in all regions. Relationships for the gate-source and gate-drain capacitances are derived as a function of the device potentials using a field dependent mobility. Using the closed form expressions of this model, simulations were performed for micron long devices having uniform and ion-implanted channel profiles and compared with data at room, above room and liquid nitrogen temperature.

6 citations


Patent
08 Nov 1977
TL;DR: In this article, the output voltage of high potential with the input signal of low voltage was obtained by constituting C-MOS inverter circuit with MOSFET of P and N channels, further providing N channel MOS FET and applying the output signal of opposite phase to the gate.
Abstract: PURPOSE:To obtain the output voltage of high potential with the input signal of low voltage, by constituting C-MOS inverter circuit with MOSFET of P and N channel, further providing N channel MOSFET and applying the input signal of opposite phase to the gate. CONSTITUTION:C-MOS circuit is constituted with the P channel MOSFET T21 200V or more in dielectric strength and the N channel MOSFET T22 having the same breakdown voltage. Further, branching resistors R21 and R22 are provided, the junction point is connected to the gate of the element T21, and one end is connected to the gate of the element T22 via the inverter INV consisting of C-MOS via the N channel MOSFET T23. With this constitution, the power supply VDD is applied to the element T21 and the resistor R21, and when the input VIN is fed to the element T23 and the inverter INV, high voltage output signal having opposite phase as the input signal is appeared at the output Vout.

5 citations


Patent
04 Jan 1977
TL;DR: In this article, a field effect transistor with a small channel width is used to achieve desired chanel impedance values independently of threshold voltage influence due to narrow channel width effect by the provision of parallel-connected field effect transistors.
Abstract: a field effect transistor having a channel width of such small dimension that threshold voltage becomes inversely related to channel width allowing the fabrication of field effect transistors of differing threshold voltages while using the same process steps. Reduced threshold voltage due to prior art "short channel length" effect may be offset by the presently disclosed narrow channel width effect. Desired chanel impedance values are achieved independently of threshold voltage influence due to narrow channel width effect by the provision of parallel-connected field effect transistors of the same channel length whose total channel widths yield a desired net width-to-length ratio.

3 citations


Journal ArticleDOI
01 Dec 1977
TL;DR: In this paper, the effect of inseparable channel resistance near the input source electrode in field effect transistor is studied experimentally by varying an added external resistance in the source electrodes, and it is shown that this resistance behaves like negative feed-back network due to its nonlinear character until input and output of the device are isolated completely where channel potential is lower than the source potential and the semiconductor bulk is depleted completely.
Abstract: The effect of inseparable resistance present near the input source electrode in field effect transistor is studied experimentally by varying an added external resistance in the source electrodes. Device physics indicates that this resistance behaves like negative feed-back network due to its non-linear character until input and output of the device are isolated completely where channel potential is lower than the source potential and the semiconductor bulk is depleted completely. In such situations, the effect of non-linear channel resistance is minimized and it behaves precisely as a lumped series resistance. It is explained further that the channel resistance affects the potential profiles of the device till input and output are isolated and it is not the only major factor responsible for current saturation in JFET, but device dimensions, channel doping profile and material properties also contribute significantly. Thus, the potential profile in effect controls the device characteristics of the majority carrier semiconductor devices.


Journal ArticleDOI
TL;DR: In this paper, a new method to determine the threshold voltage for VDS = 0 V was discussed, which is based on the square root extrapolation method in the saturation region in a short-channel MOSFET.
Abstract: It has been well known that in a long‐channel MOSFET, the experimental value of the threshold voltage obtained by the square‐root extrapolation method in the saturation region agrees well with the theoretical criterion. In a short‐channel MOSFET, the so‐determined threshold voltage depends on the drain voltage because of the drain current dependence on the drain voltage VDS. In this letter, a new method to determine the threshold voltage for VDS=0 V will be discussed.

Journal ArticleDOI
01 Jun 1977
TL;DR: In this article, the performance characteristics of a junction field effect transistor (jfet) were evaluated considering the presence of the gap between the gate electrode and the source and drain terminals, and it was concluded that the effect of gap is to demand a higher drain voltage to maintain the same drain current.
Abstract: The performance characteristics of a junction field-effect transistor (jfet) are evaluated considering the presence of the gap between the gate electrode and the source and drain terminals It is concluded that the effect of the gap is to demand a higher drain voltage to maintain the same drain current So long as the device is operated at the same drain current, the presence of the gap does not change the performance of the device as an amplifier The nature of the performance of the device as a variable resistor is not affected by the gap if it is less than or equal to the physical height of the channel For gap lengths larger than the channel height, the effect of the gap is to add a series resistance in the drain