Showing papers on "Circuit diagram published in 1991"

Layout designing method for a semiconductor integrated circuit device

Abstract: In a layout designing method for an LSI by a CMOS standard cell method, layout cells (standard layout patterns) which respectively correspond to logical function units are selected from a library. In this selection, the respective layout cells are selected from the library as patterns which are divided into p-type layout cells and n-type layout cells. The p-type layout cells and the n-type layout cells are arranged in accordance with a predetermined logical circuit diagram. Interconnection patterns for interconnecting the p-type layout cells and for interconnecting the n-type layout cells are arranged in accordance with the logical circuit diagram. An excessive interconnection region can be minimized, and efficient interconnections can be achieved. Therefore, an occupied plane area can be reduced in the layout design.

Low-entropy expressions: the key to design-oriented analysis

Abstract: It is pointed out that the perception of many electronics design engineers is that they are able to apply a few of the formal analysis methods they have been taught, and are largely unprepared for the realization that design is the reverse of analysis. The author suggests a different perspective for teaching, based on the premise that only analysis that is design-oriented is worth doing, and that results should be presented in low-entropy expressions. High- and low-entropy expressions are described. A simple analog circuit example illustrates one method of design-oriented analysis: doing the algebra on the circuit diagram. >

Linearization techniques for nth-order sensor models in MOS VLSI technology

Abstract: The authors present new linearization techniques and introduce novel circuits for second- and third-order sensor models. Furthermore, a general framework as well as circuit techniques for linearization of sensor models of any order are presented. The new techniques are based on subtle circuit design of simple and compact multiplier/divider and vector multiplier circuits that comprise op-amps and MOS transistors. The design is programmable using DC control voltages and is capable of implementing different values of model parameters using identically sized devices without altering physical circuit layout. The resulting continuous-time signal processing circuits are completely compatible with MOS VLSI technology and easy to incorporate in a computer-aided design environment. The circuit design details are given and nonideal effects due to op-amp dynamics and MOS parasitic capacitances are investigated. Experimental results for the new second-order sensor models, obtained from a MOSIS 2- mu m CMOS process test chip, and SPICE simulation results of third-order models verify the validity of the proposed linearization techniques. >

LiB: a CMOS cell compiler

Abstract: An automatic layout generation system, called LiB, for the small-scale integrated (SSI) cells used in CMOS VLSI design, is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a mask layout in CIF. The layout style is a modification of that proposed by T. Uehara, and W. M. van Cleemput (IEEE Trans. Comput., vol.C-30, no.5, p.305-12, 1981). An optimal transistor chaining algorithm has been developed to derive a transistor placement with a minimum number of diffusion separations. To meet the cell height constraint, large transistors are folded into multiple columns algorithmically. The whole cell is divided into five routing regions. Two are on the diffusion island and the others are rectilinear-shaped routing channels. A graph-theoretic method for selecting nets (subnets) for routing on the diffusion island is proposed. A global routing algorithm has been developed to assign the remaining nets to the three rectilinear channels. For the detailed routing SILK, a simulated evolution router, is employed. LiB can be used as a cell library builder or as a subsystem of a random logic module generator. Users can alternate LiB's layout using a symbolic editor. >

A technology-independent approach to custom analog cell generation

Abstract: STAT (schematic to artwork transistor), a set of software tools designed to generate full-custom layouts of analog cells from arbitrary schematic topologies in any IC technology, is described. The system enables the circuit designer to annotate the schematic with component matching and symmetry relationships. Software subroutines are then used to generate device artwork. The placement program implements algorithms in which groups of related components are placed first so that annotated layout constraints are preserved. A novel placement method is offered which recognizes that analog schematic topologies often reflect desirable layout configurations. A flexible multilayer cell-level router has been developed to complete the device interconnection. The STAT system functions in either a polygon or symbolic layout environment. The symbolic layout allows design-rule and technology changes to be made easily and is designed to interface with a commercial compaction program to produce the final layout. >

Semiconductor integrated circuit fabrication method

Abstract: A semiconductor integrated circuit fabrication method for designing and fabricating semiconductor circuit elements on a semiconductor substrate for a LSI, which comprises the steps of: drawing a semiconductor circuit diagram by arranging standard cells for the semiconductor circuit elements and wiring among the standard cells by using a standard cell design method; describing circuit description net statements based on the semiconductor circuit diagram; arranging and wiring the standard cells to one another; converting the standard cells into symbolic cells with a one-to-one correspondence to generate a symbolic cell layout; generating a stick diagram in accordance with the symbolic cell layout; changing the dimensions of each transistor in the symbolic cell, overlapping contact areas, vias among them, and wires between adjacent transistors in the symbolic cells as a common area, where possible, shortening the length of wire in the transistor, and changing the sliding of the contact area, the vias, and the wire of the transistor to obtain the minimum area for the transistor; forming a mask pattern in accordance with the arranging and wiring of the symbolic cells obtained by the above steps; and forming the semiconductor circuit elements and wiring among the semiconductor circuit elements on the semiconductor substrate by using the mask pattern.

Logic design system and method in the same

Abstract: In a system for transforming input circuit information into information of a logic circuit composed of actual elements, a schematic diagram of a logic circuit composed of actual elements is displayed. A timing check is executed on the displayed logic circuit. A delay adjustment portion of the displayed schematic diagram is designated. A timing adjustment is executed by the system on the designated delay adjustment portion, and thereby the logic circuit is transformed into a second logic circuit composed of actual elements.

Method and system for propagating data type for circuit design from a high level block diagram

Abstract: A computer aided design system for electronic digital circuitry allows the circuit designer to design a circuit using high level block components, The designer specifies data type and precision (bus width) parameters as desired for whichever circuit blocks and/or busses he desires, Then the system propagates the data types and precision throughout the design automatically to achieve circuit-wide consistency, The system can also be used to verify a circuit design for data type and bus width consistency, The system can also be used to determine the mode of operation for the circuit blocks in the circuit.

Design aid method and design aid apparatus for integrated circuits

Abstract: Disclosed is a design aid apparatus for integrated circuits, which includes an input section for inputting design data, concerning a circuit to be designed, by means of diagrams or by means of language descriptions; a design section for designing a circuit in accordance with language input design data so as to prepare language design circuit data, and for preparing diagram design circuit data corresponding to the language design circuit data, or for designing a circuit in accordance with diagram input design data so as to prepare diagram design circuit data, and for preparing language design circuit data corresponding to the diagram design circuit data; and a holding section for storing and holding both the language design circuit data and the diagram design circuit data from the design section.

LSI design support system

Abstract: Disclosed is an LSI design support system for making a functional design of LSI using a graphic input method. This system comprises a state transition diagram preparation portion for preparing a state transition diagram, state transition table preparation portion for preparing a state transition table, and a state-operation circuit diagram preparation portion for preparing a state-operation circuit diagram. Data from these preparation portions are examined therebetween and the results are displayed at the same time on a picture plane so that a designer can efficiently make a design on circuit operation including its state transition. Also disclosed is another LSI design support system. As well as the preparation portions in the above system, this system comprises a transitional-condition analysis portion for analyzing transitional conditions of a state transition diagram obtained by the state transition diagram preparation portion or a state transition table obtained by the state transition table, an automatic-layout-wiring program execution portion for preparing a state transition diagram by data from the state transition table, and an automatic-table-preparation program execution portion for preparing a state transition table by data from the state transition diagram.

Technology mapping apparatus for a combination circuit for use in automatically synthesizing an LSI logic circuit

Abstract: A graph converter converts functionally descriptive information expressing a combination circuit into a graph expression having only NOR and inversion circuits. A multiple input NOR converter detects from the above graph expression a circuit element having a NOR circuit and an inversion circuit alternately connected in series and converts the circuit element to a graph expression where a multiple input NOR circuit replaces the circuit element. A cell mapper detects from the above graph expression a circuit element having NOR circuits connected together in series, maps the circuit element to gate cells with or without a composite cell, and outputs the mapping result with the least number of gates as the mapping output for the circuit element. A circuit element having a NOR circuit and an inversion circuit alternately connected in series is substituted by a unique multiple input NOR circuit. A circuit element mapped to a composite cell is efficiently determined just by detecting a circuit element where "nor" circuits are connected together in series. It is possible to replace NOR circuits by NAND circuits.

Semiconductor integrated circuit of standard cell system

Abstract: Transistor elements which are not initially wired are previously arranged in no-cell regions created in part of cell array regions in a standard cell layout according to the layout design. When the circuit is changed in the standard cell layout, a desired circuit is formed in the no-cell region by using the transistor elements which are not initially wired. After the circuit change, an unnecessary circuit is made inoperative. Wiring inhibition regions for inhibiting the normal wiring in the standard cell layout are provided in order to extend the input and output terminals of the desired circuit from the no-cell region to the wiring region.

Method of layout processing including layout data verification

Abstract: A method of processing layout data of an integrated circuit including several circuit blocks and inter-block routing among the circuit blocks on data verification. The method includes the steps of processing layout data within at least one of the circuit blocks and replacing the layout data within that circuit block with layout data in a peripheral neighborhood region of that circuit block to process the replaced layout data.

Optoelectronic approach to on-chip device and circuit characterization at microwave and millimeter-wave frequencies

Abstract: A practical technique for characterizing high-frequency semiconductor devices and monolithic integrated circuits has been developed, with specific emphasis on eliminating one of the primary concerns affiliated with conventional approaches, namely the often insufficient predictability of conditions at interfaces between measurement system and device under test. Arrays of high-speed photoconductive circuit elements, in conjunction with special compensation networks, are thereby utilized to implement, on chip, all signal generation and sampling functions needed to efficiently perform time-domain reflectometry. The acquired time-domain information is then converted into equivalent device-under-test scattering parameter responses. The practicability of the approach is experimentally demonstrated with the help of five individual test structures that are realized in monolithic-integrated-circuit format on a GaAs substrate and operate over a full, uninterrupted 100-GHz frequency interval. >

Programmable logic device with circuit portions common to both configuration and use circuits

Abstract: In a programmable logic device having a memory circuit for storing circuit configuration data and a logic gate block for realizing a logic circuit desired by a user on the basis of the circuit configuration data written into the memory circuit, a switching circuit is provided for controlling at least a part of a circuit for writing the circuit configuration data into the memory circuit so as to be utilized as a part of the logic circuit desired by the user after the circuit configuration.

Circuit simulations combined with the electromagnetic field analysis

Abstract: In order to provide a means of rigorous simulation for wideband nonlinear microwave integrated circuits, the concept of a lumped device model is introduced into a three-dimensional, time-domain electromagnetic field analysis method This makes it possible to perform both a circuit simulation including nonlinear lumped devices and an electromagnetic field analysis for distributed microwave components at the same time As an example, the generation of picosecond pulses from a nonlinear transmission line circuit is simulated Based on the results, the features and the validity of the method are discussed in comparison with conventional circuit simulations >

An improved state diagram

Abstract: The conventional state diagram for a synchronous sequential circuit places the circuit's output labels on arrows representing state transitions. This notation leads students to think that the labels denote output values during, or associated with, changes of state; in fact, the output is not defined when the state is changing. The misconception fostered by this notation creates difficulties for students when they encounter real circuits. A state diagram is proposed which clarifies signal timing by associating outputs with states, and not with state transitions. The proposed diagram provides a number of additional benefits. It includes markedly fewer transition labels, enabling one to design larger systems before the diagram becomes too cluttered to handle. The construction of next state and output maps is simplified. The proposed diagram readily admits register-transfer notation, and thus serves as the initial step in the design of a wired controller. The authors have employed the proposed diagram successfully in elementary and advanced classes in logical design.

Variable frequency two‐phase ac susceptometer for use in dc bias fields over the temperature range of 4.2 to 300 K

Abstract: A system has been designed and constructed in order to detect differential ac susceptibility as a function of temperature between 4.2 and 300 K. A dc bias field in the range of 0–50 kOe is provided by a superconducting magnet. The available ac field range is 0–1 Oe. Using the reference source of a PAR lock‐in amplifier, the measurements can be carried out in a frequency range of 0.1–10 kHz. A differential amplifier circuit is used to accurately detect the susceptibility signal. As this provides both in‐phase and out‐of‐phase compensating signals, both the real and imaginary components of the susceptibility can be detected even when using a single‐phase lock‐in amplifier. The circuit diagram and principle of operation as well as the calibration procedure and data processing methods are described in detail.

Monolithic circuit for reflection coefficient measurement

Abstract: A monolithic circuit for measuring the complex reflection coefficient using fixed-probe voltage sampling has been investigated. Ion-implanted GaAs Schottky diodes, with built-in isolation resistance, have been used as voltage samplers along a microstrip transmission line on semi-insulating GaAs. An algorithm for determining reflection coefficient from three detected DC voltages is described. Circuit analysis and modeling, DC voltage calculations, and experimental results for the 5-18 GHz frequency range are presented. >

A 0.5-12 GHz hybrid matrix distributed amplifier using commercially available FETs

Abstract: A matrix distributed amplifier for a coherent high-bit-rate optical receiver front-end is presented. A gain of 20 dB in the 0.5-12 GHz range with a noise figure of 5-8 dB over the whole frequency range has been obtained together with a low voltage standing wave ratio. The layout is very simple in comparison to other hybrid realizations reported in the literature and is fully related to the lumped elements of the circuit schematic. The computed results obtained using a small signal model for each FET agree rather well with measurements. >

Verification of integrated-circuit mask pattern

Abstract: PURPOSE:To deal with even a disagreement to be caused regarding a resistance element between a mask pattern and a circuit diagram on the basis of a request from the viewpoint of a design by a method wherein a plurality of resistance elements on an integrated-circuit mask pattern are replaced with an equivalent single resistance element and this element is compared with the circuit diagram and verified. CONSTITUTION:Information on connections of individual elements T1 to T6, R, R' is extracted from a circuit diagram as first information on connections; information on connections of individual elements is extracted from an integrated-circuit mask pattern as second information on connections. Information on connections regarding resistance elements R1 to R6 is extracted from the second information on connections; a plurality of resistance elements which fulfill a function equivalent to a single resistance element as an electric circuit are recognized; the second information on connections is corrected in such a way that the plurality of resistance elements are replaced with an equivalent single resistance element. The second information on connections which has been corrected is compared with the first information on connections and verified. Thereby, even when a single resistance element is replaced with the plurality of resistance elements during a design of a mask pattern, a disagreement is not judged as a result of a comparison and a verification.

Method for forming circuit diagram data

Abstract: PURPOSE:To prevent the generation of misconnection of a power supply by displaying a connection to a power supply symbol pin independently of a standard power supply voltage or non-standard power supply voltage at the time of displaying a circuit diagram on a display device CONSTITUTION:At the time of displaying a circuit diagram in the case of using a standard power supply voltage, connection is automatically formed, and if a power supply symbol name is specified at the time of displaying a circuit diagram in the case of using a power supply voltage different from the standard voltage, a net ID indicating the connection of the standard voltage with a power supply terminal is disconnected by a power supply symbol arranging means 1 and a power supply symbol is displayed on the display device When the displayed power supply symbol is connected to the power supply terminal of a certain voltage, the power supply symbol name, the name of a symbol pin of each power supply symbol, the pin number of the corresponding parts pin, a parts number, and a net ID code are written in a power supply functions constituting the parts of a circuit internal table by a connection writing means 2 When the power supply symbol name is not specified, the whole power supply column of a parts library is written in the circuit internal table Consequently, the generation of misconnection of the power supply can be prevented

Circuit diagram editing device

Abstract: PURPOSE:To eliminate the need to pay attention to hierarchic symbols in the designing of a logic circuit consisting of a large-scale hierarchic circuit by providing a symbol generation rule part and a hierarchic symbol generation part and generating the hierarchic symbols automatically according to a rule which is registered in advance CONSTITUTION:A designer registers the rule in the symbol generation rule part 2 so as to obtain hierarchic symbols in desired shapes A circuit diagram file 7, on the other hand, is stored with circuit information on a hierarchic circuit as an object of hierarchic symbol generation The hierarchic symbol generation part 6 inputs the rule from the symbol generation rule part 2 and then input/output information from an input/output information acquisition part 3 next, and the input/output information acquisition part 3 inputs the input/ output information from the circuit diagram information in the circuit diagram file 7 in advance The hierarchic symbol generation part 6 generates the hierarchic symbol automatically from the input/output information according to the rule Consequently, the designer only registers the rule in advance to obtain the hierarchic symbols in the desired shape

D/a converter

Abstract: PURPOSE:To decrease the number of externally mounted components and an inter-channel offset having been a problem in the case of use of plural D/A converters by unifying a D/A converter and a reference power supply in one chip, and providing separately an output terminal of the reference power supply and an input terminal for setting output amplitude CONSTITUTION:The Figure shows a circuit diagram in the case of using three sets of D/A converters Voltages VRT, VRB depending on a reference power supply built in a D/A converter 1 in (A) are applied respectively to output amplitude setting terminals VFS, VZS of each D/A converter 1 of the sets (A), (B), (C) to decide the output amplitude In such a case, since the setting voltage and the output amplitude depend on a resistance ratio inside of an IC, an inter-channel offset among the D/A converters 1 of the sets (A), (B), (C) is theoretically zero Moreover, a current IRT supplied from the built-in reference power supply of the D/A converter 1 of the set (A) is I1X3because a current I2 flowing to current SW is supplied from the inside of each A/D converter 1 The current I1 is sufficiently smaller than the current I2, the current capacity of the reference voltage source is enough to be small and the wire resistance causes no problem

Circuit diagram editor

Abstract: PURPOSE:To facilitate the confirmation of a connection state by extracting and displaying connection between optional two elements in the circuit diagram of multihierarchy and multipage structure in a circuit diagram editor provided with a circuit diagram information generating means. CONSTITUTION:The circuit diagram editor which generates circuit diagram information by the generating means 3 by an input from an input means 1 and stores this information in a storage means 4 is provided with an inter- hierarchy inter-page connection extracting means 5, and the connection between two elements from the means 1 is extracted from the circuit diagram information in the means 4, and the circuit diagram including this connection is displayed on a display means 2.

Circuit design supporting device

Abstract: PURPOSE: To obtain a circuit design supporting device which can program efficiently the procedure of an automatic design by displaying a circuit diagram charged with respective fundamental circuit data and derived circuit data, and the result of circuit simulation as a two-dimensional image. CONSTITUTION: Data for indicating a fundamental circuit and a circuit element inputted to a CPU 2 through an input part 1 consisting of a keyboard, etc., are stored as circuit information in a circuit information storage part 3. Also, the data are stored in a circuit changing information storage part 4 through the CPU 2 from the input part 1. In the CPU 2, a circuit changing means 5, a circuit constant optimizing means 6, and a circuit simulation means 7 are provided in addition to a function as a regular computer. In such a state, in the case of designing optimumly the fundamental circuit, the constitution of the fundamental circuit and a circuit constant can be optimized by referring to a characteristic obtained by executing the simulation to the fundamental circuit, and several simulation derived circuits of this fundamental circuit, and its result is displayed as a two-dimensional image on a display part 8. COPYRIGHT: (C)1993,JPO&Japio

Manufacture of semiconductor integrated circuit

Abstract: PURPOSE:To reduce an area and to automatically design a mask layout by preparing several basic disposition patterns, selecting a nearest template to positional relation of elements in a circuit diagram from them, and disposing the elements CONSTITUTION:Several basic disposition patterns (templates) 4 are prepared, a nearest template 4 to positional relation of elements in a circuit is selected from them, and the elements are disposed The template 4 includes a positive power source side resistance plate 1, a transistor plate 2, and a negative power source side resistance plate 3 Accordingly, resistors 5, 6, 12-15, 18, 19, 25-28, transistors 7-10, 20-24, capacitors are gathered according to the same type elements, and can be rationally disposed Thus, a dead space due to separately diffused layers is reduced, an automatic design of a mask layout by a computer is facilitated, and a chip area can be minimized

Human Learning of Schemas from Explanations in Practical Electronics

Abstract: : Training materials in practical electronics appear to follow a building blocks approach in which common simple circuits are presented and then combined into more complex circuits Each circuit is presented in the form of a circuit diagram and an explanation of how the circuit works in terms of a causal chain of events Such materials suggest that teaming electronics consists of learning schemas for the building block circuits; complex circuits can then be understood as combinations of these simpler schematic circuits The process of teaming appears to be based on extracting schemas from the explanations This report presents human experimental results based on earlier artificial intelligence work in this project Engineering students learned building block circuits and then learned complex circuits; the time required to understand the explanations and answer questions about the circuit behavior were compared to an Al system that learned from explanations and a model of question-answering Generally, learning the schematic building block circuits facilitated performance, and the Al system and question-answering model could predict the amount of facilitation However, the benefit of learning circuit schemas under these conditions was surprisingly mild

HERESY: a hybrid approach to automatic schematic generation (for VLSI)

Abstract: An automatic schematic generation system called HERESY is presented, which represents a well-engineered combination of algorithmic and rule-based approaches. Equipped with a set of carefully-chosen evaluation criteria, HERESY is able to generate high-quality, reasonably general classes of schematic diagrams in an efficient way. A novel levelization algorithm that can detect and resolve arbitrary cyclic structures of a circuit is described. An example schematic generated by HERESY, together with its computational efficiency is also presented. >

Engineering work station circuit diagam editor

Abstract: PURPOSE:To generate a large-scale circuit diagram without paying attention to the size of a page by providing a function to divide the generated circuit diagram into pages. CONSTITUTION:On the supposition that a sheet has an infinite size, a circuit diagram 17 is generated without paying attention to divisions of pages. The circuit diagram 17 consists of symbols and wirings, and an outside frame 18 is so generated that it surrounds the whole of the generated circuit diagram. The generated circuit diagram using logic symbols are divided into pages having a designated size, and the same symbol name is added to divided parts of one signal line, and symbols to discriminate between signal input and output are added to cut end points of the signal line. Thus, the large-scale circuit diagram is generated without paying attention to the size of pages.