Showing papers on "Clock gating published in 1975"

Clock recovery from random binary signals

Abstract: A circuit for detecting timing errors between a binary signal and a local clock pulse generator is described. Three binary samples are compared and logical control signals for the clock are derived.

Clock phasing circuit

Abstract: A clock phasing circuit for aligning data which is transmitted by a first clock, running at a particular frequency, with a second clock running at the same frequency as the first clock but in a different and undetermined phase relationship. The incoming data includes a synchronizing signal which initiates the operation of the clock phasing circuitry so that the data is alternately clocked into each of a pair of flip flops by successive pulses from the first clock. Each flip flop is individually connected to one of the inputs of one logic gate of a pair of gates which are alternately enabled by successive pulses from the second clock. The outputs from the two logic gates are combined by a further logic gate so that the data is reformed in alignment with the second clock.

Flip-flop controlled clock gating system

Abstract: A flip-flop controlled clock gating system comprises a single-shot clock circuit including triggerable means effective to allow the passage of only one clock pulse from the clock input terminal to the output terminal; a clock inhibit circuit including a flip-flop network settable in a first condition enabling the passage of clock pulses from the input to the output terminal and STOP actuator means effective to actuate the flip-flop network to a second condition inhibiting the passage of such clock pulses; and a clock enable circuit including RUN actuator means effective when actuated to trigger the single-shot clock circuit to restore the flip-flop network to its first condition enabling the passage of clock pulses from the input terminal to its output terminal.

Gating signal control for a phase-controlled rectifier circuit

Abstract: A method and apparatus for controlling the phase retard time of a phase-controlled rectifier circuit in a power conversion system wherein a clock-pulse synchronized alternating voltage source is connected to supply power to the phase-controlled rectifier circuit. The clock pulses controlling the voltage source are detected and delayed for a predetermined time interval prior to their application to the voltage source. A ramp voltage generator synchronized to the clock pulses and a comparator circuit for comparing the ramp voltage signal level to a reference level provide a means for generating gate pulses to control the phase retard time of the phase-controlled rectifier circuit between maximum and minimum retard times. Maximum retard time is established at the occurrence of a clock pulse by applying a gating signal to the rectifier circuit if the rectifier circuit has not been triggered prior to detection of the clock pulse. Further gating signals are inhibited until the alternating voltage source has reversed polarity in response to the delayed clock pulses thus establishing a minimum retard time. The predetermined time interval between detection of the clock pulses and application of the delayed clock pulses to the alternating voltage source is selected to be at least sufficient to allow commutation and achievement of forward voltage blocking ability, by the components of the phase-controlled rectifier circuit.

Transmission system for pulse signals of fixed clock frequency

Abstract: A transmission system for pulse signals of fixed clock frequency having repeaters located in the transmission path, each of which is provided with an adjustable equalizing amplifier, a pulse regenerator and a clock extraction circuit. In addition to the pulse signals a pilot signal synchronized with the clock frequency is transmitted which is synchronously mixed with a local pilot signal derived from the clock extraction circuit. From the mixing product an adjusting signal for automatic equalization is derived which is reliable under all conditions. The resulting simplicity of structure and implementation of the equalizing amplifier renders the transmission system particularly suited for pulse signals at a very high clock frequency.

Transmission system for pulse signals of fixed clock frequency using a frequency selective circuit in a clock frequency recovery circuit to avoid phase jitter

Abstract: A transmission system for pulse signals of fixed clock frequency with regenerative repeaters located in the transmission path, each being provided with a pulse regenerator and a clock extraction circuit recovering the clock frequency for the control of the pulse regenerator from the received pulse signals with the aid of a frequency selective circuit. The use of a special type of frequency selective circuit results, especially in transmission systems having a large number of regenerative repeaters, in a considerable reduction of the phase jitter of the recovered clock signal in the receiver without detrimentally influencing the acquisition of the clock frequency in the individual regenerative repeaters.

Method and apparatus for the mutual synchronization of the exchange clock pulse oscillators in switching systems of a PCM time division multiplex telecommunication network

Abstract: A method and apparatus for synchronizing clock oscillators in each of the exchange installations (network nodes) of a PCM/TDM telecommunication network is described. A frequency divider in each network node receives pulses from a clock generator at that node, and frequency dividers are provided for receiving clock pulses from other exchangers on incoming trunks. The incoming trunk frequency dividers are caused to operate with a phase displacement of 180° relative to the clock generator in the exchange. The outputs from the incoming trunk frequency dividers and the exchange clock frequency divider are coupled to phase discriminators. The phase discriminator outputs are coupled through a sum or mean value producing element to produce a control signal for adjusting the frequency of the exchange clock oscillator. Reference phase regeneration is initiated as a result of frequency drift from the oscillator no-load frequency, which drift exceeds a predetermined value.

Leaf-type digital clock

Abstract: A leaf-type clock driven by a intermittent and segmental rotation by using so called Geneva-gear mechanism to cause turning-over of the time- and minute-indicating leaves is disclosed. This leaf-type clock has the advantages that number of the leaves may be reduced, and that the time accuracy is improved, and further that small-sized clock can be designed.

Low power clock driver

Abstract: A low power dissipation circuit for generating clock pulses comprises a plurality of solid state devices which are normally off and draw only leakage current in their quiescent state. The clock pulse is started by a signal to a set side driver and is stopped by a signal to a reset side driver. The input drivers remain on only during the time they are being driven. The output drivers for generating the clock pulse comprises a pair of switching transistors which remain on only while the clock switching pulses are being generated.

Static inverter control circuit

Abstract: Method and apparatus for effecting control of a complementary impulse commutated inverter to enable start-stop operation without power removal and to avoid start-up failures caused by inductive load flux saturation. The invention utilizes a gating logic circuit to always start inverter operation by gating a first predetermined switching element. The gating logic circuit responds to a stop command by terminating operation in a half-cycle in which the first predetermined switching element is not carrying load circuit. In one embodiment upon receipt of a stop command the gating logic circuit terminates inverter operation by applying a last gating signal to the first predetermined switching element, the last gating signal having a time duration less than that required after receipt of a gating signal for current reversal in the inductive load. The last gating pulse is effective to commutate the conducting switching element and current reversal in the load is effective to commutate the first predetermined switching element.

Clock signal regeneration system operating on ternary pulses

Abstract: Apparatus for regenerating periodic clock signals in a ternary pulse transmission system. It comprises an input transformer with a secondary winding having a grounded midpoint, a high "Q" band-pass filter tuned to the repetition frequency of the clock signals, and a shaping circuit for these clock signals. The apparatus further comprises a threshold level comparator differentially supplied by the input transformer and supplying through an addition circuit an adjustable delay line whose output is connected through the filter to the said shaping circuit. The latter circuit may comprise a limiting amplifier combined with a pair of flip-flop circuits.

Electronic digital clocks

Abstract: An electronic digital clock includes an arbitrary number of fixed value stores the BCD stored values of which are compared with the BCD time representative signals generated by the clock to produce, in the event of coincidence, an electrical output signal which serves for switching purposes. In order to reduce the number of connections to be made to an integrated clock chip the clock may include a changeover switch which enables connections to the clock display device also to be used as connections to the stores.