Showing papers on "Clock generator published in 1980"

Electronic kilowatt-hour meter for measuring electrical energy consumption

Abstract: In a kilowatt-hour meter for measuring electrical energy consumption from an alternating electrical supply, a microprocessor includes a clock signal generator which is synchronized in phase with the incoming supply frequency. Pulse sampling means controlled by the clock generator sample the incoming voltage and current waveforms at a preselected time instant or instants in each cycle and the sampled data is utilized in the microprocessor to determine energy consumption.

Clock recovery apparatus for phase shift keyed encoded data

Abstract: A pseudo clock generator produces pulses synchronous with, and having a period equal to one-half of the clock signal within a phase shift keyed encoded data stream. A phase lock circuit, having a stable period equal to that of the data clock signal tends to lock to the pseudo clock signal. Logic detects the condition of the phase lock signal being in phase lock with said data clock signal and in response thereto, masking circuitry prevents the pseudo clock generator from responding to input data transitions which occur outside of a predetermined masking window.

Time counting clock generator

Abstract: A counting clock generator for a video tape recorder, in which two different phase counter clock signals at a pulse repetition frequency corresponding to the running speed of a tape are processed to obtain a direction detection signal indicating the direction of running of the tape and a clock signal at a frequency of predetermined times that of the two different phase counter clock signals, and the clock signal thus obtained is counted by a reversible counter, which is controlled for switching between up-counting and down-counting by the direction detecting signal with data "0" preset when the tape is running forward and data "maximum value" preset when the tape is running backward, for producing two revised counter clock signals of different phases according to the count output signal from the reversible counter.

Delay stage for a clock generator

Abstract: A delay stage (30,50) receives input signals at input terminal (16) and power from power terminals (12, 14). A detector circuit (30) is connected between power terminals (12, 14) and to the input terminal (16) for receiving the input signal and for generating a detection signal upon detecting a predetermined level of the input signal. A buffer circuit (50) is connected between the power terminals (12, 14) and to the detector circuit (30) for receiving the detection signal while not capacitively loading the detector circuit (30).

Skip count clock generator

Abstract: A skip count clock generator yielding multiple frequencies of clock pulses for variably driving a scanner to produce a required resolution of scanned data includes a base frequency generator of clock pulses and a device for establishing a periodic clock pulse cycle. An electrical logic circuit is used to skip any chosen whole number of clock pulses in a period to yield a desired fraction of the clock pulse cycle.

Method and circuit arrangement for clock synchronization in the transmission of digital information signals

Abstract: A method and a circuit arrangement for clock synchronization in the transmission of digital information signals. In the four-wire type transmission of blocks of information signals on a two-wire transmission line it is determined, by phase comparison, whether the first bit in each block of signals (1) falls within a time interval derived from the bit clock signal of the local clock generator; (2) falls within an adjacent time interval or (3) falls within none of such time intervals. Depending upon the results of this comparison, the time relationships are left unchanged, the period of the clock generator is shortened or lengthened one or more times, or a one-time, initial phase equality is established.

Phased array sonar

Abstract: PURPOSE:To markedly simplify a transmission beam former, by separately performing the delay of an envelope and the setting of the local phase of each element assuming the band limitedness of a probe without performing the delay of each channel of a delay map in a high frequency signal stage. CONSTITUTION:The data of the pulse width, delay quantity or the like of the output signal of each channel are successively inputted as control words. An oscillator 2 oscillates a high frequency signal having a frequency f1 sixteen times of the fundamental frequency f0 at the same time when a power supply is turned ON and a frequency divider 3 divides the frequency of said signal to output the fundamental frequency. When a transmission trigger is inputted, an MV1 generates an envelope pulse having a pulse width prescribed by control word input at every transmission trigger. A SIPU SSR 6 outputs the control words to a VLSR 5 as parallel words with respect to the serial input of said control words to give the data delaying the output pulse of the MV on the basis of the output clock phiE of a clock generator 4 to the VLSR 5 and the output signal E thereof becomes a signal coupled with the signal input having the fundamental frequency by an AND circuit 7 to be outputted. A VLSR 8 delays a signal B in the same way as the VLSR 5 to output a signal B'.

Kilowatt-hour meters

Abstract: in a kilowatt-hour meter for measuring electrical energy consumption from an alternating electrical supply, a microprocessor (20) includes a clock signal generator (22) which is synchronised in phase with the incoming supply frequency. Pulse sampling means (21) controlled by the clock generator (22) sample the incoming voltage and current waveforms at a preselected time instant or instants in each cycle and the sampled data is utilised in the microprocessor to determine energy consumption.

MOS Device including a substrate bias generating circuit

Abstract: An MOS device including a substrate bias generating circuit, comprising: a clock generator for receiving an external clock signal and generating first and second internal clock signals; an internal circuit operated by the first and second internal clock signals; a pumping circuit driver for generating third and fourth internal clock signals in synchronization with the first and second internal clock signals and; a pumping circuit operated by the third and fourth internal clock signals. In this device, when the substrate potential (VBB) is relatively high, currents flow from the substrate to the pumping circuit.

Synchronization circuit for video clock oscillators

Abstract: A synchronization circuit for video clock generators, wherein in order to obtain a line synchronization simultaneous with a complete image synchronization, there is provided a follow-up control which delivers a clock frequency signal. The follow-up control has its reference input connected with the output of a line pulse-separation circuit, delivering an external horizontal pulse signal, and is further connected with the input of an external complete image characteristic or marker pulse-separation circuit. Both of the separation circuits have infed at their input side a mixed pulse signal. The external complete image-characteristic pulse-separation circuit is connected at its output side with the first input of a comparator, the second input of which has infed thereto the output signal of an internal complete image characteristic pulse-separation circuit. The output signal of the comparator is infed to the first input of a regulation pulse-switch means, whose output is connected with the clock input of a clock generator, delivering to a respective output an internal mixed pulse signal and an internal horizontal pulse signal. The latter is delivered to the comparator input of the follow-up control and the first input of the internal complete image-characteristic pulse-separation circuit, the second input of which receives the internal mixed pulse signal. The output of the follow-up control is connected with the second input of the regulation pulse switch means.

Non-moving ultrasound therapy instrument - has several transducers switched electronically in cyclic sequence by preset clock generator

Abstract: An ultra-sound therapy head normally has to be moved over the body of a patient by the therapist. This is not required with this instrument which has several heads. These are placed on the patient and ultrasound energy is switched to each in cyclic sequence. The output of a h.f. generator (10) is switched electronically to the five transducers (18-22) on the patient (23). Switching is cyclic-sequential and is controlled by a pre-set clock generator (12). The bell-shaped transducer is held to the body by suction.

IGFET Clock generator circuit employing MOS boatstrap capacitive drive

Abstract: A random access read/write MOS memory device or the like employs a clock driver circuit which includes a push-pull type output stage with two transistors having a clock Φ and its complement Φ as gate inputs. An output node is pulled to a full supply voltage level by a pump transistor connecting the output node to the supply and having a delayed clock coupled to its gate. Another transistor with the supply voltage on its gate connects the output node to the gate of the pump transistor.

Mos device with substrate-bias generating circuit.

Abstract: A MOS device with a substrate-bias generating circuit comprising: a clock generator (41) for generating internal clocks ((Alpha)0, (Alpha)1) after receiving an external clock (EXC); an internal circuit (42) operated by the internal clocks; a pumping-circuit driver (43) for generating clocks ((Alpha)A, (Alpha)B) synchronized with the internal clocks; and a pumping circuit (44) operated by the clocks ((Alpha)A, (Alpha)B). In the device, a current from the substrate to the pumping circuit is caused to flow when the substrate-potential (VBB) is relatively high.

Colour television receiver comprising at least an integrated digital circuit for processing the composite colour signal

Abstract: 1. Television receiver comprising at least one digital integrated circuit for processing the composite color signal, - with a square-wave clock generator used as a chrominance-subcarrier oscillator and generating at least four clock signals (F1, F2, F3, F4) the first of which (F1) has four times the chrominance-subcarrier frequency, and the second to fourth of which (F2, F3, F4) have the chrominance-subcarrier frequency, the first and second clock signals (F1, F2) having a mark/space ratio of 1 : 1, - with a stage providing the digital chrominance signal (C), - with a first parallel multiplier (M1) one input signal of which is the digital chrominance signal (C), and the other input signal of which is a digital chroma control signal (SE), - with at least one buffer memory to which the digital chrominance signal (C) and the third clock signal (F3) are fed, and - with binary computing stages, such as parallel adders and parallel subtracters, characterized by the following subcircuits and features serving to effect digital amplitude control of the received chrominance-subcarrier wave, digital PAL identification and color killer action as well as digital chroma control : - the chrominance-subcarrier oscillator generates a fifth clock signal (F5) having twice the chrominance-subcarrier frequency and a mark/space ratio of 1:3 ; - the third and fourth clock signals (F3, F4) have a mark/space ratio of 1:7 and are 180 degrees out of phase with respect to each other ; - leading edges of the first, second, and fifth clock signals (F1, F2, F5), coincide, while the leading edges of the fourth clock signal (F4) lead those leading edges by the period (T) of the first clock signal (F1) ; - the output of the first parallel multiplier (M1) is connected to the inputs of a first buffer memory (PS1) and a second buffer memory (PS2) whose enable inputs are fed with the third clock signal (F3), and the fourth clock signal (F4), respectively ; - the minuend input of a first parallel subtracter (ST1) is connected to the output of the first buffer memory (PS1), and the subtrachend input of the first parallel subtracter (ST1) is connected to the output of the second buffer memory (PS2) ; - the output of the first parallel subtracter (ST1) is connected to the minuend input of a first parallel comparator (K1) and to the inputs of a third buffer memory (PS3) and a fourth buffer memory (PS4), whose enable input is fed with the fifth clock signal (F5) ; - the subtrahend input of the first parallel comparator (K1) is connected to the output of the third buffer memory (PS3), and the minuend-greater-thansubtrahend output of the first parallel comparator (K1) is connected to the enable input of the third buffer memory (PS3), whose clear input is fed with the inverted burst gating signal (~B) ; - the first input of a parallel adder (AD) is connected to the output of the third buffer memory (PS3) and the second input of the parallel adder (AD) is connected to the output of the fourth buffer memory (PS4) ; - the minuend inputs of a second parallel comparator (K2) and a third parallel comparator (K3) are connected to the output of the parallel adder (AD), while the subtrahend input of the second parallel comparator (K2) is connected to the output of a first programmable read-only memory (FS1), and the subtrahend input of the third parallel comparator (K3) is connected to the output of a second programmable read-only memory (FS2), the first and second programmable read-only memories (FS1, FS2) holding an upper reference value and a lower reference value, respectively, which determine the amplitude control ; - the minuend-greater-than-subtrahend output of the second parallel comparator (K2) is connected to the count-up enable input of a first up-down counter (Z1), and the minuend-smaller-than-subtrahend output of the third parallel comparator (K3) is connected to the count-down enable input of the first up-down counter (Z1), whose count input is fed with horizontalfrequency pulses (H), while the "up" zero-crossing output and the "down" zero-crossing output of the first up-down counter (Z1) are connected, respectively, to the up input and the down input of a second up-down counter (Z2) ; - the outputs of the second up-down counter (Z2) are connected to the first inputs of a second parallel multiplier (M2) and an electronic multiple switch (US) having its second input connected to the output of the second parallel multiplier (M2), while its control input is fed with the burst gating signal (B) ; - the digital chroma control signal (SE) is applied to the input of a fifth buffer memory (PS5), whose enable input is fed with the burst gating signal (B) ; - the second input of the second parallel multiplier (M2) is connected to the output of the fifth buffer memory (PS5) ; - the output of the multiple switch (US) is connected to the second input of the first multiplier (M1), whose enable input is fed with the first clock signal (F1) ; - the minuend-equal-to-subtrahend output and the minuend-smaller-than-subtrahend output of the first parallel subtracter (ST1) are connected to the inputs of an OR gate (OD), whose output is connected via an inverter (IV) to the first input of a first AND gate (U1) and directly to the first input of a second AND gate (U2), the second inputs of which AND gates (U1, U2) are fed with the fourth clock signal (F4) ; - the outputs of the first AND gate (U1) and the second AND gate (U2) are connected, respectively, to the up input and the down input of a third up-down counter (Z3), whose "up" and "down" zero-crossing outputs are connected, respectively, to the R input and the S input of a first RS flip-flop (FF1) ; - a few, preferably three, most significant bits of the output signal of the second up-down counter (Z2) are applied to the inputs of a NAND gate (NG), and - a few, preferably five, most significant bits of the output signal of the first parallel multiplier (M1) are applied to the inputs of a multiple-input AND gate (VU), whose other inputs are connected to the output of the NAND gate (NG) and to the Q output of the first RS flip-flop (FF1), and whose output provides the controlled digital chrominance signal (CG).

Circuit arrangement for clock generation in telecommunications exchanges, in particular time division multiplex digital exchanges

Abstract: having Direction for generating two with one another at most limited phase differences clocks (T ', T ") by doubly provided, in each case by a master clock (M', M"), servo-synchronized clock generator (CCG ', CCG ") generate this first respectively a higher-frequency intermediate clock (H' , H "), which is then turned down to the desired clock frequency, wherein a phase comparison of the two clocks (T ', T") is made, at (in the order of one intermediate clock period coming phase difference between the two clocks T', T ") is "shortened by an intermediate clock period or longer. This is done with the aid of the intermediate clock generators (Z-PD-VCO) downstream digital Taktuntersetzungs- and phase synchronization circuit (UVR ', UVR one clock period of a clock (T)"). is connected such Taktuntersetzungs- and phase synchronization circuit (UVR ") has a Zwischentakt- frequency halving stage which is connected downstream via a Phasenumtaster a further frequency divider and to which a phase comparing circuit for phase comparison between guided clock (T") and leading clock (T ') ,

Gear automatic inspection unit

Abstract: PURPOSE:To make unnecessary, the visual inspection through automatic discrimination of defective or non-defective small sized gears, by comparing the data in photo electric conversion of the dark and light binary shade image scanning the tooth with light, with the reference data. CONSTITUTION:The tooth of the tested gear is illuminated with the light source 3 and the image is formed on the line sensor 15 via the mirror 16 and the lens 17. The line sensor 15 has a constitution of several tens to several hundreds of photo electric conversion elements on one row and controls the output with the clock generator 18. This output is converted into binary signal indicating dark and light with the comparator 19 of suitable threshold value, and the data counting the output of the comparator 19 is delivered to the picture data memory circuit 6 with the counter 20. This data output is converted into the shape parameter and discrimination is made by comparing this with the reference parameter inputted from the data input circuit 7 at the discrimination circuit 11.

Control system for channel selection

Abstract: A channel-selection control system for a frequency synthesizer type receiver which comprises: a frequency synthesizer (1); a plurality of switches (SW 1 , SW 2 ) corresponding to channels having different broadcasting programs, respectively; a plurality of memories (ROM 1 , ROM 2 ) associated with the respective switches (SW 1 , SW 2 ) and each storing data signals (n) corresponding to broadcasting waves for one broadcasting program; a clock generator (CK) for producing clock pulses; a counter (CNT) adapted to count up by the clock pulses for producing address signals (m) for the memories; a comparator (COMP) for comparing a level value of a received signal outputted from said frequency synthesizer (1) with a preset reference level value; and a gate circuit (G 4 ) responsive to said comparator for preventing the clock pulses from being inputted to said counter (CNT) when the level value of the received signal is higher than the reference level value and for allowing the clock pulses to be inputted to the counter (CNT) when the level value of the received signal is lower than the reference level value; the data signal corresponding to the address signal produced from said counter (CNT), being read out from the memory (ROM 1 , ROM 2 ) associated with the switch (SW 1 , SW 2 ) selected; said read out data signal being supplied as a program signal to a programmable divider (PD) included in a PLL circuit of the frequency synthesizer (1).

Peproducing device for halftone picture

Abstract: PURPOSE:To improve the correlation between tone and average luminance, by taking the threshold level of a middle cell of a dither matrix to a low level and sequentially increasing the threshold level of surrounding cells. CONSTITUTION:The X address of a picture memory 103 is advanced one by one with every one clock of a clock generator 1 and the column address of a matrix memory 105 is advanced one by one. On the other hand, a main scanning sychronizing signal HS of a laser beam electrophotography recorder 106 advance the Y address of the memory 103 one by one and advances the row address of the memory 105 with the row counter 108 one by one. Thus, the video information of the memory 103 is compared with the threshold of the memory 105, and a recording signal is outputted to a device 106 sequentially. In this case, the threshold levels of the middle cell of the memory 105 is taken as the lowest level to make recording with improved correlativity between the tone and the average luminance.

Generator for phaseesynchronizing signal

Abstract: PURPOSE:To reduce the cost of the entire system by making input device systems from detection ITV cameras in one by stably shifting (delaying) synchronizing signals to the cameras by a fixed value. CONSTITUTION:The output of clock generator 3 is inputted to synchronizing signal generator 7 and horizontal synchronizing signal 16 of reference synchronizing signal 22 is inputted to counter 8 while vertical synchronizing signal 17 is supplied as a reset signal to counter 8. The output of counter 8 is inputted to coincidence circuit 9 with synchronous phase-shift set values 11 and 12. Output 19 of coincidence circuit 9 is inputted to one-shot generator 10 for start signal generation, where start signal 20 for the generation of synchronizing signals with a constant phase shift from reference synchronizing signal 22 is generated and supplied to synchronizing signal generator 7 of each camera.

Time division multiplex system having transmitted pulses in time channels distributed over and co-transmitted with a frame clock signal component

Abstract: In a time division multiplex system having chronological grouping of optically transmittable PPM signals, the PPM signals of one half of the time channels are transmitted as pulses in one half of each pulse frame and the PPM signals of the other half of the time channels are transmitted as pulse pauses in the other half of each frame for the purpose of the co-transmission of a clock frequency component without providing a separate synchro time slot. For this purpose, PPM pulses are formed and transmitted only in one pulse frame half, while PPM pulses formed in the other pulse frame half are subtracted from a continuous signal corresponding in amplitude to the pulse amplitude, and the signal difference is transmitted. At the receiver, the frame clock component is filtered out by a band-pass filters and is exploited for controlling a receiving clock generator.

Channel selection control system for frequency synthesizer receiver

Abstract: PURPOSE:To realize a channel selection system which can detect easily and rapidly a broadcast wave exceeding a preset reference level among broadcast waves on a broadcast system which broadcasts the same broadcast contents by several broadcast waves. CONSTITUTION:PLL synthesizer part 1, switches SW1 and SW2 selecting several channels with the same broadcast contents, and automatic detection switch SW3 are provided. Further, ROM1 and ROM2 stored with data signals corresponding to broadcast waves of the same broadcast contents, clock generator CK supplying clock pulses to counter CNT, and comparator COMP making an amplitude comparison between received signals from reference signal generating circuit VR and waveform shaping circuit S are provided. When switches SW1 and SW2 are turned ON and automatic detection switch SW3 is also ON for automatic detection, a signal exceeding a fixed level is selected among radio waves of the same broadcast contents and then applied to counter CNT and an address corresponding to the broadcast wave is supplied from counter CNT to ROM1 and ROM2, so that synthesizer part 1 will make automatic channel selection.

Coding communication system

Abstract: PURPOSE:To save power consumption for signals of measuring distances extreamly, shorten the time for holding signals and multiply the measurement of distances, commands and telemetry by carrying out synchronously measurement of distances by means of PN and communication by means of PCM CONSTITUTION:Clock f (127k bps) of PN code for measurement of distances is applied from clock generator 1 to PN code generator 2 and a PN code with length N is generated A clock for command of f/N is entered into code generator 7 Divider 6 sends a start synchronizing signal of f/K to the diemodulating part and synchronizes with the start of transmission of the command code The PN code array is processed in exclusive ''OR'' 3 in correspondence with the command code, modulated in modulator 4 and transmitted by transmitter 5 The up-link signal is received and relayed by the transponder equipped in a artificial satellite and is transmitted again Therefore, the PN code becomes 1/100 of the usual one and the process is completely finished within about 1 sec In addition, S/N of the circuit is not decreased by the signal for measurement of distances

Continuous-wave radar responder having two-position switches

Abstract: The invention relates to C-W radar responders, having a carrier of some gigahertz whose amplitude is modulated between some dozens and some hundreds of kilohertz. Such a responder comprises means for sampling the signal it receives in such a manner that the sampling theorem is satisfied with respect to the amplitude-modulation frequency. The responder comprises at least an aerial, a radio-frequency amplifier, a delay line, a clock generator, an input, an output and two switches connected to the input and to the output, respectively, of the amplifier. The operating sequence of the switches, controlled by the clock generator, is such that each sample of the received signal passes through the amplifier more than once before it is re-transmitted.

Measurement of quantity of fish in drag net - uses sweep generator and absorption resonance analyser for net sensors

Abstract: The device for measuring the catch in a dragnet uses several level sensors connected to an evaluation circuit and arranged at intervals along the dragnet. Reliable level monitoring is ensured by simplification of installation and maintenance of the sensors compared to conventional arrangements. Each level sensor has an absorption resonance circuit tuned to the characteristic frequency of the sensor which varies when the net is fitted to its height. All the sensors are supplied from a common cable connected to a sweep generator whose frequency variation encompasses the frequencies of all sensors. The evaluation circuit contains a device which counts the number of the frequency dependent signal level disruptions per sweep period. The sweep frequency and output signal transfers are controlled by a common clock generator.

Signal processing device

Abstract: A signal processing apparatus comprises a main unit having a frame, and a plurality of modules for processing analog signals replaceably inserted into said frame Each of the modules has an analog-to-digital converter for the analog signals and an identification signal generator which generates a module identification signal different for each module The main unit comprises a signal processing system and a conversion pulse clock generator The latter one clocks each analog-to-digital converter in each module to convert analog signals to digital data The digital data are transmitted together with the module identification signal to the signal processing system

Pulse modulation system

Abstract: PURPOSE:To improve a modulation efficiency by giving information to the width as well as the interval of pulses CONSTITUTION:The output of a 2/(2, 2) converter in pulse interval and width modulator 62 becomes the preset signal of counters 81 and 82, and these counters count timing signals (e) and (f), which are distributed alternately, by the number of preset and generate end signals (g) and (h) at the count completion These end signals are supplied to RS-FF84, and i-number on and j-number off are generated correspondingly to codes (i) and (j) to generate pulse interval and width modulation signal (k), and code read controller 83 instructs converter 2/(2, 2) to transmit the code and controls the read of counters 81 and 82 on a basis of the change point of signal (k) Meanwhile, clock generator 85 generates prescribed-period clocks, and these clocks are gated in gate circuits 86 and 88 by signal (k) and the inverted signal obtained by causing signal (k) to pass through inverter 87 and are supplied to counter 81 and 82 alternately Consequently, information is given to the width as well as the interval of pulses, and the modulation efficiency can be improved

Clock signal distribution system

Abstract: PURPOSE:To eliminate undesired variation in pulse width by shortening a period while avoiding an influence of the rounding of a waveform, etc, in transmission, by providing a frequency multiplier circuit and chopper circuit which shorten pulse width to fixed width near a load circuit CONSTITUTION:On printed substrate 1, several integrated-circuit elements LSI4 are packaged and in the center, clock signal distributor 5 is provided which distributes clocks from clock generator 7 to respective circuit elements 4 Near latch circuit 11 which forms a load on circuit elements 4 receiving clock signals from distributor 5, chopper circuit 10 is provided which compresses pulse width to fixed width, and this circuit 10 is composed of a circuit of NOR gate circuits 12-14 or inverters combined and two-input NOR circuit 15 serving as a frequency multiplier circuit; and the duty ratio of a clock signal generated by generator 7 is fixed to approximate 50%, and consequently the rounding of a waveform and variation in pulse width caused by components in substrate 1 and wiring are prevented

Automatic decision system for color signal

Abstract: PURPOSE:To make it possible to record and reproduce accurately a desired signal by making an automatic discrimination between signals on NTSC and PAL systems. CONSTITUTION:Part of a video signal is applied to sub-carrier generator made of a burst clock generator, etc., whose output is inputted to BPF12 as a 1st detection circuit and detection circuit 13. Then, the output of generator 11 is supplied to BPF14 as a 2nd detection circuit and detection circuit 15 and outputs of those circuits 13 and 15 are inputted to change-over circuit 16 supplied with the video signal; and a NTSC signal is outputted from 1st output terminal 17 of circuit 16 and a PAL signal is outputted to 2nd output terminal 18. From the video signal applied to generator 11, a continuous wave of 3.58MHz as a NTSC sub-carrier or of 4.43MHz as a PAL sub-carrier is obtained; BPF 12 provides a passing band of 3.58MHz, and BPF14 provides that of 4.43NHz. Consequently, NTSC and PAL outputs are obtained by both detection circuits 13 and 14 and outputted from circuit 16.

All TTL Compatible Clock CCD Memory with CCD Generator

Abstract: The method of on-chip CCD clock generation is discussed and successfully demonstrated by a 64 kbit CCD memory. Since the memory chip contains its own CCD clock generator, all inputs are fully TTL compatible. The memory is organized 65 536 X 1 in 256 random access loops of 256 bits each. The memory array employs an 8-phase electrode/bit (E/B approach to achieve high packing density and to increase charge-carrying capacity. The chip size is 7.1 mm X 4.7 mm and 13 percent of the chip area is occupied by the CCD clock generator. The typical power dissipation is 205 mW in the active mode at 1 MHz and 40 mW in the standby mode at 50 kHz. Only 25 percent of the total power is devoted to the CCD clock generation at 1 MHz. The device is processed witlh an n-channel double level polysilicon-gate technology.

Circuitry for determining the mean period length of a periodical signal

Abstract: To determine the mean period duration pulse sums are formed by means of a shared or in time with the periodic signal stopped counting device, wherein the pulses from a frequency-stable clock generator originate. In order to obtain values ​​for the average period at the shortest possible time intervals with high accuracy, in the circuit arrangement an intended for receiving the pulse sum data register (4) having at least two memory locations (5) is provided, which via a synchronous with the periodic signal command clock of is externally controllable. In addition, the circuit means a downstream data register adder (6), which engages with its intended for the formation of the total memory locations of the data register in such a way in electrical connection, that at the output (7) of the circuit arrangement in each case the sum of a predetermined number of successively stored is pulse sums available.