Showing papers on "Clock generator published in 1996"

Digital downconverter/despreader for direct sequence spread spectrum CDMA communications system

Abstract: A system for digitally downconverting and despreading a multi-channel analog direct sequence spread spectrum signal is provided. The system includes a free-running, non-steering, clock generator which outputs an A/D sample clock, and an A/D sample clock having a rate which is an integral multiple of a chip rate of the spread spectrum signal. An A/D converter which receives the spread spectrum signal and the A/D sample clock and outputs a digitized multi-channel signal from the multi-channel spread spectrum signal, and a local pseudo-noise sequence signal source which outputs M local pseudo-noises, wherein M is an integer greater that 1 is also included. A multi-channel complex downconverter/polyphase filter which receives the digitized multi-channel signal and the A/D sample clock and a sample timing phase control signals, simultaneously filters and downconverts the digitized multi-channel signal to baseband, corrects timing phase misalignment between the digitized multi-channel signal and the locally generated pseudo-noise sequences, and outputs a multi-channel complex corrected baseband signal is provided.

A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation

Abstract: This paper describes a low-power microprocessor clock generator based upon a phase-locked loop (PLL). This PLL is fully integrated onto a 2.2-million transistors microprocessor in a 0.35-/spl mu/m triple-metal CMOS process without the need for external components. It operates from a supply voltage down to 1 V at a VCO frequency of 320 MHz. The PLL power consumption is lower than 1.2 mW at 1.35 V for the same frequency. The maximum measured cycle-to-cycle jitter is /spl plusmn/150 ps with a square wave superposed to the supply voltage with a peak-to-peak amplitude of 200 mV and rise/fall time of about 30 ps. The input frequency is 3.68 MHz and the PLL internal frequency ranges from 176 MHz up to 574 MHz, which correspond to a multiplication factor of about 100.

Spread spectrum clock generator

Abstract: A clock circuit includes an oscillator for generating a reference frequency signal, and a spread spectrum clock generator cooperating with the oscillator, generating a spread spectrum clock output signal having a fundamental frequency and reduced amplitude EMI spectral components at harmonics of the fundamental frequency. The spread spectrum clock generator preferably includes a clock pulse generator for generating a series of clock pulses, and a spread spectrum modulator for frequency modulating the clock pulse generator to broaden and flatten amplitudes of EMI spectral components which would otherwise be produced by the clock pulse generator. The spread spectrum modulator frequency modulated the clock pulses with specific profiles of frequency deviation versus the period of the profile. The clock generator circuits are digital and may be reset to a starting condition to synchronize the spread spectrum clock. For a laser printhead, the clock is synchronized with the start-of-sweep signal, so that printing is not degraded.

Block clock and initialization circuit for a complex high density PLD

Abstract: A block clock and initialization circuit for a programmable logic block in a complex very high density programmable logic device generates a plurality of block clock signals and block initialization signals for elements in the programmable logic block. The block clock and initialization circuit includes a block clock generator circuit and a block initialization circuit. The block clock generator circuit receives a first set of product terms in a plurality of product terms and a plurality of clock signals as input signals. In response to the input signals, the block clock generator circuit generates output signals on a plurality of block clock lines. The block initialization circuit receives a second set of product terms in the plurality of product terms as input signals. In response to the input signals, the block initialization circuit generates a plurality of output signals on the block initialization lines.

Integrated circuit temperature monitoring and protection system

Abstract: A system of monitoring and protecting integrated circuits against damage due to over temperature conditions functions to monitor the temperature of an IC and either shut down its input clock signal or assert its reset line if case temperatures rise to high. Heat dissipated by an integrated circuit is sensed by a temperature sensor. The temperature sensor is thermally coupled to the integrated circuit via thermal glue or other thermally conductive means. The output of temperature sensor is input to temperature sensor circuitry which converts the low level output of the temperature sensor into a signal that can be read by a processor. The processor is suitable programmed to monitor the output of temperature sensor circuitry. When the temperature of the integrated circuit rises past a predetermined threshold value, the processor outputs a control signal to the clock generator circuitry causing it to switch off its clock signal input by the integrated circuit or asserts the chips reset line. Either action should prevent any further temperature rise of the chip. Other embodiments include monitoring multitude integrated circuits and placing the sensing components within the chip itself. In addition, an embodiment is disclosed that utilizes the JTAG interface standard included in many integrated circuits to transmit temperature information to the processor. In addition, the present invention can be used to generate heat maps of circuit boards, useful during prototyping and in the management of real systems.

A monolithic digital clock-generator for on-chip clocking of custom DSP's

Abstract: This paper shows a robust and easily implemented clock generator for custom designs. It is a fully digital design suitable for both high-speed clocking and low-voltage applications. This clocking method is digital, and it avoids analog methods like phase locked loops or delay line loops. Instead, the clock generator is based on a ring counter which stops a ring oscillator after the correct number of cycles. Both a 385 MHz clock and a 15 MHz custom DSP application using the on-chip clocking strategy are described. The prototypes have been fabricated in a 0.8 /spl mu/m standard CMOS process. The major advantages with this clocking method are robustness, small size, low-power consumption, and that it can operate at a very low supply voltage.

Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook

Abstract: A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

Pulse modulator circuit for an illuminator system

Abstract: An illuminator system is provided that is responsive to a trigger signal from a remote source to supply controlled pulses to a load, such as an array of light emitting diodes in a LED strobe. The LED strobe is positioned in close proximity to a lens mounting system. The system of the present invention includes a remote trigger source, a load such as an array of light emitting diodes, and a pulse gate section. The pulse gate section includes a trigger interface having an input connected to the trigger source and is configured to generate a pulse trigger signal in response to a trigger signal from the trigger source. A clock generator responds to the pulse trigger signal by generating at least one clock signal, and a flash pulse generator responds to the clock signal and to at least one user definable input signal by generating a flash pulse signal. The flash pulse signal is used to activate or deactivate the load, and a load drive section is used to drive the load.

Delay clock generator for generating a plurality of delay clocks delaying the basic clock

Abstract: The present invention provides a delay clock generator where a plurality of stable delay clocks can be generated and digitizing is easy. The delay clock generator comprises first to nth (n: integer not less than 2) delay circuits (11 to 1n) connected in cascade connection for delaying the basic clock (KO) in sequence, a phase comparator (21) for comparing phase of a delay clock from the nth delay circuit (1n) with that of the basic clock, and a delay control circuit (31) for generating a delay control value to make the phase of the delay clock from the nth delay circuit synchronize with that of the basic clock based on a phase comparison result, and for controlling delay amounts of the first to nth delay circuits respectively by the delay control value. In the present invention, a voltage control type oscillator is not used, and since delay amounts of the first to nth delay circuits are controlled by the delay control value generated based on the phase comparison result, the delay clock generator can be constituted wholly by digital circuits and moreover can generate stable delay clocks.

Image-forming device

Abstract: PROBLEM TO BE SOLVED: To provide an image-forming device capable of preventing the interference between the correction period of main scanning magnification variation and a screen period effectively. SOLUTION: The image-forming device forms a latent image by performing exposure scanning on the surface of a photoreceptor in a main scanning direction by the modulation of light beams. The image-forming device comprises a subpixel clock generator 32 for generating a subpixel clock having a fixed period, a pixel clock generator 33 for generating the pixel clock for prescribing pixel width in the main scanning direction, and a clock period corrector 36 for correcting the period of the pixel clock generated by the pixel clock generator 33. The pixel clock generator 33 uses a plurality of subpixel clocks generated by the subpixel clock generator 32 to generate pixel clocks. The clock period corrector 36 increases and decreases the number of subpixel clocks applied to the generation of the pixel clock by a prescribed number to the preset reference number of subpixel clocks for correcting the period of the pixel clock, and can change the prescribed number of subpixel clocks arbitrarily. COPYRIGHT: (C)2007,JPO&INPIT

Differential delay line clock generator with feedback phase control

Abstract: An on-chip clock waveform generator for generating from an externally supplied clock (EFI) an on-chip (internal) clock with a 50% duty cycle having a clock rate of 1/2, 1, or 2 times that of EFI, is based on a tapped delay line with a tap-to-tap differential delay of approximately 1% of the external clock (EFI) period. The waveform generator detects the tap at which a full period of delay occurs between delay line input and the tap. By knowing the tap for a first full period delay the generator determines the taps at which the 1/4, 1/2, and 3/4 period waveform states can be observed. The pulses corresponding to fractional periods, are used to generate standard pulse width streams that correspond to 1/4 period intervals. A programmed multiplexer/selector selects the proper sequence from these pulse streams to drive an RS flip-flop in order to produce the output 50% duty-cycle clock running at 1/2, 1, or 2 times the external (EFI) clock. Generally, the system can produce output clocks with 50% duty cycle and with rates greater than, equal to, or less than the external clock (EFI). Other optional operating modes generate 25% duty cycle waveforms at 1/2 the rate of EFI. A feedback signal is generated by comparing the phase of the generated on-chip clock with the phase of EFI which is used to adjust the overall delay of the generator in order to improve synchronism between EFI and the on-chip clock.

Processor chip having on-chip circuitry for generating a programmable external clock signal and for controlling data patterns

Abstract: Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.

Image sensing apparatus and method for discharging dark current charge stored therein

Abstract: A solid state image sensor including a light-receiving section, a storage section, and a clock generator. The clock generator performs a first discharging operation for discharging noise charges in the light-receiving section, a first transferring operation for transferring the noise charges in a reverse direction from the storage to the light-receiving section, and a second discharging operation for discharging the noise charges transferred from the storage into the light-receiving section.

Video signal processing device for writing and reading a video signal with respect to a memory according to different clocks, while preventing a write/read address pass-by in the memory

Abstract: An input video signal is written into alternate field memories M1 and M2, according to a timing clock from an input video clock generator. A display video signal is alternately read from those field memories, according to a timing clock from a display video clock generator. In switching a read memory, an address observation circuit judges whether or not a read/write address passes by a write/read address, referring to the condition of reading and writing operations. In this event, the circuit makes a judgement, based on the lag between a vertical synchronizing signals of an input video signal and of a display video signal, and a change of the lag with time. If it is judged that one address will pass by the other, the same read/write memory is again accessed for reading/writing. With this arrangement, there is provided a circuit having a relatively simple structure for preventing a match of read and write addresses.

Computer system with low power mode invoked by halt instruction

Abstract: A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) stops the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.

Closed loop clock recovery for synchronous residual time stamp

Abstract: An SRTS clock recovery apparatus and method are provided. The apparatus broadly includes a controllable destination node clock generator (37) such as a digitally controllable oscillator, a block (36, 38, 40) for generating a local RTS-related value from the destination node clock (37) and the system reference clock (10), and a comparator (50) which compares the incoming RTS-related value to the local RTS-related value to provide a feedback error or control signal which is used to adjust the controllable clock generator (37). If desired, a filter (52) which filters the error signal can be provided in the loop. With the feedback loop as provided, when the destination node clock (37) is faster than the source clock, the error signal will cause the destination node clock (37) to slow, and vice versa.

Semiconductor integrated circuit

Abstract: PURPOSE: To reduce the power consumption of a semiconductor integrated circuit even in its fast operation state. CONSTITUTION: The clock signals of fast frequency f1 and slow frequency f2 are inputted to a function block 3 from an internal clock generator 2, and one of these two internal clock signals can be selected by the selectors 4 and 5. The clock signal of frequency fl or f2 of the block 3 is supplied to the input terminal of a frequency/voltage converter 6 which controls the power voltage in response to the high or low frequency of the internal clock signals. Then a reference clock pad 15 of an LSI 1 is connected to a reference terminal, and the gate electrode of an N type MOSFET 7 is electrically connected to the output terminal of the converter 6. In other words, the voltage of a power supply Vcc' of an internal logic circuit 8 of the block 3 can be controlled by the MOSFET 7 whose gate voltage is controlled by the output of the converter 6.

Method and circuit arrangement for operating a discharge lamp

Abstract: The invention relates to a method and a circuit arrangement for operating aischarge lamp. In the preheating phase, the actual value of the load current is registered, a first time-invariant setpoint value of the load current, which corresponds to a desired actual value of a load current in the preheating phase, is formed, and a clock generator is activated, which runs freely at a frequency which is less than the resonant frequency of the load circuit when the lamp is off and is greater than the resonant frequency of the load circuit when the lamp is on. The preheating phase is terminated after a first predeterminable time period has elapsed. In the striking phase, the actual value of the load current in the load circuit is registered, a time-varying setpoint value of the load current is formed, and the clock generator is synchronized with the frequency of an inverter. The striking phase is terminated as soon as the setpoint value of the load current reaches a value at which an on-time of a half-bridge switching element is greater than the period of the free-running clock generator. In normal operation, the actual value of the load current is registered and a second time-invariant setpoint value of the load current is formed, which setpoint value corresponds to a desired actual value of the load current in normal operation.

Software configurable digital clock generator

Abstract: The clock generator generates an output clock signal of known frequency from an internally generated high frequency signal of unknown frequency and from a low frequency input signal of known frequency. To this end, the clock multiplier first determines the frequency of the internal clock signal from a comparison with the input clock signal. In one arrangement, the frequency of the internal signal is determined by counting a number of clock transitions occurring during the internal signal within one period of the input clock signal. Once the frequency of the internal signal has been determined, the clock multiplier generates an output clock signal based upon the internal clock signal but adjusted in accordance with the newly determined frequency of the internal clock signal. In one arrangement, the clock multiplier employs a programmable divider. A software control unit calculates a divide factor for use by the programmable divider based upon the period of the input signal, the count of transitions, and the desired period for the output signal. The internal signal is then routed through the programmable divider to divide the signal by an amount sufficient to produce an output signal having a period approximately equal to the desired output period. In one specific arrangement, the internal signal is generated by a ring oscillator which produces an internal signal having a frequency of, for example, 300 megahertz (MHz) to 500 MHz. The programmable divider divides the internal signal by a divide factor between 6 and 10 to yield an output frequency of about 50 MHz. The clock multiplier also includes a mechanism for determining whether the actual frequency of the output signal remains within an acceptable range of frequencies and for reprogramming the programmable divider, if necessary, to reset the output frequency to within the acceptable range of frequencies. Method and apparatus embodiments of the invention are described.

Monolithic integrated sensor circuit

Abstract: The CMOS integrated circuit consists of a sensor system (100) to produce the sensor signal (u1), a power supply (400), an amplification stage (200) for the sensor signal. An inverter circuit (310, 320, 220, 340) reverses the sensor signal polarity at equal intervals (b1, b2) by means of a clock generator (500). The amplified sensor signal is fed into an averaging circuit (240) which is coupled to the inverter. The sensor signal path is principally symmetrical to reduce offset errors. The circuit may contain a differential sensor system for two Hall effect sensors (110, 130) connected with opposite polarities.

Source synchronization data transfers without resynchronization penalty

Abstract: A system clock generator for a computer system to efficiently transfer data from a source subsystem to a destination subsystem of the computer system. The system clock generator generates a globally synchronized clock signal for the source subsystem and the destination subsystem. The source subsystem includes a clock generator for generating a source clk (SRC -- CLK) signal and a source-synchronous clock (SRC -- SYN -- CLK) signal for the source subsystem and destination subsystem, respectively. The SRC -- SYN -- CLK signal is generated whenever data is transferred from the source subsystem to the destination subsystem. Upon receiving the data and SRC -- SYN -- CLK signal from the source subsystem, the data is synchronized at the destination subsystem using the SRC -- SYN -- CLK signal. Since the source and destination subsystems are synchronized by the system clock signal, an incoming data stream can be synchronized within one system clock cycle. In one embodiment, data from two streams can be multiplexed and combined into a single data signal at the source subsystem, thereby increasing the bandwidth of the computer system to twice the frequency of the system clock generator.

Method and apparatus for automatic frequency and voltage selection for microprocessors

Abstract: A method and apparatus for providing automatic frequency and voltage selection for microprocessors in a computer system. Microprocessor identification (ID) bits are burned into a microprocessor during manufacture to specify the correct bus frequency and core voltage. A clock generator and voltage regulator are provided to receive and interpret the ID bits and provide the correct frequency and voltage.

Complementary clock generator and method for generating complementary clocks

Abstract: A complementary clock generator and a method for generating complementary clocks are disclosed. A complementary clock generator according to the present invention includes a first inverter, a first transmitting switch and a second transmitting switch. The first inverter outputs inverted clock signals by inverting input clock signals. The first transmitting switch has an input terminal, an output terminal, a first control input terminal and a second control input terminal, and connects the input terminal to the output terminal when the input clock signal reaches the first control input terminal and the inverted clock signal from the first inverter reaches the second control input terminal. The second transmitting switch has an input terminal, an output terminal, a first control input terminal and a second control input terminal, and connects the input terminal to the output terminal when the inverted clock signal from the first inverter reaches the first control input terminal and the input clock signal reaches the second control input terminal, wherein same-phase clock signals are obtained from the output terminal of the first transmitting switch, and opposite-phase clock signals are obtained from the output terminal of the second transmitting switch.

Method and apparatus for dynamically adapting the clock rate and data transfer rate of phone-line powered modems.

Abstract: Methods and apparatus are disclosed for detecting the amount of the power available from a phone line and for adjusting the clock rate and data transfer rate of a modem or a device that transfers data over the phone line to provide the best possible performance for the available phone-line power. A method of operating a device for transferring data over a phone line includes the following steps: setting the device off hook; measuring the voltage level of the phone line; determining the amount of the power available from the phone line; selecting a clock rate for the device; setting the device to operate at the clock rate; placing a call; selecting a data transfer rate; and transferring the data. An apparatus for transferring data over a phone line includes a clock generator for generating a first clock signal of a first frequency; a frequency divider for generating multiple clock signals of different frequencies and for outputting one of the multiple clock signals; a data pump for modulating and demodulating data; a sensor for sensing the voltage level of the phone line; a microcontroller for controlling the frequency divider, the data pump and the sensor; a line isolator for blocking hazardous electrical signals from coming into the apparatus; an interface for coupling the microcontroller to a computer host; and a power converter for converting a DC voltage of the phone line to an appropriate DC power supply voltage to be used by the apparatus.

Low electromagnetic interference clock oscillator module

Abstract: A low noise clock oscillator in standard surface mount plastic or ceramic form. With the same soldering pads design such devices can be replace with a convention standard surface mount clock oscillator to reduce Electro-magnetic Interference or RFI (Radio Frequency Interference) without redesign of the main board. The oscillator is characterized by using a spectrum spread clock generator and a spread controller on an elevated platform to reduce common mode emission currents.

Method and apparatus for telemetering data bidirectionally between two devices, one device incorporating a coarse phase adjustment and the other device incorporating a fine phase adjustment

Abstract: An improved system is disclosed for telemetering data bidirectionally between two devices such as an implantable device and an external programmer. The two devices both include clock generators that operate at the same nominal frequency, but only one of the devices (i.e., the programmer) includes a phase-locked loop receiver that adjusts the frequency and phase of its clock signal to match that of the received data. The clock generator of the other device (i.e., the implantable device) generates a fixed-phase clock signal, which is selectively inverted or not inverted, to adjust its phase by 180°. This selective 180° adjustment enables the programmer's phase-locked loop receiver to have a reduced, ±90° pull-in range, which simplifies its construction and reduces the time required to achieve synchronization.

Clock generator for generating complementary clock signals with minimal time differences

Abstract: An improved complementary-type clock generator minimizes the time difference between a normal clock signal and an inverted clock signal. The clock generator includes an inverting unit for outputting Vcc-Vtn and Vss+Vtp level voltage by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal, and a first buffer for outputting Vcc-Vtn and Vss+Vtp level voltages by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal. A level converting unit receives the Vcc-Vtn and Vss+Vtp level voltages and second and third buffers inverters the outputs of the level converting unit for outputting a normal clock signal and an inverted clock signal.

Pad cells for a 2/N mode clocking scheme

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Clock distribution network utilizing local deskewing clock generator circuitry

Abstract: A clock signal distribution network for a high-speed microprocessor includes a clock synthesizer (30) coupled to receive an externally generated clock signal. The clock synthesizer (30) deskews the external clock to generate an internal clock signal, which is then distributed about the semiconductor die by a conductivity tree. A set of local deskewing clock generators (40 a-d) are coupled to branch interconnects (31, 33 a-b, 34 a-d) of the tree and function as a zero-delay buffers for driving proximally located circuitry.