Showing papers on "Column (database) published in 1983"

Random/serial access mode selection circuit for a video memory system

Abstract: In a video computer system, an improved memory circuit is provided which is effective for delivering stored data only at appropriate instances, and which is also simpler and more reliable in design. In particular, the system preferably includes a bit-mapped RAM circuit which assumes a serial mode in response to both a row address signal and a suitable data output control signal, and which assumes a parallel or "random" mode when only the row address is received. Stored data is transferred to a parallel output terminal in the RAM circuit, or to a serial output terminal therein, depending upon the sequence of these signals as well as the column address and read signals, whereby the data output control signal is used for two separate and different purposes within the system.

Two axis fast access memory

Abstract: The disclosure relates generally to a computer generated synthesized imaging system. More particularly, the invention relates to a method and apparatus for providing fast access to a two axis memory wherein consecutive data elements in both row and column orientation of a data set represented as a matrix may be obtained at a rate faster than the access time of memory elements utilized. A speed-up of access speed by a factor N may be achieved, where N is a power of 2 (2, 4, 8, 16 . . . ). The memory elements are organized in N independently addressable banks of data memories. The matrix oriented data is mapped into these N banks such that any N contiguous data elements of any row or any column reside in different memory banks. Any N contiguous data elements of any row or column may then be accessed within the access time of any one memory bank. The N contiguous data elements may then be read from memory in a single memory cycle. These N data elements can then be multiplexed in the proper sequence into a data stream operating N times faster than the basic access speed of the memory elements used.

Memory with redundancy

Abstract: A byte-wide memory with column redundancy. The redundant columns can each be substituted for any column in the half-array, without regard to which bit position the defective column relates to. Fuses store the address information of the defective columns, and when a match between the externally received column address and the stored defective-column-address is found, the sense amplifier for the bit position which contains that defective column is disabled, and the output of the redundant column (selected by whichever word line is activated) is multiplexed into the I-O buss. Thus, before the row address signal has even been decoded, the defective column has been disabled and one of the redundant columns has effectively been substituted. This configuration means that it is not necessary to have one redundant column for every bit position, but each redundant column can substitute for a defective column in any bit position, and more than one defective column in a single bit position can each be replaced.

Spatial light modulator drive system

Abstract: The spatial light modulator drive system of the present invention permits useful light modulation, such as employed in a projection display device, with a minimum of required data input. A plurality of charge storage cells with associated charge dependent light modulator cells are disposed at the intersection of row and column conductors. The drive system alternately refreshes the data stored in a particular row and responds to external commands. The automatic refresh involves selecting a particular row via a dedicated refresh counter, reading the column data in that row, storing this data in a column latch and rewriting this data to the same row. The generation of a new display is achieved in a number of steps. A particular row is selected by externally applied data. The data type, such as number of bits and variations in shade, is also specified. The starting column for application of new display data enables this new data to be entered into the desired portion of the column latch for application to the desired light modulator cells.

Remark on “Algorithm 603: COLROW and ARCECO: FORTRAN Packages for Solving Certain Almost Block Diagonal Linear Systems by Modified Alternate Row and Column Elimination”

Abstract: In the numerical solution of boundary-value problems for ordinary differential equations, hnear systems with a partmular block structure are encountered. In this paper two packages of FORTRAN subroutines, COLROW and ARCECO, which use alternate row and column elimination for solving such systems, as discussed by Varah, are described Varah's procedure is stable, and introduces no fillin, tha t is, reqmres no additional storage To improve its efficiency, use is made of the fact tha t after each sequence of eliminations a reducible matrix is obtained. In addition, the packages presented treat systems with a more general structure than those considered by Varah. The results of numerical experiments, which demonstrate the effectiveness of the new packages and their superiority over a prevmusly pubhshed code, on a suitably restrmted class of problems, are presented

Implementation of data abstraction in the relational database system INGRES

Abstract: This paper discusses the design and implementation of an abstract data type (ADT) facility which was added to the INGRES database manager. Our implementation of ADTs allows a user to register ADTs and ADT operators with the run-time database manager, declare column values of relations to be instances of ADTs, and formulate queries containing references to ADTs and ADT operators. The user view, implementation, performance, and possible extensions to this new facility are described.

Multi-dimensional-access memory system with combined data rotation and multiplexing

Abstract: A data memory arrangement includes n columns of storage elements each column being addressable only one element at a time and having at least n2 storage elements so as to provide a succession of square arrays. Each square array comprises square sub-sections. On storage of a complementary array of data the data is multiplexed from each square array to the next within each sub-section and after each cycle of such multiplexing the sub-sections are rotated one step cyclically. Such rearrangement of data gives freedom and speed of simultaneous access to data words occurring in original rows and/or columns without excessive penalty in the complexity of the addressing system.

Repairable ROM array

Abstract: The individual rows of a ROM array are accessed by a row decoder/driver in response to the arrival of the address of the individual row on the address lines. A plurality of programmable switches store the address of a row of ROM array found to contain one or more defects. If the incoming address is that of the defective row each of a plurality of comparators connected to both an address line and the associated switch outputs a coincidence signal to an AND gate. The output of the AND gate accesses a spare row of RAM which thus replaces the defective row of the ROM array. Access to the spare row is automatic upon receipt of the address of the defective row. Each column of the ROM array contains a check bit computed from the remaining contents of the respective column, and the data to be stored in the spare row is generated from the remaining contents of the ROM array. At initialization, the generated data which should have been stored in the defective row is written into the spare row.

Modular display for cigarette packs

Abstract: A modular retail counter display apparatus for merchandise, such as cigarettes, which is displayed and sold in small packages. Two identical trays may be connected to a column, either with a separate means supporting the column or with one or both trays supporting the column. A sign holder slides onto the top of the column and a ratchet engagement between the sign holder and the column permits a sign to be mounted at any desired height on the column. The trays may be connected to the column in vertically spaced relationship, or the trays may be secured together in end abutting relationship and connect to the column in a horizontal arrangement. Alternatively, the trays and column may be supported by means of a clamp assembly either upon a horizontal rail or upon a vertical pole.

Architecture for two dimensional fast fourier transform

Abstract: A novel architecture and circuitry for implementing a new fast fourier transform algorithm which does not require a very large core memory and also does not require a transpose of a matrix. A pipelined and parallel architecture implements the two dimensional fast fourier transform on an array of input data values, with the transformation being performed by a plurality of serially arranged pass stages. Each pass stage includes an input shuffle arrangement for receiving an ordered set of input data from a row or column of a two dimensional matrix of such input data values, and for performing a shuffle operation thereon to produce a shuffled order of the input data. Each pass stage further includes a plurality of identical switching circuits coupled in parallel to receive the shuffled order of input data. Each switching circuit includes an arithmetic logic unit which receives four input data values and performs four data transformations thereon to produce four output data values, with each of the four data transformations including a first operation of selective addition or subtraction of the four input data values, followed by a second operation of selective multiplication by an exponential multiplier.

Removable synthesis column

Abstract: A column for use in DNA synthesis. The column is transparent and is disposable to allow access to the resin beads within the column. The column includes end caps which are engageable with a housing and a screw to secure the column in the housing.

Redundant columns for byte wide memories

Abstract: Apparatus is provided for substituting a spare column of memory cells in a byte wide memory for a defective column of cells in such memory. The apparatus includes a spare column of memory cells, an electrically conductive line 13, a spare decoder 16 for switchably connecting the line 13 to the spare column, a first fuse FSD₁ between the spare column and the line 13, a series of second fuses FS controlling a series of switches T₁, T₂ . . . between the line 13 and corresponding sense amplifiers 11, and a series of third fuses FD, each connected between a corresponding column and the sense amplifier associated with that column. The spare column of memory cells is connected to the appropriate sense amplifier by blowing the appropriate fuse FS and supplying the necessary address information to spare decod­ er 16. The defective column of memory cells may be disconnected by blowing the appropriate fuse FD.

Column Rules of ACI, SSLC, and LRFD Compared

Abstract: Steel industry specifications (AISC and LRFD) as well as the concrete industry Building Code (ACI) are described for composite column design. Results from the 3 design documents highlight some of the differences in design philosophies.

Interconnection and addressing scheme for LCDs

Abstract: Liquid crystal elements are interconnected in an array of rows and columns, which are not independent of one another, and are addressed by pulsed signals which together reduce the number of leads N required to operate the display The interconnection scheme includes connecting together the last column to the second row, the penultimate column to the third row, etc, and the first column to the last row In one embodiment for randomly accessing the display, the addressing scheme divides a row-select signal and a column-select signal into two time-wise sequential subsets: a first subset which includes pulses of one polarity in the time slots corresponding to the elements in that row, and a second subset which includes pulses of either polarity depending on which elements in that column are to be turned on and which off The coincidence of two pulses of opposite polarity applied to an element from the row-select and column-select signals in sufficent to turn on that element Different addressing schemes are utilized in other embodiments for use as pseudo-analog pointer displays and bargraph displays

A 64K DRAM with 35 ns static column operation

Abstract: A 64K dynamic RAM with a function mode similar to static memory operation is described. The device has multiplexed address inputs and a one-address strobe clock (RAS). After a row address is applied to the device, column selection is performed as in static memory, resulting in fast cycle time and simplicity of use. Column address access time and cycle times of 35 ns are achieved. The device has some other functions to reduce critical timings. Address transition detector circuits are used for column selection. An improved column decoder is provided to allow column address input skew. The device uses NMOS single transistor memory cells and is packaged in a standard 300-mil 16-pin DIP.

Up- and down-dating procedures for linear L 1 regression

Abstract: In this paper algorithms are given for up- and down-dating the solution of the linearL 1 regression problem ∥b−Ax ∥1→min when a column or a row ofA is inserted or deleted or the right hand sideb is changed. The algorithms are up-or down-dating the condensed simplex tableau given by the algorithm of I. Barrodale and F. D. K. Roberts. The results of empirical tests are included.

Processing system of parts data of machine design

Abstract: PURPOSE:To prevent erroneous inputs and to hold the consistency of data between systems by generating a parts table in accordance with drawings generated in a designing system by the aid of a computer and giving parts information from the parts table to drawings. CONSTITUTION:A data base 3 of computer-aided design (CAD) has internal data 10; and when this data is outputted by a plotter or the like, it has a form of drawing as shown by an output image 11. In this output image, NOTE indicates character data of parts information, title column information, etc. A parts information data base 7 has internal data 12; and when this data is outputted from a parts generating system to a printer or the like, it has a form shown by an output image 13. As its contents, item numbers, quantities, specifications, goods names, etc. are outputted by the printer.

High density programmable memory array

Abstract: An array of electrically alterable floating gate devices arranged in rows and columns with each column of devices sharing a column conductor. Each row of devices is connected between two row conductors with adjacent rows sharing a common row conductor whereby in an array having N rows of devices there is a total of (N+1) row conductors. Input and output decoders connected to the row conductors enable the unique read-out of any selected element.

Gas feed means for use in centrifugal casting devices

Abstract: An improved gas feed means adapted to accommodate and secure the lower end of a polymerization column for synchronous rotation therewith and adapted to supply a controlled amount of a gaseous medium, such as nitrogen, into and through the rotating polymerization column so as to purge any undesirable gas within the polymerization column that could adversely affect the quality of the objects being centrifugally casted.

High-speed digital computer system

Abstract: Data (including instructions) is fed to a memory from a processor on MEMIN bus 320 and from the memory to the processor on MEMOUT bus 318 The memory comprises up to 8 boards connected in parallel, the Figure showing one board Each board comprises four memory modules 512, 514, 516, 518 which can be accessed in overlapping manner since the memory cycle of a module is 400 ns against 100 ns for the buses 318, 320 Each module comprises two memory banks 520, 522 each with 21 16 K memories each arranged as a 128 x 128 bit array The 16 K memories are addressed in parallel by row and column address latches 526, 528 whereby each bank stores 16 K 21 bit words For memory access the row and column addresses RA, CA are supplied to the latches 526,528 from MEMIN bus 320 and a buffer 534 while six bits BMS supplied to memory logic 538 These bits select the board which is to perform a memory operation, the module within the board and the bank within the module Readout is from the selected module via a multiplexer 540 and one of four registers 542, 544, 546, 548 catering for overlapping accesses For a write operation, the word to be written is transferred from MEMIN bus 320 to a data latch 365 before the addresses RA, CA and select bits BMS are supplied as described above

Copy-milling machine with at least two movable columns.

Abstract: One column is equipped with a tracing device for tracing the pattern and the other column is equipped with a suitable milling tool for carrying out the machining of the workpiece.

Methods of and apparatus for digital audio signal processing

Abstract: not available for EP0098082Abstract of corresponding document: US4549298A method of detecting and correcting errors in digital audio signals comprises assembling digital data words each of which corresponds to a digital audio signal representing an analog audio sample into units of six data words, assembling with each unit six redundant words derived by exclusive-OR operations on the data word in each row and each column of the unit, assembling the data words and redundant words into sub-blocks and adding cyclic redundancy check code words to the sub-block, recording and reproducing each sub-block, after reproduction using the code words of each sub-block to set the logic state of error flags that have been added to each word in the sub-block, re-forming the units and assembling with each reproduced unit horizontal and vertical syndromes derived by exclusive-OR operations on the data words and redundant words in each row in each column of the unit, comparing the horizontal and vertical syndromes and resetting the logic state of the error flags in dependence on this comparison, deriving further horizontal syndromes by exclusive-OR operations on the data words and redundant words in each row of the reproduced unit and where there is only a single word in a row flagged as being in error, correcting that error word using the further horizontal syndrome, and deriving further vertical syndromes by exclusive-Or operations on the data words and the redundant word in each column of the reproduced unit and where there is only a single word in that column in error, correcting that error word using the further vertical syndrome.

Limit switch columns

Abstract: The invention is used to replace limit switches which are generally arranged in a linear fashion, and is fitted to a rotating part of the drive. Two or more columns of limit switch cams having different rotation speeds are driven via different step-down transmissions. The cams in each case operate associated limit switches. The step-down ratios of the individual columns are in this case selected such that the slowest column carries out less than one full revolution for the complete movement travel. The step-down to the next slower column is selected such that the switching accuracy is sufficient for the slowest column in order to define a specific revolution of the next slower column. The same applies to all the intermediate columns. The step-down to the fastest column is designed such that its switching accuracy is sufficient for the application. Break and make functions, as in the case of simple switches, are possible by connecting together in each case one switch from the individual columns.

A present trend in rectification: energy saving

Abstract: Rectification columns are the greatest consumers of energy in many chemical plants. Decreasing their energy consumption has been a long-term aim of process engineering. These considerations have culminated, e.g., in the splitting of a separation between two columns operating at different pressures to make an energy match feasible, the application of heat pumps, the addition of intermediate evaporators and condensers, and also the joint execution of different separations in one column with several feeds and side streams. Formerly, these ideas were often thwarted by high investment costs and (supposedly) reduced flexibility. However, in recent years, the design of complex plants with extensive energy matching has become commonplace. A prerequisite is the feasibility of calculating exactly the necessary separation units; moreover, there is also a need for efficient column sections and heat exchangers which can operate with small pressure drops and modest temperature differences. A general energy-saving strategy also leads to process modifications in other separation techniques such as liquid-liquid extraction.

Matrix keyboard with plurality of sequences of cascaded electrical elements

Abstract: An improved multikey matrix keyboard for inputting data into a computer, wherein pressing a key places in circuit the point of intersection of a plurality of row conductors and a plurality of column conductors respectively connected to portions of separate sets of row and column sequential series of measurable electrical elements whose cumulative values correspond to the specific row and column of the pressed key. By employing a plurality of row and column key output circuits, the number of keys present in the matrix keyboard is exponentially increased.

Access controlling system

Abstract: PURPOSE:To exclude a process related to the control of transmission of data, by feeding the data given from a processor to an input/output device based on the priority order of a control table when access is requested from the processor. CONSTITUTION:When access requests are given from application programs P1-Pn, a processing part 5 executes an access controlling program 3 and writes the access requests in tables T1-T3 for each input and output. While the program 3 analyzes both a chain column CH and switch column SW to decide the data to be transmitted. For instance, the levels of matrix columns are set higher in order of Q0-Q2. In this case, the order of transmission of data B, A and C is informed to the part 5. Then the part 5 starts a control program 4, and data A-C in a memory 6 are fed to input/output devices I1-I3 in order of B, A and C. In such way, a program can be produced regardless of the input/output state when the application program is produced.