Showing papers on "Comparator applications published in 1993"

Overcurrent protection circuit of power device and semiconductor integrated circuit device

Abstract: In an overcurrent protection circuit of a power device, an analog switch (4) connects a negative input of a comparator (3) to a reference voltage VREF1 or another reference voltage VREF2 depending on a control signal (S5) from a timer (5). A positive input of the comparator (3) receives voltage drop value (VS). The timer (5) is triggered by a leading edge of an input signal (IN) to output the control signal (S5) to the analog switch (4). The control signal (S5) directs the analog switch (4) to connect the reference voltage VREF2 to the negative input of the comparator (3) only during a transient state estimated period (T) and to connect the reference voltage VREF1 to the negative input of the comparator (3) out of the transient state estimated period (T).

Novel area-time efficient static CMOS totally self-checking comparator

Abstract: The comparator is an essential element in concurrent error detection (CED). To ensure the correctness of error detection processes, comparators must be totally self-checking (TSC): any single fault occurring in the comparator must be detected by at least one normal input pattern, and before the detection of that fault, no erroneous output must be guaranteed. An area-time efficient static CMOS TSC comparator design is presented. This comparator uses only eight transistors and is totally self-checking with respect to stuck-at, stuck-open, stuck-on, bridging faults, and breaks. >

Differential comparator and analog-to-digital converter comparator bank using the same

Abstract: A fully differential comparator includes a differential signal input, a differential reference input, and a differential signal output. Identical first and second gain stages are used in the differential comparator that each have a first single-ended input, a second single-ended input, and a differential output. The first single-ended inputs from the first and second gain stages form the differential signal input of the differential comparator. The second single-ended inputs from the first and second gain stages form the differential reference input of the differential comparator. The differential outputs of the first and second gain stages are cross-coupled to form the differential signal output of the differential comparator. The differential comparator can be used in conjunction with a conventional resistor string found in the front end of a flash ADC, but in a novel manner that prevents undesirable loading effects, as well as other problems associated with prior art single-ended comparators.

Method and apparatus for reducing jitter and improving testability of an oscillator

Abstract: An oscillator such as a pulled-crystal oscillator (50) provides low clock jitter by converting a sinusoidal voltage on a crystal's (51) terminals into a digital square wave with a comparator (56). The oscillating frequency of the crystal (51) is pulled by selectively switching in extra capacitance through capacitor digital-to-analog converters (CDACs) (57, 58). The oscillator (50) has built-in testability which allows individual capacitors in the CDACs (57, 58) to be quickly tested for opens. A scan path is connected to the inputs of the CDACs (57, 58) for selecting individual capacitors. A first input terminal of the comparator (56) is precharged before a capacitor under test (171) is connected. A comparison voltage is provided to the second input terminal. The capacitor under test (171) is determined to be functional if, after being connected to the first input terminal of the comparator (56), it discharges the first input terminal to a voltage below the comparison voltage, causing the comparator (56) to switch.

Fractional N frequency synthesis with residual error correction and method thereof

Abstract: A frequency synthesizer (107) utilizes a variable oscillator (114) the output of which is used as the frequency synthesizer output (115) and is fed to a digital divider (108). The output of the digital divider (108) feeds one input of a phase comparator (109). The other input of the phase comparator (109) is fed from a reference oscillator (116). A phase comparator (109) output controls the variable oscillator (114). The digital divider (108) has a division ratio that is varied with time by a multi accumulator fractional-N division system (112) such that the effective division ratio may be varied by non-integer steps. Due to the time varying division sequence applied to the digital divider (108) there is a residual spurious level on the output signal (115). A second digital sequence from the multiple accumulator fractional. N-division system (112) is generated to reduce this spurious level and is applied to the output of the phase comparator (109).

Programmable voltage hysteresis on a voltage comparator

Abstract: A programmable voltage comparator having a programmable hysteresis function controlling the comparator's output relative to first and second comparator input voltage variables. The programmable voltage comparator comprises an inverting and non-inverting input for receiving a first and second input voltages and an output providing a logic state signal reflecting the amplitude of the inverting and non-inverting input voltages. The comparator includes level shift circuitry coupled to the inverting and non-inverting inputs for programmably shifting the amplitude of the voltages applied to the inverting and non-inverting inputs responsive to the logic state output of the comparator. In one embodiment, the comparator includes a differential amplifier having inverting and non-inverting outputs, wherein the level shift circuitry comprises a first level shift circuit coupled to the non-inverting voltage input and having a feedback element coupling to the non-inverting output. A second level shift circuit is coupled to the inverting input with a feedback element coupled to the inverting output.

Analog-to-digital converter with capacitor network

Abstract: Link capacitors are used to establish connection between joining-points of coupling capacitors and inverters in an inverter chopper comparator array, in order to reduce injected electric charge variation due to feedthrough. Some of the comparators in the comparator array, arranged at each end thereof, constitute a redundant comparator array without connection to a logic circuit that is used to obtain an A/D conversion output. This reduces the effects of the device parameter variations in the comparator array, whereby a high accuracy voltage comparison is achieved, and noise-resistant strength is improved.

Comparator circuit for triggering a switching process when a variable measurement signal passes through a switching threshold

Abstract: A comparator circuit having a signal input and at least one signal output having an ON-state and an OFF-state, wherein the ON-state represents an input signal lying above a pre-given switching level V s and the OFF-state represents an input signal lying below the switching level V s . The comparator circuit has two comparators, the signal inputs of which are each acted upon by the input signal, wherein both the comparators are wired together in such a way that a switching on of the first comparator produces a signal corresponding to the ON-state of the comparator circuit and the switching off of the second comparator produces a signal corresponding to the OFF-state of the comparator circuit.

Digital phase comparator and phase-locked loop.

Abstract: A digital phase comparator measures the phase difference of two signals (S1, S3) from a third signal (S2), and calculates the difference. The zero crossing of the two signals respectively sets two flip-flops (11, 12). If both flip-flops are set, they are simultaneously reset with a delay. Each set flip-flop enables a corresponding counter (13, 14). An evaluation unit averages the counter outputs at major intervals. The phase comparator can be incorporated into a phase-locked loop.

Electronic tire gauge

Abstract: An electronic tire pressure gauge has a tire valve stem receiver, a thin silicon square diaphragm with four diffused resistors configured in a full Wheatstone bridge as a pressure transducer, a voltage controlled oscillator, a comparator, a clock, a microprocessor with program memory, and a display. The comparator compares the stable transducer output for a given pressure with the voltage-controlled oscillator output, to yield a comparator pulse which goes high while the transducer signal is greater than the oscillator signal. The clock provides bus cycles used by the microprocessor for counting the duration of the high comparator pulse. Multiple high comparator pulses are compared, and the longest duration is selected and converted to a pressure value and displayed. Battery power is conserved by a power on/off algorithm.

Fully-differential relaxation-type voltage controlled oscillator and method therefor

Abstract: A fully-differential relaxation-type voltage controlled oscillator (VCO) (30) includes an operational transconductance amplifier (OTA) (31) for receiving a differential input voltage. The OTA (31) provides a charging current to a capacitor (33) proportional to the differential input voltage during a first phase of an output signal, and provides a discharging current to the capacitor (33) proportional to the differential input voltage during a secon d phase of the output signal. A comparator having hysteresis (34) detects the charge on the capacitor. A latching portion (35) latches the output of the comparator (34) to provide non-overlapping clock signals.

Low current comparator with hysteresis

Abstract: An accurate, low-current integrated circuit comparator includes a differential input stage 10 comprising differential pair transistors 22 and 24, differential pair current mirror transistors 26 and 28, and a constant current source transistor 30. The comparator also includes an hysteresis stage 12 coupled to one of the current mirror transistors; the hysteresis stage comprises an hysteresis mirror transistor 34 and a switching transistor 36. The comparator additionally includes a gain stage 14 comprising a gain transistor 38 and a constant current source transistor 40. Finally, the comparator includes an output stage 15 comprising gain transistor 42 in an open-drain configuration. In the disclosed embodiment, the descending trip threshold is set entirely by the ratios of device geometries, and is therefore very accurate and is independent of temperature, lithography and processing variations. While the ascending trip threshold is related to the ratio of tail current of the differential pair to the transistor gain of the devices in that pair, which quantities are dependent on the device parameters, this relationship is only to the one-half power, and therefore is relatively small.

Offset reduction in a zero-detecting circuit

Abstract: The offset of a zero-crossing detector circuit is virtually eliminated by inverting the inputs of the comparator after a certain delay from a detected zero-crossing while storing the output state assumed pursuant the detection of a zero-crossing for an interval of time longer than said delay but shorter than the minimum interval of time occurring between any two successive zero-crossings of the input signal.

Device, consisting of a transmitter and a receiver, for detecting objects

Abstract: Such a device is the subject matter of the main patent 4237311 C1. In order to check the making and breaking conditions or the signal reserve and the hysteresis of the signal reserve, the output of the comparator (10) is connected to a signal input of a microcontroller (11). The reference voltages are generated via resistors which are connected to an input of the comparator (10) and are activated by corresponding switching outputs of the microcontroller (11). A transmission pulse or a transmission pulse sequence is not output until after interrogation of the comparator (10) for the presence of an interference (unwanted, undesired, parasitic, spurious, noise) signal and in the event that such a signal is not detected. The novel device is intended to render it possible to eliminate periodically occurring interference signals, in particular. After the transmission pulse has been emitted, a second interrogation of the comparator (10) is performed. The time interval up to the emission of the next transmission pulse can be set as a function of the detection of interference signals during interrogation. The result of this is that the transmission pulses are respectively emitted in the transmission pauses of periodically occurring interference signal sequences, as a result of which disturbances of the device are avoided.

Multiple input comparator circuit for a switched resistive network

Abstract: A comparator circuit, for a switched resistive network which may be combined with a transconductance amplifier, simultaneously and independently compares a plurality of input voltages to a reference voltage. The circuit comprises a current splitter having a current input, a plurality of comparator outputs, and a corresponding plurality of voltage inputs that control the fraction of the input current available at each comparator output. A reference output of the current splitter is provided as an input to a current mirror, and each of the comparator outputs of the current splitter is connected to a corresponding output of the current mirror. The current available at each of the current mirror outputs is a function of the reference input provided from the current splitter. The comparator circuit needs only one bias input and one reference input. The inclusion of a second biasing device with an associated mirror device produces a transconductance amplifier combined with the comparator circuit. This combination minimizes the integrated circuit area required for transconductors and comparators on image processing chips.

Low power dual power supply high resolution comparator

Abstract: A low power comparator is provided in which a wide common mode range, high resolution and near continuous operation is achieved. The comparator of the present invention employs a wide common mode range with true one millivolt resolution. Furthermore, the comparator is a low power device rendering it readily adaptable to today's portable low power devices. An innovative three stage comparator is described. The first stage receives the two input signals to be compared. A number of innovations are utilized to minimize the offsets and therefore errors in the comparison measurements. More particularly, a transmission gate is provided at the inputs to balance the differential amplifiers employed in the first stage. The balance of the differential output nodes permits fast settling time of the comparator and minimizes voltage stresses which can create offsets. Furthermore, the design incorporates fully symmetric loads and is interdigital for optimum matching and minimum size. The second stage circuit utilizes a unique cascode circuit which provides very high gain thereby enabling the comparator to function at a higher resolution. Furthermore, a gain loop is created in the second stage such that the output swing is within 0.2 of a volt of the voltage rail, thereby realizing the benefit of stack cascoded devices with the advantage of optimal swing at low voltage operation. The third stage modifies the two signal differential output of the second stage to a single signal output of the circuit.

Intruder detection system for room surveillance - applies several voltage reference levels to comparator from microprocessor via resistors, and prevents emission of pulse upon detection of noise signal.

Abstract: The object detection system has a transmitter providing a pulsed signal received by a corresponding receiver at the opposite end of a light path crossing the surveillance zone. The received signal is fed to a comparator (10), coupled to the signal input of a micro-controller (11) coupled to switch outputs for activating corresponding resistances (R1..R3) which provide the reference voltages for the second input of the comparator. The pulsed signal is transmitted by the transmitter after interrogation of the comparator for detection of a noise signal, with the transmission prevented until the noise signal is absent. ADVANTAGE - Tests switching conditions and hysteresis. Reduces effects of internal or external noise..

Monitor for current circuit of appliance, e.g. separate lamps of motor vehicle - uses differential amplifier as comparator with inputs across fuse and output supplying warning appts. if heat exceeds threshold value

Abstract: A load circuit monitoring arrangement contains a measurement resistance in the leads to at least one load (1). The resistance input is connected to one comparator (4) input via a potential divider (3) and its output is connected to the other comparator input. The comparator drives a warning device. The fuse (2) in the lead to the load can be used as the measurement resistance. For functional monitoring of the load the threshold of the comparator is matched to the load current and the variation in the resistance of the fuse with temp. ADVANTAGE - Contains min. number of components and occupies relatively little space. Measurement resistance does not introduce any additional potential drop in load circuit or generate additional heat loss.

Method of tracking thresholds on a read signal

Abstract: A pulse detection sensing system which provides an output signal only when a maximum voltage peak is detected. The system has a comparator which generates a comparator output signal when an output signal generated by the transducer of the system is equal to or greater than a threshold signal. The comparator is coupled to a peak follower and a sample/hold circuit which increases the voltage of the threshold signal to the level of the head output signal when the output signal attains a zero slope and has equaled or exceeded the set threshold value.

Direct current motor control circuit in positioning systems

Abstract: A control circuit, in particular for a direct current control in positioning systems, comprising a differential circuit (1), a control logic (2) and a full bridge (3) connected between a supply voltage V S and a reference potential GND. The differential circuit (1) has a first hysteresis comparator (HC1) and a second hysteresis comparator (HC2). The two comparator inputs (HC1-, HC1+, HC2-, HC2+) of the two hysteresis comparators (HC1, HC2) are connected each to one of two input terminals (IN1, IN2) of the control circuit and crosswise to a comparator input of the respective other comparator (HC1, HC2). The inverting input of each comparator (HC1, HC2) is connected to the non-inverting input of the respective other comparator.

Protection circuit for devices comprising nonvolatile memories

Abstract: A protection circuit (1) comprising a first and second supply line at a first and second supply voltage respectively; a reference voltage source; a comparator connected to the first supply line and the source; and a switch controlled by the comparator via a control terminal and located between the second supply line and the output of the circuit. To reduce static consumption of the comparator under normal operating conditions, the circuit comprises enabling control elements connected to the two supply lines and to the comparator for disabling the comparator and turning on the switch when the two supply voltages differ by a value below a predetermined threshold, but are greater than a reference value.

Communication apparatus with low power consumption

Abstract: A communication apparatus includes a comparator comparing the voltage at one external bus with that at another external bus, and an oscillator. The comparator has a high speed operation mode and a low speed operation mode, and the oscillator has an oscillating operation mode and a non-oscillating operation mode. A sleep signal is supplied to the communication apparatus, to put the comparator in the low speed operation mode and put the oscillator in the non-oscillating operation mode. When a fall or a rise is detected in an output of the comparator, the oscillator is changed to the oscillating operation mode, and thereafter, the comparator is changed to the high speed operation mode.

Fast CMOS multilevel current comparator

Abstract: A new multistage current comparator based on a recently presented principle is proposed. The principle of switching continuously from stage to stage promises high speed and requires a simple regular structure. Simulations are carried out to verify the expected properties.

Hysteresis comparator circuit.

Abstract: A comparator circuit is provided wherein an input impedance element (Z1) is connected to a non-inverted input terminal (T12) of a comparator (CP), and a feedback impedance element (Z2) is connected between an output terminal (T13) of the comparator (CP) and the non-inverted input terminal (T12). The feedback impedance element (Z2) and input impedance element (Z1) are connected with each other to cooperatively constitute a differentiation circuit when seen from the output terminal side of the comparator (CP). With this arrangement, it becomes possible to eliminate an undesirable extension of the pulse width resulting from a hysteresis and at the same time, to prevent chattering. Further, this hysteresis comparator circuit requires no additional special circuit there by reducing the substrate accommodating space and manufacturing cost.

A simple precision frequency standard comparator

Abstract: The authors describe a frequency standard comparator based on the characteristics of the greatest common factor frequency and the phase coincidence detection technique. By using a stable and high-frequency common oscillator, the comparator not only can compare frequency standards with a very high accuracy, but can also measure frequency precisely in a wide frequency range. Almost all the circuits in the comparator are digital integrated circuits. This comparator can also be used to compare the frequency standard with other frequencies precisely, if the frequency of the common oscillator is changed. >

Data signal decoding device.

Abstract: not available for EP0638213Abstract of corresponding document: WO9322841A circuit for decoding a bi-phase mark signal comprises a circuit (2, 3) for detecting transitions in the signal, a counter (4) for producing an output signal proportional to the period between consecutive transitions in the signal, and a comparator (5) for comparing the value provided by the counter (4) with a reference value that is the mean between short and long periods of the incoming bi-phase signal. The mean value is derived by scaling the output of the counter (4) in a scaler (9) by a value determined in accordance with the output from the comparator (5) and by filtering the output of the scaler (9) in a recursive loop that is returned to an input (6) of the comparator (5). A data extractor circuit (14) coupled to outputs of the transition detector (3) and the comparator (5) serves to decode the bi-phase signal in an arrangement which compensates for variation in the overall repetition rate of the incoming bi-phase signal, for example due to variations in the speed of a video tape.

Article detection device using a transmitter and a receiver

Abstract: 2.1. Such a device is the subject matter of the main patent/Patent Application P 42 37 311.5-52. To check the switching-on and -off conditions and the signal reserve and the hysteresis of the signal reserve, the output of the comparator (10) is connected to a signal input of a microcontroller (11). The comparison voltages are generated via resistors connected to an input of the comparator (10) and activated by corresponding switching outputs of the microcontroller (11). A transmission pulse or a transmission pulse sequence is output only after interrogation of the comparator (10) for presence of an interference signal and with non-detection of such a signal. The novel device is intended to make it possible to eliminate, in particular, periodic interference signals. 2.2. After the transmission pulse has been emitted, the comparator (10) is interrogated for a second time. The time interval before the next transmission pulse is emitted can be adjusted as a function of the detection of interference signals during the interrogations. The result is that the transmission pulses are in each case sent out in the transmission pauses of periodic interference signal sequencies, which prevents interference in the device.

Versatile CMOS comparator with adjustable window and digital input reference

Abstract: A CMOS window comparator which is capable of accepting a digital input reference is presented. The comparator uses two external resistors to adjust the boundaries as a percentage of the reference voltage. The reference input is a digital word which is converted, using an on-chip DAC. The proposed circuit is a useful building block for various applications like process control, automatic testing and the implementation of analogue built-in self-test (BIST) structures, etc.

Motor control, especially within a printing machine

Abstract: A description is given of a computer, especially within a printing machine, having a device for the analog registration of signal values. The computer is intended, for example, to drive a positioning motor with an associated analog current value transmitter via a motor control. It is intended to produce a simple, cost-effective and precisely functioning alternative to an analog-digital convertor. The PWM (pulse-width modulated) output of the computer is connected on the input side to a low-pass filter whose output is connected to an input of the comparator. The signal of the analog current value transmitter is connected to the second input of this comparator. The output of the comparator is connected to the computer.

Apparatus including a multiple channel pulse width modulated signal circuit.

Abstract: Apparatus for generating a plurality of pulse width modulated signals for separately driving a plurality of electrical loads, comprising, a microprocessor, a plurality of comparator means, each of the comparator structure including first and second input terminals and an output terminal, digital to analog converter structure connected to the microprocessor for control thereby, the converter structure including a plurality of output terminals respectively connected to a different comparator structure first terminal for providing separate control signals thereto, structure for generating a reference voltage signal having a variable amplitude, the signal generating structure connected to each of the comparator structure second terminals for providing the reference voltage signal thereto, a plurality of power amplifiers, a plurality of electrical loads respectively connected to a different comparator structure output terminal via a different power amplifier for receiving therefrom an amplified comparator structure output signal, the microprocessor programmed for selectively addressing the converter structure output terminals, the microprocessor programmed for generating said separate control signals, and each of the comparator structure responsive to a different separate control signal and said variable reference voltage signal for modulating the pulse width of a comparator structure output signal to drive the power amplifier and thus the electrical load connected thereto.