Showing papers on "Constraint graph (layout) published in 2000"
20 Sep 2000
TL;DR: In this paper, the authors compare four constructive heuristics based on rectangular dissection and on turn-regularity, also in combination with two improvement heuristic based on longest paths and network flows, and an exact method which is able to compute provable optimal drawings of minimum total edge length.
Abstract: We present an experimental study in which we compare the state-of-the-art methods for compacting orthogonal graph layouts. Given the shape of a planar orthogonal drawing, the task is to place the vertices and the bends on grid points so that the total area or the total edge length is minimised. We compare four constructive heuristics based on rectangular dissection and on turn-regularity, also in combination with two improvement heuristics based on longest paths and network flows, and an exact method which is able to compute provable optimal drawings of minimum total edge length.
We provide a performance evaluation in terms of quality and running time. The test data consists of two test-suites already used in previous experimental research. In order to get hard instances, we randomly generated an additional set of planar graphs.
21 citations
Journal Article•
TL;DR: In this article, an efficient 2\|D compaction algorithm is proposed, which is based on the constraint graph expression of the figures on layout and newly designed rules, in order to do compaction on the chip level, a hierarchical strategy and the fall leaves pool data structure are used,regarding the interconnections as soft lines it also can add to jogs automatically.
Abstract: Due to the unbalance between the development of EDA system and IC process technique,the layout reuse technique is demanded on the market.The existing layout should be compacted to fit for the new process technique. An efficient 2\|D compaction algorithm is proposed,which is based on the constraint graph expression of the figures on layout and newly designed rules.In order to do compaction on the chip level, a hierarchical strategy and the ‘fall leaves pool’ data structure are used,regarding the interconnections as soft lines it also can add to jogs automatically.From the test cases it is shown that this compaction algorithm is practical and effective.
1 citations