Showing papers on "Emulation published in 1999"

Matching output queueing with a combined input/output-queued switch

Abstract: The Internet is facing two problems simultaneously: there is a need for a faster switching/routing infrastructure and a need to introduce guaranteed qualities-of-service (QoS). Each problem can be solved independently: switches and routers can be made faster by using input-queued crossbars instead of shared memory systems; QoS can be provided using weighted-fair queueing (WFQ)-based packet scheduling. Until now, however, the two solutions have been mutually exclusive-all of the work on WFQ-based scheduling algorithms has required that switches/routers use output-queueing or centralized shared memory. This paper demonstrates that a combined input/output-queueing (CIOQ) switch running twice as fast as an input-queued switch can provide precise emulation of a broad class of packet-scheduling algorithms, including WFQ and strict priorities. More precisely, we show that for an N/spl times/N switch, a "speedup" of 2-1/N is necessary, and a speedup of two is sufficient for this exact emulation. Perhaps most interestingly, this result holds for all traffic arrival patterns. On its own, the result is primarily a theoretical observation; it shows that it is possible to emulate purely OQ switches with CIOQ switches running at approximately twice the line rate. To make the result more practical, we introduce several scheduling algorithms that with a speedup of two can emulate an OQ switch. We focus our attention on the simplest of these algorithms, critical cells first (CCF), and consider its running time and implementation complexity. We conclude that additional techniques are required to make the scheduling algorithms implementable at a high speed and propose two specific strategies.

Matching output queueing with a combined input output queued switch

Abstract: The Internet is facing two problems simultaneously: there is a need for a faster switching/routing infrastructure, and a need to introduce guaranteed qualities of service (QoS). Each problem can be solved independently: switches and routers can be made faster by using input-queued crossbars, instead of shared memory systems; and QoS can be provided using WFQ-based packet scheduling. However, until now, the two solutions have been mutually exclusive-all of the work on WFQ-based scheduling algorithms has required that switches/routers use output-queueing, or centralized shared memory. This paper demonstrates that a combined input output queueing (CIOQ) switch running twice as fast as an input-queued switch can provide precise emulation of a broad class of packet scheduling algorithms, including WFQ and strict priorities. More precisely, we show that a "speedup" of 2 is sufficient, and a speedup of 2-1/N is necessary, for this exact emulation. We introduce a variety of algorithms that configure the crossbar so that emulation is achieved with a speedup of two, and consider their running time and implementation complexity. An interesting feature of our work is that the exact emulation holds for all input traffic patterns. We believe that, in the future, these results will make possible the support of QoS in very high bandwidth routers.

Network emulation in the VINT/NS simulator

Abstract: Employing an emulation capability in network simulation provides the ability for real-world traffic to interact with a simulation. The benefits of emulation include the ability to expose experimental algorithms and protocols to live traffic loads, and to test real-world protocol implementations against repeatable interference generated in simulation. This paper describes the design and implementation of the emulation facility in the NS simulator a commonly-used publicly available network research simulator.

Reconfigurable pipelined 2-D convolvers for fast digital signal processing

Abstract: In order to make software applications simpler to write and easier to maintain, a software digital signal-processing library that performs essential signal- and image-processing functions is an important part of every digital signal processor (DSP) developer's toolset In general, such a library provides high-level interface and mechanisms, therefore, developers only need to know how to use algorithms, not the details of how they work Complex signal transformations then become function calls, eg, C-callable functions Considering the two-dimensional (2-D) convolver function as an example of great significance for DSP's, this paper proposes to replace this software function by an emulation on a field-programmable gate array (FPGA) initially configured by software programming Therefore, the exploration of the 2-D convolver's design space will provide guidelines for the development of a library of DSP-oriented hardware configurations intended to significantly speed up the performance of general DSP processors Based on the specific convolver, and considering operators supported in the library as hardware accelerators, a series of tradeoffs for efficiently exploiting the bandwidth between the general-purpose DSP and accelerators are proposed In terms of implementation, this paper explores the performance and architectural tradeoffs involved in the design of an FPGA-based 2-D convolution coprocessor for the TMS320C40 DSP microprocessor available from Texas Instruments Incorporated However, the proposed concept is not limited to a particular processor

Dynamic emulation of mechanical loads using a vector-controlled induction motor-generator set

Abstract: This paper addresses the problem of electronic emulation of both linear and nonlinear mechanical loads using a vector-controlled induction machine dynamometer. It is shown that a basic emulation scheme where the dynamometer torque demand is derived from the inverse dynamics of the emulated load is not generally viable, especially if the emulated load is part of a closed-loop speed control system. A new feedforward speed-tracking control scheme for the dynamometer is presented, which preserves the load dynamics and allows for emulation of a large class of nonlinear loads. An experimental rig is described using vector-controlled induction machines as the drive motor and dynamometer, and experimental results showing excellent emulation of both linear and nonlinear load dynamics are presented.

Fault emulation: A new methodology for fault grading

Abstract: In this paper, we introduce a method that uses the field programmable gate array (FPGA)-based emulation system for fault grading. The real-time simulation capability of a hardware emulator could significantly improve the performance of fault grading, which is one of the most time consuming tasks in the circuit design and test process. We employ a serial fault emulation algorithm enhanced by two speed-up techniques. First, a set of independent faults can be injected and emulated at the same time. Second, multiple dependent faults can be simultaneously injected within a single FPGA-configuration by adding extra circuitry. Because the reconfiguration time of mapping the numerous faulty circuits into the FPGA's is pure overhead and could be the bottleneck of the entire process, using extra circuitry for injecting a large number of faults can reduce the number of FPGA-reconfigurations and, thus, improving the performance significantly. In addition, we address the issue of handling potentially detected faults in this hardware emulation environment by using the dual-railed logic. The performance estimation shows that this approach could be several orders of magnitude faster than the existing software approaches for large sequential designs.

A method and apparatus for evaluating software programs for semiconductor circuits

Abstract: A microcontroller software testing tool (100) for testing and debugging software for a target semiconductor circuit implemented as a dynamic link library (210). The microcontroller software testing tool (100) includes a simulator (300) for simulating the execution of the software program on the target semiconductor circuit and an emulator (400) to permit emulation before the actual silicon exists. The microcontroller software testing tool (100) includes a software development environment dynamic link library (220) monitors the estimated time to execute the software on the target semicondutor circuit and monitors the percentage of code that is executed during texting. In an emulation mode, the microcontroller software testing tool (100) utilizes a low-cost field programmable gate array programmed with a hardware description language description of the target semiconductor circuit. The features of the microcontroller software testing tool (100) are accessible by means of a data exchange protocol provided by the operating system.

A Trajectory for Validating Computational Emulation Models of Organizations

Abstract: Validation of complex simulation models is a challenging problem in computational organization theory research. In this paper, we describe a validation strategy suitable for emulation simulation systems, and show how a comprehensive validation consists of a sequence of steps that evaluate different aspects of a computational organizational simulation model. We demonstrate how this strategy can be applied to the evaluation of the Virtual Team Alliance (VTA), an emulation simulation system designed to guide managers charged with organizational change. VTA required a “trajectory” of successive validation experiments, before managers where willing to follow the recommendations of VTA. Ultimately, we believe this validation approach can be applied to a wide range of different simulation systems, and will make identification of the strengths and weaknesses of organizational simulations easier.

Optimising Bytecode Emulation for Prolog

Abstract: Byte-code representation has been used to implement several programming languages such as Lisp, ML, Prolog, or Java. In this work, we discuss the impact of several emulator optimisations for the Prolog system YAP. YAP obtains performance comparable or exceeding well-known Prolog systems by applying several different styles of optimisations, such as improving the emulation mechanism, exploiting the characteristics of the underlying hardware, and improving the abstract machine itself. We give throughout a detailed performance analysis, demonstrating that low-level optimisations can have a very significant impact on the whole system and across a range of architectures.

Integrated circuit with emulation register in JTAG JAP

Abstract: An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control.

Method and apparatus for patching program text to improve performance of applications

Abstract: The present invention relates to a method and an apparatus for patching program text to improve performance of applications running on a computer through the elimination of table lookup and emulation.

A new framework for debugging globally optimized code

Abstract: With an increasing number of executable binaries generated by optimizing compilers today, providing a clear and correct source-level debugger for programmers to debug optimized code has become a necessity. In this paper, a new framework for debugging globally optimized code is proposed. This framework consists of a new code location mapping scheme, a data location tracking scheme, and an emulation-based forward recovery model. By taking over the control early and emulating instructions selectively, the debugger can preserve and gather the required program state for the recovery of expected variable values at source breakpoints. The framework has been prototyped in the IMPACT compiler and GDB-4.16. Preliminary experiments conducted on several SPEC95 integer programs have yielded encouraging results. The extra time needed for the debugger to calculate the limits of the emulated region and to emulate instructions is hardly noticeable, while the increase in executable file size due to the extra debug information is on average 76% of that of the executable file with no debug information.

Buffer memory requirements in DSP applications

Abstract: Studies synchronous multi-rate data flow graphs to determine the minimal required buffer sizes that still guarantee the construction of a deadlock-free static schedule. We develop a rule to quickly analyze a graph's consistency. A graph is split up into single and parallel paths. Single paths are analysed, as well as the most frequent parallel paths. The results are used in the rapid prototyping environment GRAPE-II in the case where the emulation hardware contains FPGAs, or when memory is critical. >

Methods, data structures, and computer program products for representing states of interaction in automatic host access and terminal emulation using scripts

Abstract: Host interaction and terminal emulation sessions are conducted between a client and a resource by transitioning between terminal emulation states that represent interaction between the client and the resource. Transitions from a present terminal emulation state to a next terminal emulation state is automatically performed based on output provided by the resource and the present terminal emulation state. The terminal emulation may thereby be provided by ScriptUnits XML tags that represent the transitioning of terminal emulation states. The ScriptUnits can be parsed to create an object tree that can be manipulated using a visual editor. The visual editor may be used to change existing states in the terminal emulation session and add new states. The visual manipulation may allow a person who is unfamiliar with source programming languages to support the terminal emulation services. The format of the script representation may allow one vendor to import a script from another vendor to process in the importing vendor's internal structure without affecting the external terminal emulation programs.

Improving the observability and controllability of datapaths for emulation-based debugging

Abstract: Growing design complexity has made functional debugging of application-specific integrated circuits crucial to their development. Two widely used debugging techniques are simulation and emulation. Design simulation provides good controllability and observability of the variables in a design, but is two to ten orders of magnitude slower than the fabricated design. Design emulation and fabrication provide high execution speed, but significantly restrict design observability and controllability. To facilitate debugging, and in particular error diagnosis, we introduce a novel cut-based functional debugging paradigm that leverages the advantages of both emulation and simulation. The approach enables the user to run long test sequences in emulation, and upon error detection, roll-back to an arbitrary instance in execution time, and transparently switch over to simulation-based debugging for full design visibility and controllability. The new debugging approach introduces several optimization problems. We formulate the optimization tasks, establish their complexity, and develop most-constrained least-constraining heuristics to solve them. The effectiveness of the new approach and accompanying algorithms is demonstrated on a set of benchmark designs where combined emulation and simulation is enabled with low hardware overhead.

Entertainment/information system having disparate interactive devices

Abstract: An information/entertainment system having a number of interactive input and output devices is provided. Each interactive input device is electrically connected to a selected output device using a host that communicates with a router apparatus. The router apparatus includes a plurality of emulation assemblies. Each emulation assembly is configured to communicate input information to a particular interactive output device. Input information from a particular interactive input device is received and properly handled by a pre-configured emulation assembly which is electrically connected to the interactive output device associated with that particular interactive input device. This emulation assembly formats the information/data that it receives so that it is acceptable to the interactive output device to which it is connected. The host obtains input information using a slot/subslot arrangement associated with interactive interrogations or polling. The slots/subslots enable the system to obtain inputs at different transmission rates from different interactive input devices.

Functional verification of the equator MAP1000 microprocessor

Abstract: The advanced VLIW architecture of the Equator MAP1000 processor has many features that present significant verification challenges. We describe a functional verification methodology to address this complexity. In particular, we present an efficient method to generate directed assembly tests and a novel technique using the processor itself to control self-tests and check the results at speed using native instructions only. We also describe the use of emulation in both pre-silicon and post-silicon verification stages.

System and method for presenting multiple sheetlets on a medium surface while presenting multiple logical pages within the sheetlets

Abstract: A method and document presentation system utilize at least one N-up instruction together with at least one emulation instruction to cause multiple sheetlets to be presented on a surface of a physical sheet while multiple logical pages are presented within the multiple sheetlets. The at-least-one N-up instruction specifies that first and second logical pages are to be presented within a first sidemap and that a third logical page is to be presented within a second sidemap. The at-least-one emulation instruction specifies that said first sidemap is to be presented within a sheetlet on first area of a surface of a physical medium and that the second sidemap is to be presented within a second sheetlet on a second area of that surface.

Method for adaptive test generation via feedback from dynamic emulation

Abstract: A function for adaptively generating test vectors to verify the behavior of a digital system. The function utilizes one or more user-defined verification directives for directing the generation of the test vectors to areas of interest within the digital system. An emulator of the digital system provides dynamic feedback of internal state information to the test vector generation function during the verification. The test vector generation function adaptively generates future verification test vectors based on the user-defined verification directives in view of the internal state information feedback received from the emulator.

Advanced read cache emulation

Abstract: A low complexity approach to DASD cache management. Large, fixed-size bands of data from the DASD, rather than variable size records or tracks, are managed, resulting in reduced memory consumption. Statistics are collected for bands of data, in order to improve upon the performance of a simple LRU replacement scheme. The statistics take the form of a single counter which is credited (increased) for each read to a band and penalized (reduced) for each write to a band. Statistics and LRU information are also collected for at least half as many nonresident bands as resident bands. In an emulation mode, control information (e.g., statistics and LRU information) regarding potentially cacheable DASD data, is collected even though there is no cache memory installed. When in this mode, the control information permits a real time emulation of performance enhancements that would be achieved were cache memory added to the computer system. Dynamic reconfiguration of the cache size is also permitted in real time without requiring computer system downtime.

Fast prototyping: a system design flow applied to a complex system-on-chip multiprocessor design

Abstract: This paper describes a new design flow that significantly reduces time-to-market for highly complex multiprocessor-based System-On-Chip designs. This flow, called Fast Prototyping, enables concurrent hardware and software development, early verification and productive re-use of intellectual property. We describe how using this innovative system design flow, that combines different technologies, such as C modeling, emulation, hard virtual component re-use and CoWare N2C/sup TM/. We achieve better productivity on a multi-processor SOC design.

Concurrent legacy and native code execution techniques

Abstract: A method and apparatus for emulating instructions of a microprocessor (“legacy instructions”) with an incompatible instruction set which provides increased throughput relative to known emulation systems. In particular, each word of legacy memory is translated into an opcode/operand field and a dual function vector/tag field. The vector field represent addresses to legacy instruction emulation routines. The tag field is indexed to table of “thunk” objects, which can be used for various purposes. Such purposes include a disabling part of the legacy software, augmenting the legacy software with native software, and gathering execution statistics without modifying the legacy software.

PVM Emulation in the Harness Metacomputing System: A Plug-in Based Approach

Abstract: Metacomputing frameworks have received renewed attention of late, fueled both by advances in hardware and networking, and by novel concepts such as computational grids. Harness is an experimental metacomputing system based upon the principle of dynamic reconfigurability not only in terms of the computers and networks that comprise the virtual machine, but also in the capabilities of the VM itself. These characteristics may be modified under user control via a "plug-in" mechanism that is the central feature of the system. In this paper we describe our preliminary experience in the design of PVM emulation by means of a set of plug-in.

Peer networking in concentrated computer clusters

Abstract: A presently disclosed network oriented multiprocessing system, concentrated into a small space, uses a LAN (local area network) emulation protocol to transmit data packets directly between processing subsystems of the system via a bus connecting the processing subsystems. The processing subsystems and bus thereby constitute components of a virtual LAN defined by the LAN emulation protocol. The system also contains a storage subsystem which is connected to the same bus and is not a part of the virtual LAN. The spatial concentration of the system allows the bus to be operated at a speed sufficient to enable the processing subsystems to share access to the storage subsystem via the bus for retrieving stored information immediately relevant to program processes being executed in respective processing subsystems. Signal processes on said bus representing transfers relative to said virtual LAN are distinctly different from signal processes on the bus that are used to transfer information between said storage and processing subsystems. The virtual LAN defined by the LAN emulation protocol contains a virtual port for each processing subsystem currently active in the virtual LAN. This virtual port construct serves to maintain compatibility between software applications which define the LAN protocol and operating system software which supports both the LAN applications and other applications. The LAN emulation protocol permits each processing subsystem to independently initiate a failure communication to the other processing subsystems as well as to independently remove itself from and re-insert itself into the virtual LAN. It also permits any processing subsystem to conduct a “broadcast” data packet transfer to all other processing subsystems.

Exploiting FPGA-features during the emulation of a fast reactive embedded system

Abstract: This paper presents the emulation of an embedded system with hard real time constraints and response times of about 220μs. We show that for such fast reactive systems, the software overhead of a Real Time Operating System (RTOS) becomes a limiting factor, consuming up to 77% of the total execution performance. We analyze features of different FPGA architectures in order to solve the system performance bottleneck. We show that moving functionality from software to hardware through exploiting the fine grained on-chip SRAM capability of the Xilinx XC4000 architecture, that feature eliminates the RTOS overhead by only a slight increase of about 28% of the used FPGA CLB resources. These investigations have been conducted using our own emulation environment called SPYDER-CORE-P1.

System and method for intelligent analysis probe

Abstract: A system and method are described for providing intelligence to an analysis probe being utilized by logic analyzers. The system provides for regenerating target system internal processor data signals for analysis by a logic analyzer from data lines that are being utilized for other purposes by the target system processor. In particular, the analysis probe includes programmable logic for providing an interface between an emulation module and the target system, a memory for receiving signal reconstruction data from the emulation module, a processor for generating a data map from signal reconstruction data, and programmable logic for generating a target system internal signal from at least one of a plurality of target system data signals and the signal reconstruction data.

Fast prototyping: a system design flow for fast design, prototyping and efficient IP reuse

Abstract: This paper describes a new design flow that significantly reduces time-to-market for highly complex multiprocessor-based system-on-chip (SOC) designs. This flow, put in place within STMicroelectronics and which is called fast prototyping, allows concurrent hardware and software development, early verification and enables the productive re-use of intellectual property. We describe how using this innovative system design flow, that combines different technologies, such as C modeling, emulation, hard virtual component re-use and CoWare N2C, we achieve better productivity on a multiprocessor SOC design.

Performance analysis of a RTOS by emulation of an embedded system

Abstract: We analyze the performance of two different real-time operating systems. Therefore, we used a real benchmark embedded system design with fast external reaction times of about 220 /spl mu/s. We show that for such fast reactive systems, the software overhead of a real-time operating system becomes a limiting factor. We analyze the influence of novel microcontroller features, e.g., different on-chip caches, which tend to accelerate execution, but make it less predictable. These investigations have been conducted using our own emulation environment called SPYDER-CORE-P1.

Classical Illustrations of CP Violation in Kaon Decays

Abstract: It is easy to construct classical 2-state systems illustrating the behavior of the short-lived and long-lived neutral $K$ mesons in the limit of CP conservation. The emulation of CP violation is more tricky, but is provided by the two-dimensional motion of a Foucault pendulum. Analogies are drawn between the pendulum and observables in neutral kaon decays. An emulation of CP- and CPT-violation using electric circuits is also discussed.