Showing papers on "FET amplifier published in 1988"

On the choice of optimum FET size in wide-band transimpedance amplifiers

Abstract: The main figure of merit for transimpedance amplifiers used in amplifying photocurrents in fiber-optics systems is the optical sensitivity. This sensitivity is determined by the equivalent input noise current of the amplifier. To obtain the best noise performance, most transimpedance amplifiers with FET input stages are designed using a result that prescribes making the capacitance of the input FET equal to the photodiode capacitance. It is shown that this is not necessarily the most favorable practice when using FETs in scaled submicrometer technologies. For example, it may compromise the stability of the amplifier. >

Monolithic integration of InGaAs p-i-n photodetector with full ion-implanted InP JFET amplifier

Abstract: A monolithically integrated p-i-n FET amplifier, fabricated using ion-planted indium-phosphide (InP) JFETs, is described. The vertically integrated structure consists of a vapor-phase epitaxy (VPE)-grown InGaAs photoabsorption layer and a metal-organic-chemical-vapor-disposition (MOCVD)-grown Fe-doped semi-insulating layer. A Zn diffusion was performed to complete the p-i-n photodiode. High-performance fully implanted InP JFETS were used to form the integrated amplifier with a symmetrical design to remove the DC offset. With a receiver sensitivity of -36.4 dBm measured at 200 Mb/s NRZ for 10/sup -9/ BER, it is thought to be the most sensitive monolithic p-i-n FET preamp yet reported in this frequency range. The p-i-n amplifier has a dynamic range of 15 dB. >

Polarisation-independent configuration optical amplifier

Abstract: A new polarisation independent semiconductor laser amplifier is presented. By using a regular semiconductor amplifier in a double pass configuration, polarisation independent gain is achieved. Experiments demonstrate a reduction in the gain difference between TE and TM waves from 4dB to 0.2 dB.

Track-and-hold amplifier

Abstract: A track-and-hold amplifier system comprises an added switching means (23) for adding compensatory signals to a second input of an operational amplifier (10) used in the system.

Differential amplifier incorporating negative resistance

Abstract: A differential amplifier capable of achieving a large amplification, a wide frequency range, a high common mode rejection ratio, and a wide dynamic range simultaneously includes a device to produce negative resistance connected to output terminals. The differential amplifier also includes level shift circuits to generate additional voltages.

High-efficiency 5-watt power amplifier with harmonic tuning

Abstract: An X-band power amplifier using harmonic tuning and a GaAs FET is described. The amplifier has demonstrated 36% power-added efficiency with 5 W of output power and a 6.0-dB gain at 10 GHz. The key to this design is determining and matching the optimum load impedance for power-added efficiency at the first two harmonics. Nonlinear models were used to study the effects of harmonic tuning and to determine the optimum harmonic terminations. Two amplifiers were designed that demonstrated high-efficiency power amplification at the 0.5-W and 5-W power levels, respectively. The effects of harmonic loading were demonstrated in the 0.5-W amplifier, where the maximum efficiency measured for a device tuned only at the fundamental was 44%, while the measured efficiency of the amplifier with optimum harmonic tuning was 49.3%. >

Cmos power operational amplifier

Abstract: A CMOS power operational amplifier with large output voltage swing and high noise rejection is obtained by coupling a folded cascode type differential input stage and an output stage comprising an intermediate signal shifting amplifier and two common source output stages. Constant current generators inject into the drain of grounded gate MOS transistors pairs of said folded cascode type stage and of said intermediately signal shifting amplifier, respectively, a current which is pulled out of the source of the same grounded gate transistors by other constant current generators for increasing the effective transconductance of said grounded gate transistors pairs.

The dual-fed distributed amplifier

Abstract: A conventional microwave distributed amplifier consists essentially of a gate artificial transmission line and a drain artificial transmission line which have common active components in the form of MESFETs that provide the gate-and-drain-line shunt capacitances. Such amplifiers have an input port to the gate line and an output port from the drain line. The unused gate and drain ports are terminated in the appropriate characteristic impedances. A method is presented or a dual-fed distributed amplifier, using a small number of MESFETs, in which the gain is significantly increased and the noise figure significantly reduced by feeding the signal power into both gate-line ports. Provided the amplifier operates under small-signal (linear) conditions, superposition will apply to its operation, and the output due to two forward gain signals will add to produce the total output power. This arrangement increases available gain from the amplifier in comparison with its conventional mode of operation and a concommitant reduction in noise figure. Examples verifying the design are discussed. >

Power amplifier combiner for improving linearity of an output

Abstract: A high power amplifier combiner for improving the linearity of an output of an amplifier. At least two prelinearizers are used to suppress all distortion products by using feedforward cancelling techniques. The effects of compression associated with the operation of the high power amplifier are reduced.

Microprocessor-controlled amplifier

Abstract: An amplifier circuit having an FET connected in series with a resistor coupled to a constant voltage source, coupled between a pair of amplifiers, such as audio amplifiers in a two-stage amplifying circuit. The FET specifically and directly determines the amount of gain of the two-stage amplifier, or the like. RDS of the FET is continually monitored by its connection to one input of an amplifier serving as a comparator, with the other input thereof serving as a reference voltage derived from a modulated signal emanating from a microprocessor. Each of the signals VDS, and the reference from the microprocessor is filtered through a low pass filter to remove the audio, or other cyclical signals, and, in the latter case, in order to provide a substantially constant reference voltage to the input of the comparator. The output of the comparator is coupled to an RC circuit, the capacitor thereof being continually charged and discharged in response to the state of the output of the comparator. The output from the RC circuit is coupled to the FET to define the gate voltage of VGS thereof, which in turn determines the value of RDS , to thereby continually alter RDS, to thereby provide the gain so desired and specifically required in the amplifying circuitry. Such value is inherently defined by the modulated reference signal emanating from the microprocessor.

Low-voltage oscillator with separate startup mode

Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

Differential amplifier with common-mode bias feedback

Abstract: A differential amplifier includes a pair of input transistors for directing portions of a load current from a current source through a pair of load transistors in response to a differential input signal. A common mode output voltage of the differential amplifier is detected and applied to control terminals of a pair of feedback transistors. The feedback transistors couple the load transistors to a reference voltage and act therewith to provide control currents through the load transistors concurrent with the load currents. The control currents provide feedback that maintains the common mode output voltage at a constant threshold level.

Voltage variable FET resistor with chosen resistance-voltage relationship

Abstract: A voltage variable FET resistor includes a FET network comprising a plurality of FET segments each of which have a predetermined gate width and a voltage divider network including a plurality of fixed resistors coupled to the gates of the plurality of FET segments for providing a different gate width of each of the FET segments and the resistance of each of the fixed resistors is chosen to provide a predetermined relationship between the control voltage and the channel resistance of the voltage variable FET resistor.

Bi-MOS logic circuit having a totem pole type output buffer section

Abstract: A totem pole type output buffer section comprises a pull-up NPN bipolar transistor and a pull-down NPN bipolar transistor. These NPN bipolar transistors are selectively switch-controlled by a first MOS FET. Another NPN bipolar transistor is darlington-connected to the pull-down NPN bipolar transistor, and is switch-controlled by the second MOS FET. The second MOS FET is of the same conductivity type as and has a gate connected to a gate of the first MOS FET.

High speed logic circuit having feedback to prevent current in the output stage

Abstract: An improved FET capacitance driver logic circuit having an inverter feedback stage 22 connected from output to input of output FET 23 to allow the output FET to have a large capacitance charging current surge followed by a reduced conduction thereafter.

Variable attenuator having voltage variable FET resistor with chosen resistance-voltage relationship

Abstract: A variable attenuator having first and second branch circuits configured in bridged T, T or PI topologies, each of the branch circuits having at least one voltage variable FET resistor. The voltage variable FET resistor includes a FET network comprising a plurality of FET segments each of which have a predetermined gate width and a voltage divider network including a plurality of fixed resistors coupled to the gates of the plurality of FET segments for providing a different predetermined gate voltage to each of the FET segments. The gate width of each of the FET segments and the resistance of each of the fixed resistors is chosen to provide a predetermined relationship between the control voltage and the channel resistance of the voltage variable FET resistor, to thereby provide a preselected relationship between the control voltage applied to the first branch circuit and the attenuation ratio of the attenuator.

Distributed fet amplifier and bias voltage supply circuit therefor

Abstract: A distributed FET amplifier comprising an array of FET elements each having a gate terminal, a drain terminal and a source terminal. The gate terminals of the adjacent FET elements are connected by a first inductor, and the drain terminals of the adjacent FET elements are connected by a second inductor. Between the source terminals of each of the FET elements and the ground is connected a parallel circuit comprising a capacitor having a capacitance greater than the gate-source capacitance of the FET element and an impedance element connected in parallel to the capacitor for grounding the direct current. A bias voltage supply circuit for supplying a bias voltage to such as distributed amplifier is also disclosed.

Quasi-monolithic 4-GHz power amplifiers with 65-percent power-added efficiency

Abstract: A highly miniaturized C-band 1-W GaAs FET amplifier, part of a three-stage power amplifier for communications satellite applications, has been designed, fabricated, and tested. It achieves a maximum power-added efficiency of 65%, and occupies an area of 0.20 by 0.36 inches. The circuit uses a low-reactance termination at the second harmonic and low-loss quasimonolithic circuitry. Intermodulation distortion performance at intermediate and high drive levels was found to be comparable to that of a class A amplifier. These results were obtained on the first fabrication run and with no circuit tuning. >

A high efficiency Ka-band monolithic GaAs FET amplifier

Abstract: A monolithic three-stage Ka-band GaAs FET power amplifier has been designed and fabricated on MBE (molecular-beam epitaxy)-grown material with a highly doped (8*10/sup 17/ cm/sup -3/) channel. Devices with gate length of 0.25 mu m and gate width of 50 mu m, 100 mu m, and 250 mu m were cascaded. The gate and drain bias networks were also integrated. A maximum small-signal gain of 26 dB was obtained with 4 V on the drain and 0 V on the gate. When biased for large-signal operation, the amplifier was capable of generating 112 mW output power with 16-dB gain and 21.6% power-added efficiency at 34 GHz. It is believed that this is a record efficiency for a GaAs MMIC (microwave monolithic integrated circuit) amplifier at this frequency. >

Mixer circuit for use in a tuner of a television set or the like

Abstract: Disclosed is a mixer circuit which employs four FET's in a manner so that a source electrode of a first FET and a source electrode of a second FET are connected to a first terminal, a source electrode of a third FET and a source electrode of a fourth FET are connected to a second terminal, a first impedance circuit is connected between the first terminal and the earth, a second impedance circuit is connected between the second terminal and the earth, a first high frequency input terminal is connected through a first switching circuit to a junction between the first impedance circuit and the first terminal, a second high frequency input terminal is connected through a second switching circuit to a junction between the second impedance circuit and the second terminal, a gate electrode of the first FET and a gate electrode of the fourth FET are connected to a third terminal, a gate electrode of the second FET and a gate electrode of the third FET are connected to a fourth terminal, a drain electrode of the first FET and a drain electrode of the third FET are connected to a fifth terminal, a drain electrode of the second FET and a drain electrode of the fourth FET are connected to a sixth terminal, and an electric source supply circuit is connected to the fifth and sixth terminals. Phase-reversed local oscillation signals are fed to the third and fourth terminals.

Microwave power combining fet amplifier

Abstract: A microwave power combining FET amplifier includes T-type branch circuits (13,14) for power splitting and for power combining, and interstage matching circuits (6a,6b) respectively corresponding to a plurality of multistage FET amplifiers (3a,3b,4a,4b). Predetermined positions (a,b) opposing to each other respectively at the interstage matching circuits are connected by a resistance circuit (15) having a predetermined resistance value. Accordingly, it is possible, without including a power splitting circuit and a power combining circuit using a branch-line type coupler or Wilkinson type coupler, to perform the equivalent function to the amplfiers employing the power splitting and power combining circuits using these types of couplers. The arrangement is simplified and the shape is made small in size, and it is particularly suitable when the invention is to be realised by using a monolithic integrated circuit.

Symmetric integrated amplifier with controlled DC offset voltage

Abstract: A symmetric integrated FET amplifier is disclosed which exhibits a DC offset voltage that is insensitive to power supply variations, as well as variations in the threshold voltages of the FETs forming the amplifier. These variations are known to be most prevalent in InP-based FET amplifier arrangements. The symmetry is achieved by using a pair of impedance matching elements in the input stage of the amplifier to essentially match the impedance of the input FET and its load element, and a matching buffer FET and diode level shifting arrangement are used to match similar elements present in the output branch of the amplifier structure. The impedance matching elements, as well as the level shifting diodes, may all be formed with FET structures to minimize fabrication problems. In accordance with the symmetric arrangement of the present invention, the output DC offset voltage will be maintained at zero volts, regardless of the variations noted above. A multistage symmetric amplifier may then be formed simply by directly connecting a number of single stage symmetric amplifiers together in series.

Pyroelectric sensor with high sensitivity

Abstract: A pyroelectric sensor circuit arrangement for reducing noise and increasing sensitivity has a main current amplifier with a high feedback resistor connected to receive input from an electrode of a pyroelectric element, and includes a compensation amplifier in a unity gain amplifier configuration connected to a common power source with the main amplifier. The compensation amplifier is connected to discharge transients from the pyroelectric element when electrode voltage exceeds the positive voltage or goes below the negative voltage of the power source. A pair of anti-parallel diode or similar component is connected between the main amplifier input and the compensation amplifier output.

Gallium arsenide power monolithic microwave integrated circuit

Abstract: A gallium arsenide monolithic microwave integrated circuit amplifier comprising a first stage having a common gate field effect transistor to provide matching of the input impedance, a second stage having a common source field effect transistor to provide class A gain, and a third stage having a common source open drain field effect transistor to provide class B gain for the amplifier. This monolithic integrated circuit amplifier provides a gain of greater than 25 decibels over a frequency band of 400 Hz-1.5 GHz.

Current sense amplifier with low, nonlinear input impedance and high degree of signal amplification linearity

Abstract: A current sense amplifier includes first and second current mirrors cross-coupled to collectors of first and second transistors having a common base connection to a bias voltage circuit. First and second load devices are connected to the collectors of the first and second transistors, the emitters of which are connected to control transistors of the second and first current mirrors, respectively. The control transistors also receive first and second input currents, respectively. The collectors of the first and second transistors are connected to output terminals of the current sense amplifier.

Read-out amplifier for photovoltaic detector

Abstract: A read-out amplifier (200) for a photovoltaic detector (201) employs an integrating amplifier (203) with capacitor feedback (230) during a self-calibrating active load (205, 240) to minimize debiasing of the photovoltaic detector during its operation. The self-calibrating active load reduces the effect of noise and threshold nonuniformities of the semiconductor devices (202, 203, 204, 205) used in the read-out amplifier circuitry.

Optimization of the optical sensitivity of p-i-n FET receivers

Abstract: The optimization of the input stage of a p-i-n FET receiver is discussed, with emphasis on the implications for an integrated InP/InGaAs p-i-n FET technology. In the early stages of development of this technology, it is necessary to keep the design simple, which implies that the device will consist of a single-stage, low-gain amplifier. Design criteria for such an amplifier are presented, and it is shown that the transimpedance configuration provides better sensitivity than a voltage amplifier, even when the gain of the amplifier is very small. It is also shown that the gate capacitance (i.e. width) of the input FET which optimizes the sensitivity is much smaller when the amplifier gain is low than it is in the high-gain limit. >

Static type semiconductor memory with multi-stage sense amplifier

Abstract: Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage snese amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.

Very high gain positive feedback CMOS transconductance amplifier

Abstract: This invention is for a transconductance amplifier. The amplifier has an amplifier input and an amplifier output with an amplifier output impedance. An input stage of the amplifier has a first transconductance. An intermediate state is coupled to the amplifier output through positive feedback. The intermediate stage has a second transconductance and an intermediate stage output having an intermediate output impedance. The gain of the amplifier is a function of the first transconductance times the second transconductance times the amplifier output impedance times the intermediate output impedance.

Ka-band monolithic GaAs FET power amplifier modules

Abstract: Monolithic GaAs FET power amplifiers consisting of several power-combined devices are fabricated and evaluated. The baseline monolithic chip design consists of a single stage 400- mu m FET amplifier and a six-way traveling-wave power divider/combiner with a single-stage amplifier in each of the six arms. Several chip combinations were used to make a 1-W amplifier with 5-dB gain and a 0.55-W amplifier with 27-dB gain at 34 GHz. A two-way hybrid combining scheme making use of 0.6-W monolithic chips producing 1 W of output power is also described. >