Patent
High speed logic circuit having feedback to prevent current in the output stage
TLDR
In this paper, an improved FET capacitance driver logic circuit has been proposed to allow the output FET to have a large capacitance charging current surge followed by a reduced conduction thereafter.Abstract:
An improved FET capacitance driver logic circuit having an inverter feedback stage 22 connected from output to input of output FET 23 to allow the output FET to have a large capacitance charging current surge followed by a reduced conduction thereafter.read more
Citations
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Patent
Inverting output driver circuit for reducing electron injection into the substrate
TL;DR: In this paper, a pull-up field effect transistor (FET) was used to track the source voltage in an output driver circuit, which reduces electron injection into the substrate by the drain of the circuit's pullup transistor.
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High output drive FET buffer for providing high initial current to a subsequent stage
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Latch circuit for a programmable logic device using dual n-type transistors
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Journal ArticleDOI
Feedback FET logic: a robust, high-speed low-power GaAs logic family
TL;DR: Feedback FET logic with a special output stage that enables it to drive high on-chip capacitances with low power is discussed, and FFL is robust in the face of process and temperature variations.
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Logic circuit using Schottky barrier FETs
TL;DR: In this article, a logic circuit using Schottky barrier FETs comprising a plurality of circuits (10, 12) con-nected in series between first and second power supply terminals is described.
References
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Journal ArticleDOI
Analysis of GaAs FET's for integrated logic
K. Lehovec,R. Zuleeg +1 more
TL;DR: In this article, the authors present an analysis of the speed and power dissipation of various GaAs FET inverter circuits as prototypes of integrated logic circuit design, providing analytical expressions to assess the switching performance of enhancement-mode and depletion-mode MESFET's and JFETs with respect to switching-speed and power-dissipation capabilities in optimized configurations.
Patent
MOS output buffer circuit with feedback
TL;DR: In this paper, a PMOS output buffer circuit with a feedback circuit incorporated into the buffer acts to limit the drive current for negative potential output excursions, so that the output characteristics can be set independently of process variables.
Patent
Current limiting MOS transistor driver circuit
TL;DR: In this paper, a current limiting driver circuit (10) receives a first logic level input signal (φ 1 ) and drives an output pin (26) to ground by a pull-down transistor.
Patent
Current limiting output circuit with output feedback
TL;DR: In this paper, a pull-up and pulldown pull-down push-pull driver circuit with an output stage having a pullup and a pulldown IGFET for driving an output node is described.