Showing papers on "Gate driver published in 1976"

A high power MOSFET with a vertical drain electrode and a meshed gate structure

Abstract: A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.

Complementary mos logic circuit

Abstract: A dynamic complementary metal -oxide-semiconductor circuit (CMOS) includes a pair of gate stages connected in cascade. The first gate stage includes a first logic block which effects a prescribed logical function, the logic block being connected between a P-type and the N-type MOSFET. The source electrodes of the P-type and the N-type MOSFETs are connected between a power supply and ground, respectively, and their gate electrodes are connected in common. Moreover, the first gate stage has its output terminal connected to a load capacitor. The second logic block is also connected between a P-type MOSFET and an N-type MOSFET. The source electrodes of these MOSFETs are connected between a power supply and ground, respectively, while the gate electrodes thereof are connected in common. Also, a second load capacitor is connected to the output of the second gate stage. A pair of pulse signals, inverted with respect to each other, are applied to the first and second gate stages for driving the same, respectively. One of the MOSFETs making up the second logic block is of the type and is connected so that, when the power supply voltage applied to the gate thereof from the first gate stage, that MOSFET is turned "off". As a result, the possibility of misoperation due to the decrease in the charge of the first load capacitor, at the output of the first gate stage, is prevented.

A high performance low power 2048-bit memory chip in MOSFET technology and its application

Abstract: A static 2048-bit read/wire memory chip for main stores is described. It uses a modified 6-device memory cell in an n-channel MOSFET technology. To exploit the potential of the given MOSFET technology with respect to the cost/performance ratio and the power-delay product, special provisions are taken. The power is kept low by the gate driver concept as well as by clocked peripheral circuits. High performance is achieved with fast peripheral circuits, the delayed chip select concept, and a bipolar sense amplifier which also supplies the bit-line restore voltage. Circuits are presented which successfully utilize the on-chip tracking to reduce the impact of device parameter tolerances on worst case power and performance. It is shown how the memory chip is packaged on modules, cards, and boards to build up functional memory units.

Crystal controlled logic gate clock pulse generator

Abstract: A self-triggered clock pulse generator for high frequencies comprising an oscillating quartz crystal which is included in a loop together with a capacitor and a single, non-inverting gate. An averaging feedback is obtained by means of an inverting gate and an integrating circuit, which are connected in series between the output of the non-inverting gate and the input of the gate which is connected to the crystal.

Self-feedback type low-noise charge sensitive amplifier

Abstract: A so-called charge sensitive amplifier is used as a pre-amplifier for a semiconductor detector. A field-effect transistor (FET) is used as the input stage of the amplifier, wherein the gate terminal of the FET is fed back from the output of the amplifier and the drain terminal of the FET is grounded through a capacitor and connected to a constant current source to make the drain voltage change correspond to the gate potential. The gate potential is self-stabilized.

Gate input circuit for insulated gate field effect transistors

Abstract: In a gate input circuit for insulated gate field effect transistors, an insulated gate field effect transistor of depletion type is used, whose drain electrode (or source electrode) is connected to one terminal of a power source and whose source electrode (or drain electrode) is short-circuited with the gate electrode and connected to an input terminal of the gate input circuit through a resistor.

Conditional latch circuit

Abstract: A conditional latch circuit is selectively operable as a latch or as an OR gate. The circuit comprises an OR gate having at least three inputs, each connected to the output of separate ones of three AND gates. A fourth AND gate has an inverted output connected to an input of two AND gates and a non-inverted output connected to an input of the third AND gate. The output of the OR gate is connected to a second input of the third AND gate. With one input of the fourth AND gate connected to a binary clock source, the circuit will operate as a latch to store binary signals received at the second input of the first and second AND gates when the second input of the fourth AND gate is connected to binary one. When the second input of the fourth AND gate is connected to a binary zero, the circuit will operate as an OR circuit.

Logic gate utilizing charge transfer devices

Abstract: A logic gate utilizing charge transfer structures is disclosed which forms the building block for a TWO (2)-INPUT ADDER (HALF ADDER) and a THREE (3)-INPUT ADDER (FULL ADDER). The logic gate includes a first storage gate for receiving charge packets representing binary digital input signals. The storage gate couples in a first path to a first transfer gate which allows the storage gate to store only one unit quantity Q of charge and to transfer any excess quantity of charge to a master gate. The master gate is connected to a slave gate which causes the latter to operate as a barrier gate when the master gate contains a unit quantity Q of charge or to operate as a transfer gate when the master gate contains no charge. A control gate couples the first storage gate in a second path to the slave gate. The control gate exercises control over the transfer of charge in the second path until such time as the master gate can receive and store the excess charge from the first storage gate and thereby determine the appropriate state of the slave gate before the second path is allowed to transfer charge from the first storage gate.