Showing papers on "Ground bounce published in 1990"

Output buffer for reducing switching induced noise

Abstract: An output buffer for reducing switching induced noise in high speed integrated circuit devices incorporates a relatively small current carrying capacity secondary pulldown transistor (N1) element with the current path first and second terminal leads coupled in parallel with the current path first and second terminal leads of the primary pulldown transistor element. A separate pulldown (R1) delay resistance element of selected value is coupled in series between the control terminal leads of the secondary (N1) and primary (N3) pulldown transistor elements. The secondary pulldown transistor (N1) element control terminal lead is coupled in the output buffer to receive a signal propagating through the output buffer before the primary pulldown transistor (N3) element control terminal lead. A relatively small discharge current is therefore initiated from the output before turn on of the relatively large discharge current of the primary pulldown (N3) transistor element. The separate pulldown delay resistance (R1) element delays turn on of the primary pulldown transistor (N3) element a specified time delay after turn on of the secondary pulldown transistor (N1) element during transition from high to low potential at the output. As result ground bounce is divided into two spikes and the ground rise in potential is constrained to approximately one half that of conventional ground bounce levels. A secondary pullup transistor element with associated noise reduction components can similarly be used on the supply side to reduce Vcc droop.

Electostatic discharge protection circuit

Abstract: For electrostatic-discharge-protection, a first transistor is configured with the transistor channel connected between circuit ground and an associated (input or output) pad. In addition, transistors(s) are included configured to "float" the gate and/or the well of the first transistor when no power supply potential (Vcc) is present and to couple to circuit ground (or the power supply potential) the gate and/or the well of the first transistor when the normal power supply potential (Vcc) is present.

Cmos output buffer circuit with improved ground bounce

Abstract: A CMOS output buffer circuit for providing an output signal at an output terminal with a significant reduction in ground bounce includes a pull-up driver circuit (12), a pull-down driver circuit (14), and a control circuit (16). The pull-up driver circuit includes first and second resistive means for delaying the turn-on times of pull-up transistors. The pull-down driver circuit includes third and fourth resistive elements for delaying the turn-on times of pull-down transistors. Each of the first through fourth resistive elements (D1-D4) is formed of a transmission gate and serves to control the gate-to-source voltages applied to the respective gates of the pull-up and pull-down transistors.

Ground bounce limiting driver using non-linear capacitor

Abstract: A ground-bounce limiting circuit comprised of a non-linear Miller capacitance between the drain and the gate of an output driver. Ground-bound is limited by controlling the time-ramping of the output current by continuously diverting the charge at critical times and thresholds on the gate of the output driver which are being delivered by a predriver.

Output buffer with ground bounce control

Abstract: An output buffer is described which includes a plurality of pull up transistors (54) connected in parallel and/or a plurality of pull down (64) transistors connected in parallel. A desired amount of resistance (53, 63) is included in the path connecting the gates of the pull up transistors, and in the path connecting the gates of the pull down transistors, thereby providing a distributed RC network causing pull up and pull down transistors to turn on in sequence. This the rate of change of the pull up and pull down current constant, thus reducing ground and Vcc bounce. In another embodiment, a single pull up transistor and/or a single pull down transistor is used. The single transistors have a relatively high gate resistance such that along the channel width of the transistor, the gate capacitance and the gate resistance operates as a distributed RC network. In this manner, portions of the channel begin conducting sequentially, as is the case where a plurality of pull up and pull down transistors are used.

Push-pull output stage of integrated circuit providing enhanced high-low voltage level signal transition with ground bounce control

Abstract: A push-pull output stage of an integrated circuit for generating a pulse-like output signal in dependence upon a pulse-like input signal. The push-pull output stage includes complementary output field-effect transistors which are formed by respective first and second groups of parallel-connected subtransistors (P1 to P4; N1 to N4), the subtransistors in each group being of the same conductivity type and opposite from that of the subtransistors in the other group. A resistance element (TP0 to TP3; TN0 to TN3) is connected into the lead to each gate electrode of each of the subtransistors (P1 to P4; N1 to N4) of the two groups of subtransistors. A disconnecting field-effect transistor (PD1 to PD4; ND1 to ND4) is associated with each subtransistor (P1 to P4; N1 to N4) of the two groups of subtransistors. Connected in parallel with each group of subtransistors (P1 to P4; N1 to N4) is a control field-effect transistor (MN, MP) of respective opposite conductivity type which is connected as a source follower with respect to the input signal and the output signal. The subtransistors of each group and the resistance elements corresponding thereto form a distributed RC network to facilitate high-low voltage level signal transition of the signal during the operation of the integrated circuit, while the control transistor enhances the edge steepness of the signal in the center region of the signal when undergoing a transition. The push-pull output stage thereby inhibits ground bounce from the overshoot of the pulse-like signal which could cause an inaccurate interpretation of the voltage level of the pulse-like signal.

Anti-Noise circuits

Abstract: Low noise circuits for single stage and multi-stage circuits reduce power rail noise, including both ground noise and supply noise caused by output power rail ground lead and supply lead inductance. Anti-bounce circuits reduce ground bounce by suppressing turn on of the output stage pulldown transistor element during transient occurrence of ground bounce events. Similarly anti-droop circuits reduce output supply VCC droop by suppressing turn on of the output stage pulldown transistor element during transient occurrence of VCC droop events. Anti-undershoot circuits dissipate ground undershoot energy by establishing a transient sacrificial current flow through the parasitic output ground tank circuit following transition from high to low potential at the output and by prolonging the sacrificial current flow during transient occurrence of ground undershoot events. Similarly anti-overshoot circuits dissipate overshoot energy in the parasitic output supply tank circuit by establishing a sacrificial current flow during transient occurrence of VCC overshoot events. Ground noise and power noise detectors are used for detecting occurrence of bounce, droop, undershoot and overshoot for actuating and enhancing operation of the low noise circuits. The power rail noise detectors and anti-­noise circuits are combined in various combinations and permutations.

BiCMOS output driver

Abstract: A bipolar transistor (134) and two field-effect transistors (130, 132) are connected in a BiCMOS pull-down configuration to pull-down to a (first) predetermined potential level the potential developed on an output line when a high logic level potential is developed on an input line. To maximize switching speed and to minimize ground bounce (transients), the bipolar transistor is not permitted to go into saturation. A pair of transistors, connected in an inverter configuration, develop a signal which indicates when the bipolar transistor pulls-down the level of the potential on the output line below a (second) predetermined potential level. From a signal developed from the input line signal and a signal developed from the inverter developed signal, a gate develops a signal which drives a transistor (176) that pulls-down from the (first) predetermined potential level to a low logic level potential the output line potential three gate delay times after the output line potential level falls below the (second) predetermined potential level.

Tristable output buffer with state transition control

Abstract: Voltage on a circuit ground terminal in an output buffer is controlled by limiting induced voltage on a circuit ground pad as the output makes a transition from a high voltage level to a low voltage level thereby minimizing deleterious effects on other circuits connected to the common circuit ground terminal. A ground bounce circuit controls the bias on a transistor connecting the output to the circuit ground terminal with power saver circuitry limiting actuation of the ground bounce circuitry except during the high to low transitional phase.

Integrated circuit package

Abstract: There is disclosed an integrated circuit package assembly for housing an integrated circuit die wherein the integrated circuit package assembly affords substantially reduced ground bounce within the integrated circuit. The package assembly includes a planar electrically conductive sheet upon which the integrated circuit die is insulatively bonded. The integrated circuit package includes at least one ground lead which is coupled to a conductive ground pad on the integrated circuit by a first ground wire which connects the ground pad to the electrically conductive sheet and a second bond wire which connects the electrically conductive sheet to the ground lead. The assembly is completed by an encapsulation which encapsulates the integrated circuit die, the electrically conductive sheet, the first and second bond wires, and a portion of the ground lead.

Push-pull output stage of integrated circuit for reducing ground bounce noise

Abstract: A push-pull output stage of an integrated circuit for generating a pulse-like output signal in dependence upon a pulse-like input signal. The integrated circuit of which the push-pull output stage is a part is susceptible to high switching speeds in which the pulse-like signal varies between high and low voltage levels. The push-pull output stage inhibits the overshoot of the pulse-like signal leading to inaccurate interpretation of the pulse-like signal as having a high voltage level when the pulse-like signal actually has a low voltage level. The output stage includes output field-effect transistors comprising two groups (12, 14) of parallel-connected subtransistors (TN1 to TNn, TP1 to TPn). The gate zones of the subtransistors in each respective group are connected together. To the gate zones of the subtransistors (TN1 to TNn) of at least one (12) of the two groups (12, 14) a current dissipating or grounding transistor (TS1) is connected. The current grounding transistor (TS1) is the output transistor of a current mirror circuit (TS1, TS2, TS3, TS4) which is made up solely of field-effect transistors and to the input transistor (TS2) of which a current dependent on the input signal is supplied for controlling the current grounding transistor (TS1).

Sinusoidal signal generator

Abstract: A high current CMOS circuit including a raised cosine signal generator for generating a raised cosine signal waveform and an input circuit arrangement for controlling the raised cosine signal generator is described. The raised cosine signal generator includes an output node to which a controlled chain of CMOS inverters are connected. The input circuit arrangement accepts an input signal, converts it into appropriate signals which drive respective inverters so that simultaneous conduction of inverter pairs is prevented. The off chip driver (OCD) minimizes ground bounce, electrical noise and radiation problems caused by large current transients or spikes (di/dt) that usually accompany such circuits.

Method and apparatus for controlling noise on power supply buses

Abstract: A method and apparatus for controlling ground bounce and transient noise induced in an integrated circuits power supply buses by feeding back the input/output power supply bus voltages levels and comparing those levels to the internal logic power supply bus voltage levels. Significant noise transients on the input/output upper potential power supply bus will increase a resistance of a series element in each buffer circuit that drives a respective output driver and thereby increase the overall switching time of each buffer and output driver combination. Similarly, significant ground bounce voltages on the input/output lower potential power supply bus will increase a resistance of another series element in each buffer circuit driving its respective output driver and thereby increase the overall switching time of each buffer and output driver combination. Increasing the switching time is known to reduce noise transients caused by switching currents, but by only increasing the switching time when the noise transients caused by switching currents reach a troublesome level, the remainder data switching of the output driver may be provided at a higher data rate.

Method of fabricating a base-coupled transistor logic

Abstract: A base-coupled logic gate is characterized by input Schottky diodes that are directly formed on the base region of the switching transistor for the gate. A logic of this type provides flexible circuit arrangements and savings in required area, while achieving very high speeds. As a result of the savings in area, the buried layer capacitance of the gate is also reduced, which facilitates the high-speed operation of the circuit.

A 200 MHz 100 K ECL output buffer for CMOS ASICs

Abstract: The operation and design of 200-MHz 100 K ECL output buffers for CMOS ASICs are described. It is shown how the components of the buffer output driver transistor, gate voltage generator, and low skew input drivers are combined into unique clock and data output buffers. A section on unity gain op-amp design describes how a number of these buffers are used on an ASIC. Application guidelines (curves) to illustrate the tradeoff between the buffer frequency and the number of buffers on an ASIC application are presented. The advantages that this input buffer provides in the area of low ground bounce generation is presented. Waveforms from an ASIC with 24 balanced and 16 single ended ECL output buffers are presented. >

Ground bounce isolation and high speed output circuit

Abstract: An output buffer circuit advantageously uses a simple integrated circuit package including two separate ground leads for connection to an externally supplied ground voltage. The relatively large pull down current which passes through the pull down transistor of one or more output buffers are fed through a first ground lead of the lead frame to the external ground and the remaining circuitry is connected to the external ground through the second ground lead of the lead frame. The transients in the pull down current will cause ground bounce which affects the pull down transistor only, and not the remaining components of the output buffer. In this manner, base drive to the output pull down transistor is not decreased due to ground bounce, and the high to low transition of the output voltage is not degraded by the presence of ground bounce. In an alternative embodiment, the amount of ground bounce is controlled to provide a desired characteristic of the output transition.

BiCMOS Futurebus transceiver

Abstract: An advanced BiCMOS technology is used to build transceivers that provide incident edge switching on a Futurebus backplane with max prop delay time of 3 ns, and standby Icc of less than 4 mA. A Schottky diode between the driving transistor and the pad is reverse-biased so that pin capacitance is kept below 5 pf to minimize backplane loading. Open collector outputs drive 100 mA and allow wire-OR signals. Output voltage swings are between 1 and 2 V, and receiver thresholds are 1.55 V+or-0.07 V. Edge rates of 2 ns per volt, controlled ground bounce, and rounded curves where the driver begins and ends a voltage-swing help to control ringing on the stub, improve noise immunity, and suppress high-frequency signal components. Delay skew of less than 0.5 ns from pin to pin, and edge to edge, even during simultaneous switching, allows for high-speed, reliable data transfers. Transistor level circuits used to achieve these characteristics are shown, with resulting waveforms. >