Showing papers on "Integral nonlinearity published in 1994"

Histogram measurement of ADC nonlinearities using sine waves

Abstract: This paper gives results concerning the measurement of differential and integral nonlinearity of ADC's using the histogram method with a sine wave input signal. We specify the amount of overdrive required as a function of the noise level and the desired accuracy and the number of samples required as a function of the desired accuracy, the desired confidence level, and the noise level. An analysis of the effect on the results of harmonic distortion of the applied signal is given. The error analysis assumes a mixture of coherent and random sampling rather than pure random sampling. >

A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC

Abstract: This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-/spl mu/m CMOS process. The ADC operates at 600 ks/s using 45 mW of power at /spl plusmn/2.5 V supplies. The active die area excluding the external logic circuit is 1 mm/sup 2/. Maximum DNL of /spl plusmn/0.6 LSB and INL of /spl plusmn/1 LSB at a 12-b resolution have been achieved. >

A 10-bit pipelined switched-current A/D converter

Abstract: A modified RSD algorithm has been implemented in a switched-current pipelined A/D converter. The offset insensitivity of the RSD Converter reduces the effect of several nonidealities proper to current copier cells. Moreover, the benefits resulting from the large tolerances inherent to the RSD algorithm and the pipelined architecture result in an improved conversion rate. Measurements on a first prototype give an integral nonlinearity error less than 0.8 LSB for 10-bit accuracy. Power dissipation is 20 mW and silicon area is 2.5 mm/sup 2/. The measured sampling rate is 550 kS/s. It is an improvement by a factor of twenty compared to known equivalent CMOS switched-current converters. It is nevertheless still well below the predicted conversion rate of 4.5 MHz, which should be obtained once this A/D converter is integrated into an analog front-end. Full compatibility with standard digital technologies makes this kind of converter attractive for low power, medium-fast converters with 10-bit accuracy. >

A 6-bit, 4 GSa/s ADC fabricated in a GaAs HBT process

Abstract: A GaAs-AlGaAs Heterojunction Bipolar Transistor (HBT) process was developed to meet the speed, gain and yield requirements for Analog to Digital Converters (ADCs). A 6-bit, 4 GSa/s (4 giga-samples per second) ADC was designed and fabricated in this process. The standard HBT used has an emitter area of 1.4/spl times/3.0 /spl mu/m; it has current gain of over 70 at I/sub c/=1 mA and f/sub T/ and f/sub MAX/ of over 50 GHz at I/sub c/=4 mA. The process also includes Schottky diodes, thin-film NiCr resistors, MIM capacitors and three levels of metal interconnect. The ADC uses an analog folding architecture to reduce transistor count and power well below that of a straight 6-bit flash ADC. It includes an on-chip track-and-hold (T/H) circuit and Gray-encoded digital outputs for best immunity to dynamic errors. The ADC's measured differential nonlinearity is less than /spl plusmn/0.5 LSB and its integral nonlinearity is less than /spl plusmn/0.8 LSB. It has a resolution bandwidth (the frequency at which effective bits has dropped by 0.5 bits) of 2.4 GHz at 3 GSa/s and 1.8 GHz at 4 GSa/s, higher than any ADC published to date. The chip operates at up to 6.5 GSa/s, but linearity at that clock rate is much worse.

Analog-to-digital conversion and harmonic noises due to the integral nonlinearity

Abstract: Analog-to-digital conversion inherently introduces unwanted harmonic noises due to the nonlinear transfer function error. It is essential to set proper models of the noise generation mechanisms, to quantify and compare the analytic performance of the high-resolution measurement systems including analog-to-digital converter (ADC). We addressed the importance of the integral nonlinearity in the analysis of the ADC system. We modeled the nonlinearity via a linear combination of simple power functions with single parameters and calculated the magnitudes of the harmonic noises generated by the sigmoidal shape of the ADC transfer function, analytically and numerically. For a typical ADC, a model x/sup (1+/spl nu/)/+/spl mu/x/sup 2/ was reasonably adopted, which produced the most significant harmonic noises at the second-and the third-order multiples of the fundamental frequency. Practical examples of the high-resolution ADC were observed, and demonstrated to show that the simple model explains the harmonic noises. >

Apparatus and method for producing an analog output signal from a digital input word

Abstract: A digital-to-analog converter (DAC, 300) utilizes a coarse DAC (306) and fine DAC (315) to produce an analog output signal having both low glitch energy and good linearity performance. The DAC (300) also uses an error table (312) to store correction data generated through a calibration procedure. Outputs (307, 311) from each DAC (306, 315) are summed to produce an analog output signal which exhibits better linearity than does the output (307) of the coarse DAC (306) alone.

A low-power, CMOS peak detect and hold circuit for nuclear pulse spectroscopy

Abstract: A low-power CMOS peak detecting track and hold circuit optimized for nuclear pulse spectroscopy is presented. The circuit topology eliminates the need for a rectifying diode, reducing the effect of charge injection into the hold capacitor, incorporates a linear gate at the input to prevent pulse pileup, and uses dynamic bias control that minimizes both pedestal and droop. Both positive-going and negative-going pulses are accommodated using a complementary set of track and hold circuits. Full characterization of the design fabricated in 1.2 /spl mu/m CMOS including dynamic range, integral nonlinearity, droop rate, pedestal, and power measurements is presented. The circuit operates with only 250 /spl mu/w for input pulses with 7 /spl mu/s peaking time. Power consumption was increased to 750 /spl mu/w for driving off-chip and test system capacitances. Analysis and design approaches for optimization of operational characteristics are also discussed. >

A 13-Bit 10-Mhz Adc Background-Calibrated with Real-Time Oversampling Calibrator

Abstract: A real-time digital-domain code-error calibration technique is developed and demonstrated in this fully-Merential5-volt 13-bit IO-= BiCMOS ADC. The calibration process does not interfere with the normal operation of the converter but improves its linearity in real time while the converter is working. The core of this technique is an oversampling sigma-delta ratio calibrator working synchronously with the converter in background.' 1. Introdiictiou Existing self-calibration techniques for data converters interrupt normal conversion cycle for calibration[ I]. Temperature variation, device parameter drift, etc., may cause the calibration data to become invalid unless the converter is periodically re-calibrated. Other analogdomain calibration techniques are limited by the analog signal accuracy and circuit noise[2]. A novel digital-domain, code-error background calibration technique is implemented in this experimental 13-bit 10-MHZ ADC. The calibration procedure is virtually trans arent to the normal converter operation, thus allowing tg e converter to operate continuously even while being calibrated. 2.Real-Time Digital Calibration Technique In a multi-stage type ADC, the linearity of the D-to-A converter @AC) in the first stage determines the overall transfer characteristics of the ADC. To calibrate the ADC it is necessary to correct the linearity error of the fist stage DAC. In this ADC, a resistor-string DAC is used in the first stage because it allows both the calibrator circuit and the ADC amplifier to tap different DAC outputs simultaneously without affecting each other, provided that the DAC outputs settle within the clock phase. The DAC output errors are digitized by the calibrator and later subtracted from the raw output codes with the code-error calibration technique[3], To measure the resistor DAC error, a ratio-measurement method has been used. A switched-capacitor subtracter is used to measure the mid-point voltage error of a given section of the resistor string. A simplified diagram is shown in Figxe 1. Assuming ideal conditions,C, = C2 = C,,

CAMAC standard high-speed precise spectrometer

Abstract: The paper describes the CAMAC Standard Precise High-Speed Spectrometer for X-ray and gamma spectrometry designed for applications in a high-speed spectroscopy systems with requirement to obtain the high spectroscopy performance The spectrometer contains the controlled HV (high voltage) source, spectroscopy amplifier (later-amplifier), ADC (analog to digital converter) with buffer memory, CAMAC Grate controller hardware and software for PC In this paper only the most important units, that determine quality and throughput performance of spectrometer are considered The spectrometer has main features: maximum registration speed, pps, no less-150000; maximum input count rate, pps, -1000000; integral nonlinearity, %, no more -007; differential nonlinearity, %, no more -05; shaping symmetrical quasi-Gaussian; pile-up rejector dead time, ns, -100; ADC dead time, /spl mu/s, -1, 7 Spectrometric data are processed and displayed on PC >

An eight-channel time-to-digital converter on a VME board

Abstract: An eight-channel time-to-digital converter in a one-slot VME module has been developed. It is based on eight TAC sections and a 1 μs conversion time ADC unit with 12 bit resolution. Start and Stop input signals can be either NIM or ECL pulses and the Common-Start mode is available. The full-scale time range can be on-board selected between four values from 100 to 800 ns. The integral nonlinearity is less than ±0.04% for all ranges. The Low and High thresholds of any channel and other functions can be remotely controlled.

Analysis and design of adaptive self-trimming technique for A/D converters

Abstract: A novel self-trimming algorithm for A/D converters has been presented which continually trims thresholds in the flash A/D subconverters of two-stage and pipelined A/D converters. Roughly speaking, it trims thresholds up or down by small increments in such a way as to smooth out irregularities in the code density. This paper presents the mathematical analysis and design of the algorithm. The algorithm was analyzed by a novel two-dimensional z-transform (Z-T), which can be used to demonstrate its stability, predict convergence rate, and which can be used to give a frequency-domain interpretation of the distinct properties of differential and integral nonlinearity. >

Low-current digital-to-analog converter

Abstract: A current-multiplying digital-to-analog converter (DAC) produces a low-current output which has significantly reduced current spikes or "glitches" resulting from the inherent capacitances of the switching transistors. A transistor connected in what would normally be the output line of the DAC establishes a voltage which varies in proportion to the current in that line. This voltage is applied to the control terminal of a transistor in a second current line to regulate an output current which can be made very low without experiencing significant glitches. A DAC having differential outputs (actual and complementary values) is described.

Monolithic charge-to-amplitude converter circuit as a building block of a wide dynamic-range A-to-D conversion system

Abstract: A monolithic charge-to-amplitude converter integrated circuit (QAC) was developed using bipolar Analog Master Slice technology. The QAC employs a current splitter to meet with a wide dynamic-range Q-to-A conversion system. The QAC also has an adjustment mechanism for the output voltage. We examined the QAC regarding the input impedance, the transfer function and the integral nonlinearity.

Measurement and estimation of system nonlinearity via a neural network

Abstract: This paper defines the degree of nonlinearity as a measure for the nonlinearity of the system. A method for estimating the nonlinearity is proposed based on the input and the output time-series signals under the actual condition that the additive observation noise is included. The degree of nonlinearity of the system takes a value between 0 and 1. It approaches 1 when the part of the variational power that cannot be represented by the linear combination of the input increases in the output variation depending on 0-input in the linear system. A multilayer perception is introduced as a parametric function which represents the wide class of nonlinear functions needed in the estimation. An example is shown of the family of memoryless and nonlinear systems where the degree of nonlinearity changes from 0 to 1 by the change of the system parameter. An example also is shown of the system with a finite memory having a degree of nonlinearity of 1. By a computer simulation, the validity of the nonlinearity estimation proposed in this paper is demonstrated. The method will be applied effectively to the modeling of the system based on the observed input and output signals.

A 14-b 2.5 MSPS pipelined ADC with on chip EPROM

Abstract: A 14-b 2.5-MSPS, multi-stage pipeline, subranging analog-to-digital converter is presented. In addition to conventional laser-wafer-trim, on chip, "write once" EPROM is used to calibrate inter-stage gain errors at package sort. Integral nonlinearity errors as small as +/- 2LSB, and differential nonlinearity errors of -0.6, +0.8 LSB have been achieved. The 5.4 mm by 4.4 mm device includes a 2.5-V reference is built on a 2-/spl mu/m 10-V BiCMOS process and consumes 550 mW of power.

A Digital Self Compensation Circuit for High Speed D/a Converters

Abstract: This paper presents a digital self compensation method for video-rate D/A converters(DAC's). In this method, the compensation operation is isolated from the high speed operation of the current switch. Therefore, the errors of each element of the device can be corrected without interrupting the device operation. This method was implemented using standard 0.8 pnt CMOS technology. The measured Integral Nonlinearity of the IO-bit CMOS DAC decreased to 0.22LSB.