Showing papers on "Master clock published in 1987"

Time synchronization method in data transmission system

Abstract: A method for synchronizing the times of a master clock provided in the master station and slave clocks provided in the slave stations in a data transmission and receiving system consisting of the master station as a data transmission control station and slave station and/or stations for two-way data transmission. An encoded time survey command including master clock time is transmitted from the master station to each slave station. This is followed by an encoded response from each slave station which includes the slave clock time, from which the transmission delay to and from the slave station is determined along with the time difference between master and slave clocks. Time correction data is then transmitted to correct the time of the slave station clock.

A method and a system for synchronizing clocks in a bus type local network

Abstract: The invention relates to a method of synchronizing clocks contained in a local network of bus type, such as Ethernet and a system of synchronizing clocks. In local networks of this kind a number of nodes (1-3) are connected to a common data channel (4). The object of the invention is to obtain a method and a system of synchronizing the clocks which is more accurate than previous methods and systems, in which the synchronizing information is transmitted as common data packages in which the receiver of the synchronizing information does not know the instant of the data package generation. According to the invention a synchronizing message is transmitted from one node which has been chosen to be the master to all nodes, the master node inclusive. When receiving a synchronizing message the nodes read the clock state. Then the master node transmits a clock time message containing the master node clock state when it received the synchronizing message. The clock state indicated by the received clock time message is compared in the slave nodes with the clock states which have been read in the slave nodes. The clock states of the read clocks are compared with the received master clock state and the clock stats of the slave nodes are corrected in dependence on the outcome of the comparison. The clock synchronizing according to the above is suitable for, e.g., military applications.

Method and apparatus for establishing a system clock in response to the level of one of two clock signal sources

Abstract: A system clock is produced either from clock signals (t1) recovered in a clock regenerator, based on surface wave filtered technology and having level fluctuations, or from the digital clock signals (t2) internally generated in, for example, an access controller of a ring network, in response to the level of the regenerated clock signals (t1). The change in the source of the system clock is accomplished after an early detection of the level fluctuations, so that the clock signal (t1,t2) currently connected to the clock line are disconnected and, after a short delay time, the other clock signal (t1,t2) is sychronously switched to the clock line.

Digital transmission system

Abstract: The present invention relates to a digital transmission system provided with a transmitter 11 and a receiver 12, wherein the transmitter 11 comprises a first clock extracting device 13, 14 for detecting a synchronizing signal contained in a first digital audio interface (DAI) format signal from the receiver 12 and generating a first clock signal of a predetermined frequency in being phase-locked with the synchronizing signal, a data read-out device 4 for reading out data from a recording medium on the basis of the first clock signal, and a first encoder 5 for encoding the data from the data read-out device 4 in a second digital audio interface (DAI) format signal on the basis of the first clock signal, while the receiver 12 comprises second clock extracting device 6, 7 for detecting a synchronizing signal contained in the second DAI format signal and generating a second clock signal of a predetermined frequency in being phase-locked with the synchronizing signal, a decoder 8 for decoding data from the second DAI format signal on the basis of the second clock signal, an oscillator 3 for generating a master clock, D/A a converter 9 for digital-to-analog converting the decoded data on the basis of the master clock, and a second encoder 15 for encoding the master clock to derive the first DAI format signal, whereby the system is synchronously operated by the master clock in a manner that digital-to-analog conversion can be effected with a timing clock signal which is not mixed with jitter.

Master/slave synchronizer

Abstract: A synchronizer (100, 102, 104, 106) is disclosed operable in a variety of modes. In a Master/Slave mode the synchronizer receives synchronizing clock signals from a device to which it is a "slave" and generates therefrom synchronizing clock signals to a device to which it is a "master". In a Slave/Slave mode the synchronizer receives synchronizing clock signals from two devices to which it is a slave. In this mode the synchronizer can buffer misalignment between the clocks and report their phase difference for corrective action. In a Slave mode, the synchronizer only receives a synchronizing clock signal. A data-routing multiplexer (50, 108, 110) is employed in conjunction with the synchronizer which allows five devices to be connected to the synchronizer. Signals may be routed between any of the devices. Buffers (112, 120, 122) internal to the data-routing multiplexer perform the frame alignment function.

TDM transmission system

Abstract: A time division multiplex transmission system includes: a time division multiplex encoder for supplying a master clock to a plurality of PCM digital signal sources having a same sampling frequency and a same quantization bit number to effect clock synchronization and generating a time-divisionally multiplexed data signal based on a data word not D/A converted and sampled from each digital signal source; a transmission line for transmitting the multiplexed data signal from the time division multiplex encoder; and a time division demultiplex decoder for selecting a desired transmitted, multiplexed data signal and demultiplexing the selected data signal in accordance with a transmission rate before the time division multiplexing.

Method of jumping composite PN codes

Abstract: The present invention is concerned with an apparatus and a method of jumping a composite PN code from a current phase position to a desired predetermined phase position so as to enhance acquisition of a composite PN code. The apparatus includes a plurality of individual PN code generators which are connected to a code combiner to produce a composite PN code. Each of the individual PN code generators is driven by its own timing gate for supplying synchronized clock pulses to its own PN code generator. A master clock is connected to a timing gate before being connected to the individual PN code generators. An inhibit input at each of the individual timing gates is provided so that the individual PN generators may be inhibited a predetermined number of clock pulses which causes the PN code generated to be inhibited and has the effect of jumping the PN code a desired number of phase positions.

Universal null DTE

Abstract: A communication device in the form of data terminal equipment permits two data communication equipments, each having its own master clock and operating at substantially the same nominal clock rate, to communicate with each other in a multi-segment circuit configuration of a general communication network even when phase or frequency errors exist between the two clocks. Data transmitted between communication equipments of two segments of the communication network is buffered. A variable buffer fill circuit is provided to fill the buffer to a selectable extent prior to initiation of data output clocking. Selection switches are provided to select the degree of buffer preload. A dynamic buffer fill circuit may be incorporated for automatically selecting the buffer fill level as a function of the difference in clock frequencies of the two equipments. Controllable alarm circuitry is provided for selectively generating an underflow or an overflow alarm to one or both of the communicating equipments.

Digital FSK signal demodulator

Abstract: A demodulator for a phase coherent frequency shift keyed signal has a master clock which generates a signal having a plurality of pulses during each half of the bit internal of the FSK signal. A detector determines during which master clock pulse within several groups of X number of pulses the most transitions occur in the received signal. Based on the determined clock pulse, samples taken in each of two consecutive half-bit intervals of the FSK signal are selected for comparison to produce the demodulator output signal.

Circuit and method for performing equal duty cycle odd value clock division and clock synchronization

Abstract: A circuit for dividing a master clock by an odd integral value and producing a 50% duty cycle. A state machine develops set and clear signals which are of a timing proportion of n: n+1, where 2n+1 is the divisor value. The set signal is provided to one input of a bistable multivibrator or S-R latch to set the multivibrator to a given state, while the clear signal is combined with the master clock signal to delay or disable the clearing of the multivibrator by 1/2 count of the master clock, so that an n+1/2: n+1/2 proportion output clock signal is developed. Additionally, the circuit includes a state machine which determines which of a series of differing frequency master clock signals is active and when an external triggering event occurs so that the following rising edge of the output clock signal is delayed until a determined time after the triggering event to allow synchronization of the output clock signal.

System and device to interface asynchronous apparatuses

Abstract: A system for interfacing asynchronous machines. The system includes a single-port RAM (Random Access Memory) synchronized with the master clock of only one of the asynchronous machines, and a FIFO (first in/first out) memory. The devices to implement this system consist of a single-port RAM, an FIFO memory, two counters, one of which is a write counter and the other is a read counter, a multiplexer which selects one of the two counters, and a RAM access control logic which generates the RAM control signals and the counter enabling signals and the above mentioned multiplexer select signal.

Method of accessing local area networks with a unidirectional ring-transmission line, and local area network using this method

Abstract: A method of accessing a local-area network which allows transmission on a unidirectional ring, of circuit-switched or packet-switched communications organized in hybrid frames, in which overlapping between the beginning of a frame and a residual of the preceding frame which is still to reach its destination is avoided without reporting to a rigid band allotment to the indiviual communications and to a network synchronization system, where a well defined node acts as a master clock. According to the method the individual nodes of the network, access in sequence the transmission line in each frame, maintaining the same order of asynchronous access in the circuit and packet regions. To avoid overlapping between adjacent frames, in the packet region of each frame, starting from an instant preceding by a predetermined time period the end of the frame, the packet transmission by the node which has the right of access at the instant or by the nodes which would have the right of access from that instant to the end of the new frame, is disabled. y

Alarm information collecting device

Abstract: PURPOSE:To ignore invalid alarm information by adding parity bits to the alarm information detected by respective detecting units, transferring it and parity-checking respectively the alarm information by a collecting unit. CONSTITUTION:After the parity bits outputted from parity checker 112 and 122 are added to the alarm information detected from alarm detecting units 11 and l2, it synchronizes with a master clock and is sent bit by bit. In an alarm collecting unit 2, this serial alarm information synchronizes with the master clock and is fetched by a shift register and when the parity bits are also fetched, a timing pulse is generated from a timing pulse generating circuit 23 and a parity checker executes a parity check. When it is decided that the result is effective, an enable pulse is outputted, the timing pulse inputted to a data latch timing generating circuit 25 is outputted to a latch 24 as a latch pulse and the latch 24 latches effective alarm information.

Clock synchronizing system

Abstract: PURPOSE: To make a highly precise internal clock signal run by itself even at the time of trouble by inputting a highly precise self-running clock to a phase lock control system instead of an external clock having come defective CONSTITUTION: When a detection controlling means 14 detects that the trouble occurred in the external clock signal fE, the highly precise self-running clock signal fE* is inputted to the phase lock control system of a PLO circuit 1 so that the highly precise internal clock signal fI whose frequency and phase follow the self-running signal fE* is supplied to a network system Thus, a highly reliable clock device to supply the highly precise internal clock following the self running clock signal to the network at the time of the trouble of the external clock signal can be constituted by only connecting a low-cost crystal oscillator to the PLO circuit COPYRIGHT: (C)1989,JPO&Japio

Clock voltage supply

Abstract: A clock voltage supply for electronic control circuits such as a computer system for generating four clock signals which are synchronous as to frequency and phase. When n=4, the clock signals are generated with the help of four PLL clocks. So that the four clock signals can continue to appear even if one of the four clocks is malfunctioning, the clock signals of the four clocks are supplied to four (3:4) voters from whose outputs the clock signals are then supplied. Since each voter circuit brings about a certain delay time, which significantly limits the frequency of the clock signals, a delay element is connected downstream to each of the voter outputs respectively. The delay time of the respective delay element, plus the delay time of the respective voter connected therewith, is an integral multiple of the period of the intended clock frequency. For PLL control, the output of each delay element gives the nominal phase position and the output of each clock gives the actual phase position.

Increment/decrement sampling phase shifter

Abstract: An analog interface system interfaces with a digital signal processor. The system receives analog signals, digitizes those signals and transmits them to the signal processor upon completion of the conversion. The system directs transmission of digital data from the signal processor to the system, and converts it to analog as the output of the system. The digital signal processor determines whether the sampling rate of the D-to-A and A-to-D converters is correct for the rate at which the data is being received by the respective converters. If not, the DSP sends a number of master clock cycles to the system which then retards or advances the sampling rate of the converter by that number of clock cycles.

Clock switching circuit

Abstract: PURPOSE: To prevent the production of a high frequency pulse at switching by synchronizing a switching signal to output switchingly a master clock signal and a clock signal being the result of frequency-dividing the master clock signal with the master clock signal. CONSTITUTION: A frequency divider circuit 1 frequency-dividing a master clock signal MCLK, a selector 2 switching the signal and a clock signal CLK being the result of frequency-dividing the master clock by the said circuit and a synchronizing circuit 3 synchronizing a switching signal INT with the master clock signal MCLK and applying the result to the selector 2 are provided. The switching signal INT is synchronized with the master clock signal MCLK by the circuit 3 and the result is fed to the selector 2. Thus, the master clock signal MCLK in the selector 2 and the clock signal CLK being the result of frequency-dividing the master clock are switched synchronously in outputting them switchingly. Thus, no high frequency pulse is generated. COPYRIGHT: (C)1988,JPO&Japio

Multiple phase clock generator

Abstract: A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion of an enable signal and a prebias output signal from a preceding phase cell on the ring. Enable signals supplied to each phase cell around the ring are asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being provided concurrently. When initialized with one phase cell asserting its phased clock signal and prebias output signal, each transition of the master clock signal causes a next phase cell on the ring to supply its phased clock output signal.

Real time clocks versus virtual clocks

Abstract: Symmetric distributed termination algorithms are systematically developed. Solution are first presented in an abstract setting of Dijkstra, Feijen and Van Gasteren [DFG] and then gradually transformed into solutions to the distributed termination problem of Francez [F]. The initially used global real time clock is eventually replaced by local virtual clocks. A dependence between the degree of clock synchronization and the efficiency of the solutions is indicated.

High reliability system for network system

Abstract: PURPOSE:To prevent out-of-synchronism when plural clock sources exist by supplying a general common clock usually and supplying a private station clock when the clock is at fault, to the interface of respective lines. CONSTITUTION:Usually, one side of clocks 117 and 118 extracted from receiving data 106 and 111 by clock extracting devices 33 and 43 in NTT interfaces 31 and 41 is selected as a master clock 119 with a clock selecting part 52 in a clock deciding device 5. The clock 119 is supplied through PLLs 25, 35 and 45 to transmitting receiving LSI 22, 32 and 42, and transmitting data 102, 107 and 112 are transmitted by using the clock. On the other hand, when the losing of the clocks 117 and 118 is detected by a clock deciding part 53, a main/sub- switching part 6 is switched, and a clock 116 extracted from receiving data 101 with a clock extracting device 23 in a private station interface 21 is selected as the master clock 119 by a selecting part 52.

Compact disk player

Abstract: PURPOSE:To change the reproducing speed of a CD only with the operation of a switch or a volume by varying a self running frequency of a VCO of a PLL circuit, an oscillated frequency of a master clock generator by the switch of the volume of a speed selection circuit CONSTITUTION:In turning a switch of a speed selection circuit 20 to the position (b), the switch of the PLL circuit 51 and the switch of the master clock generator 71 are turned respectively to the position (b) and a CD 1 is reproduced by the same fequency and the same speed as those of a conventional player In turning the switch of the circuit 20 to the position (a), the switch of the PLL circuit 51 and the switch of the master clock generator 71 are turned respectively to the position (a), and the clock frequency is doubled Since a closed loop comprising a phase comparator 8, a motor servo circuit 9, a motor 10, the CD 1, a pickup 2, a waveform shaping circuit 4 and the PLL circuit 51 constitutes a PLL, the clock component of an EFM signal read from the pickup 2 has a double frequency Thus, the EFM signal is reproduced by the double speed and the CD is reproduced by a double speed

A high-performance variable sampling clock generator for the nearest neighbor sampling technique

Abstract: A variable sampling clock generator for two-dimensional image sampling is proposed that features very small point error in each scan line, fast frequency switching from one scan line to another, and phase coherency at sampling starting on each scan line. The sampling clock is generated by dividing a stable high-frequency master clock by integer values stored in a simplified master-clock divider ROM. The sample point error is kept below one half of the master-clock period on the whole image plane by the nearest-neighbor-sampling technique.

Display control clock generating circuit device

Abstract: PURPOSE:To attain the generation of a master clock and a display clock with one clock generation circuit by providing a 2/5 frequency dividing circuit which inputs a signal from the oscillation circuit of 13.5mHz, and a horizontal synchronizing signal. CONSTITUTION:The signal of 13.5mHz inputted from a clock input 1 is 2/5-frequency divided, and the signal of 5.4mHz can be obtained. In such a case, 13.5mHz is represented as 858fH (fH:horizontal frequency), however, even when it is multiplied by 2.5, an integer is not obtained, and as a result, when it is left as it is, the phase of a display clock at every H is dislocated. Therefore, a set pulse generated from the horizontal synchronizing signal is inputted to the clear terminal of a 10 bit counter, and again a synchronization with a horizontal is taken. By constituting a circuit in such a way, a clock generation circuit where two PLLs are used is eliminated and the generation of the clock can be performed with one PLL.

Clock control system and method for a parallel variable speed constant frequency power system

Abstract: A clock control system for a multiple channel electric power system includes a master clock circuit (28) and control circuitry (40) in each parallel connected channel. The channel control circuits are initially phase-locked to a master clock signal. If the master clock signal is out of a preselected frequency range, the indi­vidual channel control circuits (38, 40) are decoupled from the master clock signal and one of those circuits produces a backup clock signal. The control circuits in the remain­ing channels are then phase-locked with the backup clock signal to provide continued parallel system operation.

Data transmission equipment

Abstract: PURPOSE:To improve the reliability of communication and to facilitate the transfer of a control station or a communication station by applying phase matching so that the phase difference between a data from the communication station and a master clock at a control station reception end is kept within a premissible range CONSTITUTION:At the time of sending a data from communication stations CM1-n to a control station CT, the phase measurement data sent from the communication stations CM1-n is measured for the phase difference with a master clock MCK in the control station CT by a phase measurement circuit 18 The result of measurement is sent to a control circuit 17, then supplied to a reception signal processing section 3 via transmission lines 1a-na as a control channel data, and the data is sent with compensation to that the phase difference is kept within the permissible range

Rotary head type digital information signal recorder

Abstract: PURPOSE:To record digital information signals different in number of quantizing bits and sampling frequency by generating a system synchronizing system and a master clock from a word clock synchronized with digital input signals, and supplying data of each 8 bits made by halving 16 bits of one word to two PCM processors. CONSTITUTION:Digital output of a digital tape recorder is supplied to PCM processors 18, 19 of an 8mm VTR as input data together with a word clock. Two sets of PCM processors are provided and data of 8 bits made by dividing 16 bits of input data are supplied respectively to PCM processors 18, 19. PCM processors are operated in parallel by a master clock synchronized with the word clock and two output data are formed, and the two output data are recorded in different recording area of a magnetic tape 3. As sampling frequency is different, servo is operated making a system synchronizing signal formed by frequency dividing word clock of input digital data by rotation of rotary heads 1A, 1B a reference signal.

Buffer memory circuit

Abstract: PURPOSE:To reduce the fluctuation of the phase of a PLO clock and to simplify the delayed loading/unloading operation by supplying a pulse having the width equivalent to a cycle of the phase comparison frequency of the PLO produced from a master clock to an FF circuit which works with a PLO clock having the same frequency as the phase comparison frequency and using the output of the FF circuit of the writing or reading control. CONSTITUTION:The data 3 is written to a buffer memory 1 based on the writing control signal 23 obtained by differentiating a PLO clock 21 through a differentiating circuit 2. Then the data 2 is read out of the memory 1 based on the reading control signal 13 sent from a pulse generating circuit 3 synchronising with a master clock 1. Here the signal 23 has the variance of its phase to the signal 13. However, the signal 23 is produced through an FF circuit 9 works with a clock 22 obtained by dividing the clock 21 of a VCO 6 whose phase comparison frequencies 12 and 22 given to a phase comparator 5 of a PLL circuit 4 are higher than the synchronous frequency of the signal 23. As a result, the fluctuation of phase can be reduced less than the cycles of the writing and reading control signals.

Supervisory and controlling equipment

Abstract: PURPOSE:To correct automatically missing information obtained during the stopping period of a computer by forming a recording processor in a control part to record input information from each electric part during the stopping period of the computer and output the recorded information to the computer at the restoration of the computer CONSTITUTION:A supervisory and controlling equipment is provided with an electric computer 1, a CRT display device 3, an output typewriter 4, an information transmission equipment 5, and a master clock 2, and the recording processor 7 and an output typewriter 8 are added A stop condition from the computer 1 and a current time from the master clock 2 are inputted to a digital input circuit 74 of the recording processor 7 and display/measurement information outputted from the information transmission equipment 5 is entered and stored to/in a memory 72 at a fixed period When the computer 1 is restored, the contents of the display/measurement information stored in the memory 72 are transferred to the computer 1 through an interface circuit 73 and the state change and history of the display information during the stopping period of the computer and the missing information of the measurement information are automatically corrected

Digital pll circuit

Abstract: PURPOSE:To generate a data separation clock with high reliability by providing the 1st means extracting and inserting a prescribed period of clocks from data separation clocks and the 2nd means setting a period corresponding to a frequency near a peak of a frequency spectrum of a digital data as the compensation location of the 1st means. CONSTITUTION:A prescribed value is preset to a counter circuit 28 at the polarity inversion of an input data and the compensation is executed that one clock of a master clock B is extracted from a data separation clock PLCKB at the optimum compensation position (times T5, T6, T15) obtained from the frequency spectrum of the input data. Thus, the master clock having a frequency other than an integral number of multiple of the master clock to be used substantially is used to generate a data separation clock with high reliability in the very excellent PLL circuit.

Time information automatic setting system

Abstract: PURPOSE:To prevent the setting error and the time information left unset by providing an automatic outgoing device and an automatic incoming device having a voice recognition function on an electronic exchange and recognizing the time information from the source of No.117 and setting the time information automatically. CONSTITUTION:The time information subject to command-in by a test seat 11 is given to the automatic sender 10, a dial signal is sent from a test information driving and distributing circuit 6 to an exchange side and connected to a subscriber No. 117 being a telephone service special number, time information is inputted to the automatic reply device from the exchange and returned to a maintenance information processing unit 7 by the voice recognition function. The time information returned to the unit 7 from the No. 117 is edited into a time information setting format of an exchange command and sent to a master clock device 5 of the exchange. Thus, a master clock device set signal is sent from the unit 7 after a predetermined lead time from the time information sent to the master clock device 5. Through the operation above, the accurate time is set.