Showing papers on "Master clock published in 1992"

Measuring and monitoring system

Abstract: A system for monitoring power usage of various devices at remote facilities is described. The system employs sensors at each facility to sense the on/off condition of the devices. A processor at each facility, under the control of a host computer at a central location, stores the output data of the sensors in stripped-down form. The host computer specifies to the processor at each facility the time and date at which it should begin polling the sensors, the interval between pollings of the outputs of the sensors, the time and date at which the processor should report to the host computer and transmit the stored data, and the address location to be used when the processor initiates polling of the data. A master clock/calendar at the central location is used to synchronize the clock/calendars at each facility. Thus, only stripped-down data and power outage information are required to be stored by the processor and transmitted to the host computer, without the need to store or transmit any other data such as sensor identification or time and date of polling with each sampling of data. This results in reduction of memory storage requirements and transmission time. Alternatively, rather than storing the on/off condition of the devices, sensors which generate analog currents of voltages representing the amount of power being consumed by the device can be used in conjunction with A to D converters to digitize the information for storage and transmission to the host computer.

Bill recognizing apparatus

Abstract: Image data from a transported bill is read in response to a sampling clock and is stored. A clock generator generates a master clock faster than the sampling clock. The degree of skew of the bill is calculated in synchronism with the master clock. The stored image data is then corrected with the results of the skew calculation. The skew-corrected image data is then compressed and compared with predetermined dictionary data in order to recognize the bill.

Method of and apparatus for startup of a digital computer system clock

Abstract: A method of starting up a system clock that has been generated by a phase-locked loop, and circuitry for accomplishing that method. A low frequency master clock signal is distributed to circuits that generate high frequency local clock signals. These circuits generate the high frequency local clock signals using phase-locked loops in a frequency multiplier configuration. Lock indicator circuitry determines when the phase-locked loop has locked onto the master clock signal and then enables output buffers that then provide the high frequency clock signals to components in the system which need those local clocks.

Programmable secondary clock generator

Abstract: A secondary clock generator circuit is described in which a ratio is programmed into circuitry which will be embedded on all components. The programmable circuitry takes the system's master clock signal multiplies it by the programmed ratio and yields a secondary clock signal equal to the ratio times the master clock signal for driving components and interfaces. The invention is particularly useful in computer systems operating at a first clock frequency which have replaceable components that run at different clock frequencies and where it is desired to provide a synchronization between the system clock and the various component clocks.

Glitch-free clock multiplexer

Abstract: A multiplexer for selecting one of at least two input signals as the output on sensing the change in the state of a select input waits for the clock signal of the active first clock to transition to a predetermined state, disconnects the active first clock from the output of the multiplexer and maintains the output of the multiplexer in the predetermined state while waiting for the clock signal of a second clock to transition to the predetermined state. The second clock is connected as the multiplexer output while the clock signal of the second clock is in the predetermined state. In a preferred embodiment, the predetermined state is a low logic level.

Apparatus and method for testing electronic devices

Abstract: An apparatus 1 for testing mixed signal electronic devices (i.e., devices, such as LSI devices, whose input/output signals include direct current signals, digital signals and analog signals, where the time relationship between the various input and output signals may be either synchronous or asynchronous) includes a master clock subsystem (MCLK-SS) 11, a subsystem group comprised of a digital master subsystem (DM-SS) 12, a digital slave subsystem (DS-SS) 13, a waveform generator subsystem (WG-SS) 14, a waveform digitizer subsystem (WD-SS) 15, a time measuring module (TMM) 16, and a direct current subsystem (DC-SS) 17, and an interfacing test head 18. The MCLK-SS 11 receives a master clock from a timing generator 21 or DSP 23 of the device under test (DUT) 186 and generates a first master clock MCLK1 and a second master clock MCLK2, each of which is synchronized with the master clock from the DUT. A reference clock generator 111, which receives the output of the buffer 181, supplies a standard clock to the first and second clock generators 112, 113, which in turn generate the first and second master clock signals.

Method of and apparatus for correcting edge placement errors in multiplying phase locked loop circuits

Abstract: A method of starting up a system clock that has been generated by a phase-locked loop and correcting edge placement errors during coasting periods of the phase locked loop, and circuitry for accomplishing those methods. A low frequency master clock signal is distributed to circuits that generate high frequency local clock signals. These circuits generate the high frequency local clock signals using phase-locked loops in a frequency multiplier configuration. Lock indicator circuitry determines when the phase-locked loop has locked onto the master clock signal and then enables output buffers that then provide the high frequency clock signals to components in the system which need those local clocks. An intermediate frequency signal is fed back to the input of the voltage controlled oscillator in the phase locked loop to correct edge placement errors. A slightly earlier or leading version of the signal is used to correct cycle length variations without inducing duty cycle variations.

Qualified non-overlapping clock generator to provide control lines with non-overlapping clock timing

Abstract: A clocking methodology for VLSI chips which uses global overlapping clocks, locally or remotely generated non-overlapping clocks, combined with pipeline control signals to generate signals which control the transfer gates of registers in a pipeline. The signals which control the transfer gates of the registers in a pipeline maintain the important timing relationships of the non-overlapping clock signals combined with the control signals. The global overlapping clocks are used where possible to provide timing advantages, while the non-overlapping clocks are used to eliminate race conditions as data propagates down a pipeline of transparent registers. Overlapping clock signals are used whenever such race conditions can be avoided, as at the ends of the registered pipeline, with the resultant performance improvement.

Scan test circuits for use with multiple frequency circuits

Abstract: A scan path test architecture for testing circuits using multiple system clocks with different frequencies includes a controller (16) for disabling the system clocks during a test cycle and a master clock for generating a signal frequency signal to each circuit module (10a-c), eliminating the need for partitioning scan paths between modules and synchronizing system clocks.

Method and apparatus for the synchronization of a clock means of a telecommunication switching system

Abstract: Method and apparatus for synchronizing a clock of a telecommunication switching system. The clock of the telecommunication switching system is supplied, at least at times, with reference clock signals from a plurality of external reference clock sources. Every external reference clock source has a predetermined priority allocated to it. The supplied reference clock signals are checked for clock errors to which individual errors are allocated. For synchronization, the clock accepts an external reference clock signal dependent on the priorities allocated to the reference clock sources and dependent on the clock-error-associated error values. In an initialization, initial error values are allocated to the reference clock sources. In a re-initialization of the system, the synchronization procedure is continued from the current error values that are present at the time of the system outage.

Clocking system for asynchronous operations

Abstract: A clock mechanism in modules connected to a bus over which asynchronous operations are performed wherein clock pulses are generated that can clock the transmission or capture of data and the transitioning of acknowledge or synchronization lines. Each clock mechanism generates its clock pulses based on the receipt of signals associated with synchronization or acknowledge bus lines. The clock mechanism includes a multiplexer which provides to a resettable latch a signal associated with the condition of the selected line. The resettable latch, in conjunction with a delay element produces the clock pulses.

Dual transparent latch

Abstract: A dual transparent latch circuit is disclosed comprising two latches cross coupled together by two control lines to enable the latches collectively to input and output data at twice the frequency of the master clock frequency which controls the timing of each latch individually. The control lines are controlled by a clock generator such that one latch is enabled to receive and store data while the other latch is enabled to output data stored therein. At the same time, the latch receiving and storing the data is disabled from providing an output of the stored data and the latch providing the output is disabled from receiving and storing the data. The clock generator switches the states of the control lines such that they enable or disable the input of data to and output of data from the latches on each phase of the master clock signal. A dual transparent latch with triple edge timing is also disclosed. A method for generating a master signal having a master frequency and selectively enabling inputs at an input data rate greater than the master frequency to input data into memory and selectively enabling outputs at the input data rate to output data from memory.

Apparatus and method for generating synchronized control signals in a system for testing electronic parts

Abstract: A testing system for testing electronic parts allows coexistence of the complicated control of signal generation and measurement and the time management thereof, enables a testing of a DUT under an environment close to that of a real operating environment and improves reliability of the testing. Slave subsystems are operated under control and management of a master subsystem. Control signal synchronizing means synchronize control signals from the master subsystem with one of master clocks MCLK1 and MCLK2, and outputs the synchronized control signal to the slave subsystems through clock distribution means. The clock distribution means is controlled such that master clock whose timing is identical with the synchronized control signal is input to each slave subsystem.

Method of synchronizing signals of a pulse generator

Abstract: A digital architecture for a pulse generator provides a method of synchronizing signals of the pulse generator The pulse generator has a timebase card, a microprocessor and a plurality of pulse cards The microprocessor controls the parameters of the timebase card and pulse cards, and the timebase card provides a common master clock signal to all of the pulse cards determined by a triggerable voltage controlled oscillator that has two sources of frequency control voltage, an internal DAC for absolute frequency and a frequency comparison circuit for synchronization with an external timebase The pulse cards produce pulses, either singly or in bursts, with the leading and trailing edges being separately positionable using quantum, sliver and vernier controls A pattern RAM on each pulse card provides a pulse pattern that provides an approximation of the desired pulses to one quantum, and repeated iterations through the pattern RAM provide bursts of pulses Pattern RAMs on different pulse cards, where one pattern is related to the other by a power of two, may be synchronized since both channels use the same master clock from the timebase card Likewise a burst of pulses may be synchronized with the external timebase since the master clock is synchronized with the external timebase, with a frame sync input signal being used to determine the relative phase between the burst of pulses and the external timebase

Smart clock: a new time

Abstract: A tutorial description is given of the smart clock, which makes it possible for any clock to be automatically synchronized to an external standard with a minimum of measurements. The concept covers a range of applications from wrist watches and household clocks to the specialized world of high-accuracy clocks. The smart clock enhances the accuracy or stability of a clock or oscillator by characterizing it against an external standard. The smart clock algorithm uses optimal estimation and prediction to apply a correction to the output of the oscillator, maintaining any combination of time or frequency accuracy or stability within specified limits. The algorithm decides when external measurements are necessary to maintain the desired accuracy or stability. An example of how the smart clock could be used to maintain a simple clock to 1 s using measurements over the telephone lines is given. >

A dual PLL based multi frequency clock distribution scheme

Abstract: A clock generation scheme using two loosely coupled phase locked loops is presented. Each loop produces several clocks at different frequencies based on a single input clock. To minimize clock skew, a pipelined clock distribution structure is employed where clocks are resynchronized over multiple cycles en route to their destination. For low power applications, the design allows software to initiate a cycle-down mode, which causes all clocks to simultaneously divide down to lower frequencies by a programmable amount. >

Method and apparatus for synchronizing digital data steams

Abstract: A synchronization system for multiple CD players (12), (14), (16) and (18) includes a controller (20) that generates four separate sampling frequencies for input to the word clock inputs of the CD players. A master word clock provides a master clock signal that is input to CD player (12) and then multiplied by multiplier (40). The output of multiplier (40) is divided down by variable dividers (48), (50) and (52) to provide the sampling frequencies for the remaining CD players (14), (16), and (18). Each of the disks (54) has a header (80) disposed on the beginning of each of the program tracks. This header has a unique synchronization signal associated therewith that outputs data corresponding to the position of the output digital data. During output of the data associated with the header, a difference between positions of the different CD players is determined. This difference is stored in the controller (20) and then the divide ratios of each of the dividers (48), (50) and (52) adjusted to change the sampling frequency on the output thereof, resulting in a slipping of samples, until the difference between the sample frames of each of the CD players is set equal to zero.

Low skew CMOS clock divider

Abstract: A low-skew CMOS clock divider circuit for providing tracking of the divide-by-one and divide-by-two output signals obtained from a source of master clock pulses is fabricated using two matched flip-flops externally wired as divide-by-two devices. Coincidence gates are coupled with the outputs of the flip-flops to produce the desired divide-by-one and divide-by-two output signals in a manner such that the signals in each path pass through substantially identical circuit components, Thus, any delays encountered are the same in both circuit paths. In this manner, skew between the edges of the divide-by-two and divide-by-one clock signals is significantly reduced.

Satellite communication system

Abstract: PURPOSE: To easily take synchronization economically by using a ground system ISDN master clock especially so as to modulate and decode a video image or an audio signal in the satellite communication system in which digitized video image or audio signal is sent. CONSTITUTION: In the satellite communication system in which a transmission earth station 2 sending a digitized video image or a digitized audio signal via an artificial satellite 1 and a reception earth station 3 receiving the video image or the audio signal sent from the transmission earth station 2 make transmission reception of the video image or the audio signal synchronously with each other, the transmission earth station and the reception earth station extract synchronization clock from a ground system ISDN master clock respectively to keep the clock synchronization between the transmission earth station and the reception earth station thereby taking synchronization with each other. COPYRIGHT: (C)1994,JPO&Japio

Star optical network

Abstract: PURPOSE:To eliminate an overhead due to a preamble by operating all stations synchronously with a distributed clock at all times so as to make a time required for clock recovery actually zero. CONSTITUTION:A phase locked loop oscillator 10 is operated by a master clock supplied from a clock photodetector 9 and uses its output and a pseudo data in a wavelength lambdaD is sent. The signal is made incident on its own data photodetector 11 via a star coupler 21 and an optical multiplexer and demultiplexer 8. A phase comparator 7 outputs an error signal to a phase shifter 6 to adjust the phase shifter so that a phase shift in an output of the phase locked loop oscillator 10 is within a prescribed value in terms of the error signal. Thus, the phase of a transmission data is synchronized with the master clock, the station exits from the startup mode, the phase shift of the phase shifter 6 is fixed and the monopoly right of a bus is left. The procedure above is repeated to each slave station (node) to take synchronization of the entire system.

Clock synchronization system

Abstract: PURPOSE:To continue communication stably even when a gateway being a supply port of a clock is revised by providing a phase comparator in a phase locked loop on a gateway connecting to an external network and providing a loop filter and a voltage controlled oscillator on other node being a clock master node. CONSTITUTION:In the system where a network comprising plural networks through interconnection is operated synchronously with a clock signal fed from other network, a clock signal coming from an external network is extracted by gateways 2a, 2b normally and phase difference information is obtained by a phase comparator. When a decoder of a clock master node 1g extracts only phase difference information from some one gateway 2a and aborts other information and when the selected phase difference information is not received due to interruption of a transmission line or the like, the information from the other gateway 2b this far aborted thus is selected and a voltage controlled oscillator is controlled.

System clock switching mechanism for microprocessor

Abstract: This system clock switching mechanism for a microprocessor has system clock specification data for the tasks in holding means such as a task control block (TDB) (60). If there is no task in READY or RUN status, the clock switching control unit (40) switches the system clock to the low speed clock. When the task is put in RUN status, the system clock specification data for that task in TDB (60) is referred to so that the system clock is switched to the clock as specified.

Time-division-multiplexed data transmission system

Abstract: A time-division multiplex system is disclosed where the data from two sources is coupled over a multiplexer controller by a generator comprising an XOR gate and a pair of latches where the output of both latches are coupled to the XOR gate and an inverter at the input of each latch. One of the latches is gated by a master clock signal and the other latch is gated by a clocked signal skewed approximately one-half clock cycle.

Compact disc with synchronizing header

Abstract: A synchronization system for multiple CD players (12), (14), (16) and (18) includes a controller (20) that generates four separate sampling frequencies for input to the word clock inputs of the CD players. A master word clock provides a master clock signal that is input to CD player (12) and then multiplied by multiplier (40). The output of multiplier (40) is divided down by variable dividers (48), (50) and (52) to provide the sampling frequencies for the remaining CD players (14), (16), and (18). Each of the disks (54) has a header (80) disposed on the beginning of each of the program tracks. This header has a unique synchronization signal associated therewith that outputs data corresponding to the position of the output digital data. During output of the data associated with the header, a difference between positions of the different CD players is determined. This difference is stored in the controller (20) and then the divide ratios of each of the dividers (48), (50) and (52) adjusted to change the sampling frequency on the output thereof, resulting in a slipping of samples, until the difference between the sample frames of each of the CD players is set equal to zero.

Novel analogue VLSI design for multilayer networks

Abstract: The paper introduces a new pulsestream analogue VLSI design which has been optimised for the implementation of multilayer networks. The requirements of fully-trained multilayer perceptrons have been analysed to produce a set of specifications for the hardware design. The pulse-stream circuits described in the paper are driven from a fixed-frequency master clock, and a synaptic multiply-and-add computation is performed with every pulse. Detailed SPICE simulations have been carried out, and preliminary results from a set of test chips are also presented.

Magnetic recording and reproducing device

Abstract: PURPOSE:To correct the bit divergence of servo data without a delay line by writing the servo data based on delayed index signals and increasingly expanded master clock CONSTITUTION:A clock information prerecorded on a recording medium 10 is read by a magnetic head 11, amplified through a read amplifier 12, and then pulsified through a pulse generating circuit Then, index signals S3 is generated from a pulse train by an index decoder 15, and the same pulse train is increasingly expanded through PLL circuit 14 An index delay circuit 16 delays a timing to output index signals S3 according to a cyclinder address S4, outputs the delayed index signals S5 to a pattern generator 18, and write the servo data according to the delayed index signals S5 and the increasingly expanded master clock S2 Thus, the bit divergence of the servo data is corrected without the use of the delay line

Automatic time correcting system for system configuration element

Abstract: PURPOSE:To facilitate the check of time and to improve the accuracy for setting the time by constituting this system for time correction in which one configuration element is a master and the other is a slave, executing periodically a time request from the master, and executing the check of an error and the correction request of an error. CONSTITUTION:The system consisting of plural stations is formed as a master/ slave system consisting of one master station 1 (master) and other slave station (slave) for the time operation. Also, the time as the whole system is unified, based on the time of the master 1 as a reference. That is, the master 1 is provided with a master clock 4 which becomes the standard timepiece, a counter 6 for counting the number of times of a range check, etc., and executes a communication to the slave 2 through a circuit 3. In such a state, each slave 2 periodically informs the master 1 of its own time, and when the time of the slave 2 is in the outside of an allowable range of an error, the master 1 requests a time correction to the slave 2, based on its error value. In such a manner, the accuracy of time and the facility of a time check can be improved.

Seam-less data recovery

Abstract: A circuit for seamlessly printing data from a remote source that is arriving at a clock rate (Ext Clk) that is equal to the clock rate (Int Clk) of the local data, but that has a different clock phase, due to the longer path used by the remote data. The circuit generates a number of local clock phases (CLK01-CLKON), compares these phases to the phase of the remote clock (Ext Clk), and uses for both local and remote data the clock (Common CLK) whose phase is nearest that of the remote clock (Ext Clk).

Measuring circuit for edge time of input signal and digital pll device

Abstract: PURPOSE: To detect the edge position of an RF input signal in a time unit smaller than the cycle of a master clock MCK. CONSTITUTION: In regard of a 15-bit ring oscillator 30, a set of element states of each internal stage varies in a time unit smaller than the cycle of a master clock MCK and oscillates in a cycle larger than that of the clock MCK. A flip-flop circuit part 23 fetches the element state of each stage of the oscillator 30 by using the edge detection signal of an RF input signal RF in supplied from an input terminal 11. A subtractor 26 subtracts the numerical value showing the element state from the numerical value showing each stage state of the oscillator 30 that is fetched by a flip-flop circuit 27 in the timing of the clock MCK. Then the result of the subtraction is taken out as a signal that shows the input edge position. COPYRIGHT: (C)1994,JPO&Japio

Phase locked loop circuit

Abstract: PURPOSE:To prevent the self-running of a voltage controlled oscillator by selecting one from plural input reference clocks, oscillating the voltage controlled oscillator synchronously with the clock and selecting other clock when the input reference clock is abnormal. CONSTITUTION:A frequency dividing means 13 receives a 1st reference and one or two more 2nd reference clocks as input signals and outputs a reference clock having a prescribed frequency relation with a 1st reference clock. A selective circuit 14 selects one of output clocks of the frequency dividing means 13 and outputs the selected clock to a phase comparator 11. A fault detection circuit 15 receives the reference clock and controls the selective circuit 14 when the reference clock of the clock selected by the selective circuit 14 has a fault to select and output the other clock. Thus, when an input reference clock synchronously with the voltage controlled oscillator 12 is abnormal, other clock is selected so that the voltage controlled oscillator 12 is not subject to the self-running in an uncontrolled state and oscillates a master clock with stable accuracy at all times.