Showing papers on "Memistor published in 2023"

A Flexible Memristor Model With Electronic Resistive Switching Memory Behavior and Its Application in Spiking Neural Network

Abstract: Memristive technologies are attractive due to their non-volatility, high-density, low-power and compatibility with CMOS. For memristive devices, a model corresponding to practical behavioral characteristics is highly favorable for the realization of its neuromorphic system and applications. This paper presents a novel flexible memristor model with electronic resistive switching memory behavior. Firstly, the Ag-Au / MoSe2-doped Se / Au-Ag memristor is prepared using hydrothermal synthesis method and magnetron sputtering method, and its performance test is conducted on an electrochemical workstation. Then, the mathematical model and SPICE circuit model of the Ag-Au / MoSe2-doped Se / Au-Ag memristor are constructed. The model accuracy is verified by using the electrochemical data derived from the performance test. Furthermore, the proposed model is applied to the circuit implementation of spiking neural network with biological mechanism. Finally, computer simulations and analysis are carried out to verify the validity and effectiveness of the entire scheme.

CMOS-Based Memristor Emulator Circuits for Low-Power Edge-Computing Applications

Abstract: In this paper, an optimized memristor emulator circuit is designed, by using nine MOSFET transistors and a ground capacitor. Our area- and power-optimized emulator circuit can be used for basic data storage and processing at the monitoring edge, in real-time applications. The memristor shows a nonlinear voltage–current relationship, but no multiplier circuit provides the memristor’s nonlinear characteristics. As a result, the proposed memristor emulator has a very low chip area. The memristor circuit is designed in LTSpice, using 16 nm and 45 nm CMOS technology parameters, and the operating voltage is ±0.9 V. In this research, the theoretical derivations are validated using the simulated results of the memristor emulator circuit using different frequencies, capacitors, and input voltages in SPICE simulations.

Realization of memristor using multi-stationary point PSM characteristics

Abstract: The presence of turning points (stationary points like maxima and minima) in the Parameter-versus-state map (PSM) curve of a memristor can be beneficial in several memristive uses like multi-level logic design, multi-bit memories, and chaos generation circuits. Surprisingly the memristors with these types of PSM curves exhibit multiple crossing points in the transient input v-i contours. In this paper, the memductance model has been derived for such non-linear memristors exhibiting multi-cross-over characteristics. In the presented framework, the coefficients-related condition for the multi-turning point PSM curve has been derived, a necessary condition for the multi-crossing v-i contour. The condition related to the memristor operating parameters has also been reported taking both input signal and initial states into consideration. To realise the derived memductance model corresponding to the three cross-over memristive behaviour, an OTA-based memristor emulator has been developed. Unlike some existing fractional order non-symmetric multi-crossing memristor emulators, the proposed emulator circuit realises an integer order memristor function operating at moderate frequencies. The realised emulator uses only four OTAs and three grounded passive circuit elements with no external multiplier. For the CMOS implementation of employed OTA, the simulation results are obtained to verify the three pinch-off behaviour.

Memristor Crossbar Circuit for Ternary Content‐Addressable Memory with Fine‐Tuning Operation

Abstract: Memristor‐based ternary content‐addressable memory (TCAM) has emerged as an alternative to conventional static random‐access memory (SRAM)‐based TCAM because of its high‐density integration and zero‐static energy consumption. Herein, 0T2R TCAM operation on a 32 × 32 passive memristor crossbar circuit is experimentally verified. The effective margin, which is the difference between the match case and 1‐bit mismatch case, is improved through precise tuning operations. Moreover, the number of mismatch bits and match cases can be accurately detected thanks to the linear relationship between the number of mismatch bits and match‐line current. In addition, the nonideal effects in the passive crossbar array including dynamic voltage drop and sneak current are analyzed through SPICE studies. These results indicate that the proposed TCAM operating conditions can ensure stable TCAM operation in larger arrays.

Development of an Accurate Model for Memristor based Temperature Sensor

Abstract: Memristors are a unique class of electronic devices and have been considered one of the basic circuit elements along with Resistors, Capacitors, and Inductors. A memristor's built-in nonlinear ability is to remember how much charge has passed through it, and memristance is a charge-dependent resistance. This memristance is a variable value that depends on the change in width of the doped region (state variable) of the memristor that in turn depends on various factors like applied voltage, magnetic conditions, temperature, ionic mobility etc. As the temperature changes there is a change not only in the diffusion rate but also the lowest and highest attainable memristance. As there is a change in the memristance at a particular temperature and voltage the write time can be calculated. This research study investigates the possible write time at various temperatures and observe its effect with various window functions. This has been done through analytical modeling of memristor by employing existing non-linear window functions. These changes due to the effect of temperature can be used to model a temperature sensor at the nanoscale level which can significantly reduce the power and area consumption. A detailed study is presented in the current work. The uses of a temperature sensor are very wide and have great effect on exploration of memristor based sensors.

Modeling and circuit design for three-terminal memristors

Abstract: Abstract In this paper, a three-terminal memristor model is developed in order to improve the anti-interference performance of the memristor and address the issue that the resistance value of the conventional two-terminal memristor is readily impacted by voltage. In order to simulate and validate the function of the three-terminal memristor, the logic circuit and multiplication circuit are developed using this model in this work using the cadence ic617 program. According to the findings, the three-terminal memristor multiplication circuit uses less energy than the typical conventional multiplier circuit, consuming only 0.335 uW. The memristor offers the benefits of low power consumption, compact size, and great integratability as a nanoscale device. The use of three-terminal memristors can dramatically reduce the number of chip components and improve chip integration when Moore's law approaches a limit.

A Memristive Cell with Long Retention Time in 65 nm CMOS Technology

Abstract: The memristor, which Leon Chua discovered in 1971 and Hewlett Packard fabricated for the first time in 2008, is still facing many design and fabrication challenges. Luckily, memristor emulators using mature Complementary Metal Oxide Semiconductor (CMOS) processes are good substitutes for memristors in several applications. The common setback for these emulators is their inability to retain their internal states for long periods of time. This article presents a memristive cell that not only has the memristor's characteristics but also can retain its resistance for up to 10 years. To bring forward such a cell, a charge trap in a 1 mm2 chip is designed and fabricated using a standard 65 nm CMOS process. By characterizing the proposed trap prototype, its unexpected yet interesting behavior is revealed, such as charge tunneling that occurrs at voltages between 350 mV and 650 mV despite the process sensitivity. Next, based on the measurement results and using the VerilogAMS programming language, the charge trap to be combined with other circuits that constitute the proposed memristive cell is modeled. This model, which is partly based on previously reported models, matches the measured characteristics of the fabricated charge trap and can be easily integrated into circuit simulations.

A Novel Programming Circuit for Memristors

Abstract: Memristor has attracted a lot of interest due to its high processing speed, low power consumption and high integration ability, which is critical for electronic systems and memory-centric computing. However, the memristor programming circuit and strategy are still inflexible and complex, since the signal generator/collector and stimulate pulse must be carefully matched and designed based on memristor intrinsic characteristics without reconfigurable. Here, a simple and effective circuit only consists a parallel reference-resistor-and-NMOS is designed to program memristor with a more than 99% memristance precision. And the amplitude and width of stimulate pulse are fixed to ±4V and 5ms, respectively. In order to cope with the device variation, such as ±10% tolerance of transition voltage, an optimized programming strategy was proposed and demonstrated great robustness. Additionally, a set of reference resistors and NMOSs have been added to facilitate multi-level memristance operation without requiring any changes to the circuit structure. This program circuit was also employed to program memristor crossbar remains 99% precision. In the end, a memristor-based convolutional neural network which controlled by our optimized programming circuit was used for image recognition, and 89.36% accuracy can be achieved even under 15.8% memristance tolerance. This novel circuit demonstrates a simple and flexible strategy in memristor programming, providing a new way to control memristor crossbar for practical application.

Efficient Training Method for Memristor-based Array Using 1T1M Synapse

Abstract: In this brief, an efficient training method for memristor-based array (crossbar) with one transistor and one memristor (1T1M) synapse is proposed, which enables parallel update of memristor-based arrays trained by stochastic gradient descent within two steps. Voltage ThrEshold Adaptive Memristor (VTEAM) model is utilized to describe memristor characteristics for simulations. On this basis, circuit parameters optimization method compensating the asymmetric and nonlinear weight update is provided for better training results. The effectiveness of proposed training method is evaluated on OR, AND functions and digit recognition task. Simulation results demonstrate the robustness of proposed training method to electrical noise and imperfections of memristors.

A Single Memristorbased TTL NOT logic

Abstract: This article presents a NOT logic gate circuit based on a single memristor, and analyzes it for different biological memristive samples based on extracted resistances. The simple resistorvoltage representation of the memristor in the logic circuit is used to formulate a methodology to tune the parameters of the circuit in accordance with TTL voltage values. The logic circuit consists of two resistors in series with the memristor. The input is connected to one end of the memristor, and the output is drawn across the series connection of the second resistor, and the memristor. The methodology comprises of two steps, where, in the first step, the logic ‘low’ TTLinput voltages are examined, and in the second step, the circuit is evaluated for logic ‘high’ TTLinput voltages. The methodology reveals that there is a mínimum voltage value of ‘high’ TTL-input beyond which the output does not fall within the logic ‘low’ TTL-output. The proposed technique may be extended to evaluate novel memristive materials for single memristor-based NOT logic.

Comparative Evaluation of Memristor-based Compact 4T2M SRAM with Different Memristor Models

Abstract: Static Random Access Memory (SRAM) is volatile and uses latching flip-flops to store each bit. To make SRAM work as non-volatile memory (NVM), memristor-based SRAM is a feasible choice mainly due to its high-speed operation and low power consumption. In this paper, the operational characteristics of 4T2M SRAM have been studied based on three different memristor models developed by Biolek et al. (2009), Joglekar and Wolf 2009 Joglekar, Y. N., & Wolf, S. J. (2009). The elusive memristor: Properties of basic electrical circuits. European Journal of Physics, 30(4), 661–675. https://doi.org/10.1088/0143-0807/30/4/001[Crossref], [Web of Science ®] , [Google Scholar], and Prodromakis et al. (2011 Prodromakis, T., Peh, B. P., Papavassiliou, C., & Toumazou, C. (2011). A versatile memristor model with nonlinear dopant kinetics. IEEE Transactions on Electron Devices, 58(9), 3099–3105. https://doi.org/10.1109/TED.2011.2158004[Crossref], [Web of Science ®] , [Google Scholar]), and comparative performance analysis has been made to assess its adaption to NVM. These three different models are compared in terms of delay, power consumption, and static noise margin. From the simulation, it has been observed that Biolek 4T2M SRAM produces better performance in write delay calculation scoring 0.873 ns when ‘0’ is written and 0.166 ns when ‘1’ is written. This model also provided a low power consumption value compared to other models. However, ternary plot analysis finds that Prodromakis is performing in average better in all positive traits. All the simulations are done in LTSpice and the transistor uses TSMC 180 nm CMOS technology.

Linear conductance update improvement of CMOS-compatible second-order memristors for fast and energy-efficient training of a neural network using a memristor crossbar array.

Abstract: Memristors are two-terminal memory devices that can change the conductance state and store analog values. Thanks to their simple structure, suitability for high-density integration, and non-volatile characteristics, memristors have been intensively studied as synapses in artificial neural network systems. Memristive synapses in neural networks have theoretically better energy efficiency compared with conventional von Neumann computing processors. However, memristor crossbar array-based neural networks usually suffer from low accuracy because of the non-ideal factors of memristors such as non-linearity and asymmetry, which prevent weights from being programmed to their targeted values. In this article, the improvement in linearity and symmetry of pulse update of a fully CMOS-compatible HfO2-based memristor is discussed, by using a second-order memristor effect with a heating pulse and a voltage divider composed of a series resistor and two diodes. We also demonstrate that the improved device characteristics enable energy-efficient and fast training of a memristor crossbar array-based neural network with high accuracy through a realistic model-based simulation. By improving the memristor device's linearity and symmetry, our results open up the possibility of a trainable memristor crossbar array-based neural network system that possesses great energy efficiency, high area efficiency, and high accuracy at the same time.

A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects

Abstract: We present an integrated circuit fabricated in a process co-integrating CMOS and hafnium-oxide memristor technology, which provides a prototyping platform for projects involving memristors. Our circuit includes the periphery circuitry for using memristors within digital circuits, as well as an analog mode with direct access to memris-tors. The platform allows optimizing the conditions for reading and writing memristors, as well as developing and testing innovative memristor-based neuromorphic concepts.

Application of Metal Oxide Memristor Models in Logic Gates

Abstract: Memristors, as new electronic elements, have been under rigorous study in recent years, owing to their good memory and switching properties, low power consumption, nano-dimensions and a good compatibility to present integrated circuits, related to their promising applications in electronic circuits and chips. The main purpose of this paper is the application and analysis of the operations of metal–oxide memristors in logic gates and complex schemes, using several standard and modified memristor models and a comparison between their behavior in LTSPICE at a hard-switching, paying attention to their fast operation and switching properties. Several basic logic gates—OR, AND, NOR, NAND, XOR, based on memristors and CMOS transistors are considered. The logic schemes based on memristors are applicable in electronic circuits with artificial intelligence. They are analyzed in LTSPICE for pulse signals and a hard-switching functioning of the memristors. The analyses confirm the proper, fast operation and good switching properties of the considered modified memristor models in logical circuits, compared to several standard models. The modified models are compared to several classical models, according to some significant criteria such as operating frequency, simulation time, accuracy, complexity and switching properties. Based on the basic memristor logic gates, a more complex logic scheme is analyzed.

3T2M bidirectional memristor change circuit

Abstract: In most memristor circuits, a dual voltage is used to adjust the memristor value. This paper proposes a memristor change circuit in which only positive voltage changes the memristor value. A bidirectional change circuit of memristor resistance value composed of three transistors and two memristors is proposed, and a mathematical calculation method for approximate analysis of memristor changes is used. The dual synapse function can be realized by using the circuit and can be directly controlled by digital logic signals, which greatly reduces the number of devices and provides convenience for the integration of neural synapses.

A Memristive Based Design of a Core Digital Circuit for Elliptic Curve Cryptography

Abstract: The new emerging non-volatile memory (NVM) devices known as memristors could be the promising candidate for future digital architecture, owing to their nanoscale size and its ability to integrate with the existing CMOS technology. The device has involved in various applications from memory design to analog and digital circuit design. In this paper, a combination of memristor devices and CMOS transistors is working together to form a hybrid CMOS-memristor circuit for XAX- Module, a core element used as digital circuit for elliptic curve cryptography. The proposed design was implemented using Pt/TaOx/Ta memristor device and simulated in Cadence Virtuoso. The simulation results demonstrate the design functionality. The proposed module appears to be efficient in terms of layout area, delay and power consumption since the design utilizes the hybrid CMOS/memristor gates.

Highly Accurate Memristor Modelling Using Mos Transistor for Analog Applications

Abstract: Abstract Memristor technology has grown at a breakneck pace over the last decade, with the promise to transform data processing and storage. A memristor is a non-linear electrical component with two terminals that connects electric charge and magnetic flux. The ability to store and process data in the same physical location is a fundamental benefit of memristors over traditional electrical components. It has a unique feature in that its resistance may be preset (resistor function) and then saved (memory function). Memristors, unlike other types of memory used in modern electronics, are stable and retain their state even if the device is turned off. In this work, a new highly accurate asymmetrical memristor is proposed for highly efficient analog applications. The proposed work used 5 Complementary metal-oxide-semiconductor (CMOS) devices in a parallel and series-connected manner. A bypass transistor is used to control the current flow between two terminals to perform a stable operation. A differential amplifier circuit is used to validate the proposed memristor performance. The proposed work is implemented using TSMC 45nm CMOS technology. This application consumes less power and has good performance when compared with conventional techniques. In this work, a 1V power supply occupies a 67.5 µm2 layout area. The experimental results are improved when compared with the existing circuit.

Realization of combinational logic circuit based on three terminal memristor

Abstract: A three-terminal memristor model is developed in order to improve the anti-interference performance of the memristor and address the issue that the resistance value of the conventional two-terminal memristor is readily impacted by voltage. In order to simulate and validate the function of the three-terminal memristor, the logic circuit and multiplication circuit are developed using this model in this work using the cadence ic617 program. According to the findings, the three-terminal memristor multiplication circuit uses less energy than the typical conventional multiplier circuit, consuming only 0.335 uW. The memristor offers the benefits of low power consumption, compact size, and great integratability as a nanoscale device.

Tri-State Memristors Based on Composable Discrete Devices

Abstract: We develop a tri-state memristive system based on composable binarized memristors, from both a dynamical systems construction to the development of in-house fabricated devices. Firstly, based on the SPICE model of the binary memristor, the series and parallel circuits of binary memristors are designed, and the characteristics of each circuit are analyzed in detail. Secondly, through the analysis of the connection direction and parameters of the two binary memristors, an effective method to construct a tri-state memristor is proposed, and verified using SPICE simulations. Finally, the characteristics of the constructed equivalent tri-state memristor are analyzed, and it is concluded that the amplitude, frequency and type of the input signal can affect the characteristics of the equivalent tri-state memristor. Predictions from this modeling were validated experimentally using Au/[Formula: see text]/Nb cross-point devices.

Design of General Flux-Controlled and Charge-Controlled Memristor Emulators Based on Hyperbolic Functions

Abstract: In this article, a general memristor model emulator based on the hyperbolic function is proposed. Based on the mathematical model of hyperbolic function memristor, a general circuit model emulator is designed. The general circuit can realize memristor models of different hyperbolic functions by controlling the state of switches in the circuit. The advantage of the emulator is that it can realize three different mathematical models of hyperbolic function and be easily integrated. The circuit of the hyperbolic function memristor model conforms to three basic characteristics of the mem-element, so it can be regarded as a memristor element. Finally, the model of charge-controlled memristor based on hyperbolic function is derived. The universal memristor model proposed in this article enriches the research of constructing memristor components with existing components and provides a reference for future research on mem-element emulators.

Power and Area Efficient Hybrid Memristor-CMOS based 2’s Complement FSM for High-Performance Computing System

Abstract: The fourth fundamental circuit component that is frequently employed to design nanoscale electronic devices is memristor. The compact size, non-volatility, and low power of memristor, combined with their integration suitability with conventional CMOS circuitry, has become a significant advantage in the design of the forthcoming generation of chips. 2’s complement representation is one of the signed binary number representations that every computer utilizes to perform signed arithmetic operations due to its simplicity and effectiveness. Therefore, 2’s complement circuit is a part of the high-performance arithmetic unit of a computer system. This paper presents power and area-efficient design for memristor-based 2’s complement FSM. The proposed circuit is designed in Cadence Virtuoso EDA toolset and simulations have been done using Spectre simulator on 180nm CMOS technology at 1.8V power supply. A comparative analysis of the proposed design and conventional CMOS-based design is given in the paper in terms of power consumption and transistor count. The comparison findings demonstrate 50% area savings while power savings of 18.15 %are obtained. The proposed circuit has a simple structure and requires 14 transistors and 8 memristors for its implementation.

Poor Man’s Memristor: Chua Corsage Memristor

Abstract: Chua Corsage Memristor (CCM) can accurately emulate the neuromorphic behaviors of biological neurons. Recently, we built a working CCM circuit board using only inexpensive and off-the-shelf electronic components. When this poor-mans memristor is connected to a linear passive L and C circuit, the resulting circuit can generate action potentials and chaos. This paper presents the complete theory for deriving the electronic circuit realization of the poor-mans memristor, and also displays more additional neuromorphic waveforms, measured experimentally from the poor-mans memristor, further verifying the neuromorphic dynamics of the CCM.

GEM: A Generalized Memristor Device Modeling Framework Based on Neural Network for Transient Circuit Simulation

Abstract: Conventional physics-based memristor device modeling methods highly rely on human expertise, which results in a long development period. To address the aforementioned challenges, we propose a new generalized memristor (GEM) device modeling framework based on the artificial neural network (ANN) technique, which has a minimum dependency on the underlying physics, resulting in a fast turn-around development time for customized memristor devices. GEM framework models the switching and conducting behaviors of the memristor devices separately, avoiding the signal-dependence issue in the prior time-series data modeling method. The result of the GEM framework is a compact model that supports general-purpose circuit simulators. Experimental results show that our compact model achieves a ratio of root-mean-square error to peak-to-peak (RMSE/PP) of 3.6% compared to the physics-based device model. Performance analysis of memristor-based logic and memristor crossbar circuits are conducted to demonstrate the effectiveness of our proposed GEM framework for the design and analysis of memristor-based circuits.

Review on Different Emulator memristor modelling and application

Abstract: This study presents an overview of operational transconductance amplifiers and memristor emulator circuits. In this work, many kinds of emulator circuits are investigated. Frequency and current-voltage characteristics are investigated with respect to emulation circuits. A solid-state circuit that can simulate the behaviour of a memristor. We provide the groundwork for a compact CMOS circuit that, by simulating an idealised memristor’s properties, might help close the gap between theoretical considerations and practical implementation on a chip. This circuit uses a commercially available integrated circuit to simulate the operation of a model titanium dioxide memristor. An easy-to-implement CMOS memristor emulator that makes advantage of the technology’s dynamic threshold feature. Capacitors are not required for use with this proposal. These proposals for circuits based on grounded memristor emulators have minimal static power consumption. The majority of the CMOS memristor emulator circuit is made up of a variable resistor with two terminals. The voltage that is put across these terminals determines the resistance of the variable resistor. A capacitor is responsible for controlling the value of a resistor and storing the “status” of a memristor. Resistive memristors, ferroelectric memristors, polymeric memristors, resonant-tunneling diode memristors, manganite memristors, and spintronic memristors are some of the most prevalent kinds of memristors that are used today. However, there are many more forms of memristors that are also in use. This study includes a review of memristor materials characteristics, switching processes, and prospective applications, as well as a performance comparison between several memristor emulators and a suggested memristor emulator, with the goal of assisting researchers in understanding the physical principles of the memristor and so providing a hopeful future for memristor devices. Additionally, this paper presents a memristor emulator that has been presented. Machine learning, Non-von Neumann computing, chaotic circuits, neuromorphic computing, and machine learning circuits are all areas where the memristor emulator circuit might be useful. It can be built and fabricated using typical commercial CMOS technology. The frequency range of the proposed memristor emulator has been proved to be retained for grounded setups by use of simulations of cadence. Complementary metal-oxide semiconductor (CMOS) environment using TSMC 45nm technology parameter.