Showing papers on "Memory controller published in 1990"

Embedded commericals within a television receiver using an integrated electronic billboard

Abstract: A television receiver is equipped with a graphics generator which is capable of generating a single or multiple graphic images from data representing commercial advertisements stored in a memory device. The elements of this arrangement include a micro-controller, a memory device, a graphics and memory controller, a pallet controller and a video switch. The images corresponding to the commercial advertisements are displayed to the consumer when a control function of the television receiver is activated. Alternatively, the images may be displayed in response to an internal clock. The images presented may be static or animated and may occupy a small portion of the screen or the full screen.

Dram on-chip error correction/detection

Abstract: Error detection or correction is provided on the same chip as DRAM memory. Because data and error correction bits need not travel on an external bus, error detection/correction can be conducted on a larger number of bits than the width of the data bus. When using memories which provide for access to a row of memory, such as static-column or fast-page mode memories, error correction is conducted on an entire row of memory during one error correction cycle. Following operations of the correction cycle, the data within a row of memory can be accessed independently of the EC circuitry.

The cache DRAM architecture: a DRAM with an on-chip cache memory

Abstract: A DRAM (dynamic RAM) with an on-chip cache, called the cache DRAM, has been proposed and fabricated. It is a hierarchical RAM containing a 1-Mb DRAM for the main memory and an 8-kb SRAM (static RAM) for cache memory. It uses a 1.2- mu m CMOS technology. Suitable for no-wait-state memory access in low-end workstations and personal computers, the chip also serves high-end systems as a secondary cache scheme. It is shown how the cache DRAM bridges the gap in speed between high-performance microprocessor units and existing DRAMs. The cache DRAM concept is explained, and its architecture is presented. The error checking and correction scheme used to improve the cache DRAM's reliability is described. Performance results for an experimental device are reported. >

Programmable controller communication interface module which is configurable by a removable memory cartridge

Abstract: A module interfaces a programmable controller to several serial communication networks over which data may be exchanged according to different protocols. A module has a central controller and a separate port circuit for each of the networks. Each port circuit includes a microprocessor and a shared memory to which both the central controller and the port microprocessor have access for the exchange of data. The central controller transfers data from the shared memories to a module output coupled to other components of the programmable controller. A removable memory cartridge stores a plurality of programs for execution by the port microprocessors to exchange data over the networks using different communication protocols. Configuration data is stored in the module defining which program is to be transferred from the memory cartridge into the shared memory of each port circuit. Protocol parameter configuration inquiries are stored for each program so that the user can be queried to select values for the parameters of the communication protocol used by the program.

Combined synchronous and asynchronous memory controller

Abstract: A memory controller (48) of a personal computer has an asynchronous portion and a synchronous portion. The synchronous portion is used wher the system processor (20) is accessing the memory, while the asynchronous portion is used when control of the memories is held by a DMA controller (48) or a bus master (34) located on a standardised bus (44).

Data cache management system with test mode using index registers and CAS disable and posted write disable

Abstract: A memory controller which can be used with an external tag RAM is disclosed. Existing index registers in the controller serve double duty as buffers for storing tag RAM data during a test mode. Input/output lines for the external tag RAM are coupled to the index registers in addition to being coupled to a comparator for comparison with an external address during normal operation. A buffer is provided so that data from the external address from the CPU can be written through these same tag RAM input/output lines in order to update the tag RAM after a miss. In order to prevent DRAMS from putting data on the memory bus during a cache RAM test, a CAS inhibit signal is provided to the DRAM state machine. Posted writes are also disabled to avoid interference with the address provided to the tag RAM.

Method and apparatus for a backup power controller for volatile random access memory

Abstract: A method and apparatus for a software actuable backup power controller for selectively controlling power to a volatile random access cache memory. If memory does not contain any data that needs to be retained during a primary power failure the controller isolates memory from the backup power supply during the power failure. Only when the memory contains data to be retained during a power failure will memory be treated as non-volatile and is the backup power supply connected to memory on primary power failure. By selectively enabling the backup power supply with software commands from the computer, a suitable cache memory can be constructed with a compact non-rechargeable battery.

Single in-line DRAM memory module including a memory controller and cross bar switches

Abstract: A data processing system includes a processor coupled to a system bus. A memory controller is also coupled to the system bus and to a memory bus in communication with a plurality of single in-line memory modules (SIMMs). Each SIMM comprises a plurality of DRAMS coupled to four cross bar switches (CBSs), such that address and data information is provided to the DRAMs through the cross bar switches. Each CBS includes a counter and decoder which controls a multiplexor. The multiplexor is coupled to enable ID logic, and four input registers (AR, BR, CR, DR), such that register AR is coupled to the output of the multiplexor, and the remaining registers are coupled to the input side of the multiplexor. An input buffer on the CBS is coupled to four input registers (A'W, B'W, C'W, DW). In addition, three of the input registers (A'W, B'W, C'W) are coupled to intermediate input registers AW, BW and CW. During each refresh cycle of the DRAMs on the SIMM, enable ID logic provides a unique 2-bit ID value to the memory controller, thereby forming an ID byte. (The sum of all ID bits from each CBS.) The ID byte identifies the manufacturer of the DRAMs, their size and speed.

Solid state memory array using address block bit substitution to compensate for non-functional storage cells

Abstract: A solid state memory array includes an address bus and a bidirectional data bus and a plurality of partly defective VLSI memory array chips each containing at least one megabit of data storage capacity, having defective memory cell locations, being connected to the address bus, and providing plural data storage bit positions. Each memory array chip has a bidirectional tri-state driver connected between the bit lines thereof and corresponding ones of the data bus. At least one VLSI substitution memory chip contains at least one megabyte of data storage capacity, is connected to the address bus and provides plural data storage bit positions. A substitution chip tri-state driver is connected between the bit lines of the substitution memory chip and all of the parallel data bit lines of the data bus. A programmable read only memory is connected to be addressed by the address bus and is programmed for putting out a binary coded value which has been coded to identify each said defective memory cell location of each one of the memory array chips. A decoder is connected to receive and decode the binary coded value into tri-state driver control values and applies the values to the substitution chip tri-state driver and to one of the memory array chip bidirectional tri-state drivers so as to disable the memory array chip associated with the particular chip driver when a defective memory cell location thereof is addressed, and to enable the substitution memory chip at the particular location and connect it to the data bus in place of the associated memory array chip.

Efficient memory controller with an independent clock

Abstract: A means and a method of interfacing a memory controller with a high speed synchronous CPU wherein the CPU clock is independent of the memory controller clock. The CPU clock is connected to both the CPU and a control interface state tracker located externally to the memory controller. The control interface state tracker is then connected to the memory controller. A separate clock independent from the one used with the CPU is coupled to the memory controller and drives the operation of the memory controller. During the operation of the computer system, the CPU makes read or write cycle requests of the memory controller. Such cycles are initiated when the CPU sends a cycle "start" indicator to the state tracker. In response, the state tracker activates a start strobe to the memory controller to start the actual memory cycle. The memory controller receives the CPU address and cycle status and determines the page hit/miss condition of the memory access. Using this information, the appropriate register in the cycle length register file is accessed to obtain a cycle length feedback value indicating the quantity of wait states necessary for the particular memory cycle. This cycle length feedback value is sent to the external control interface state tracker. The state tracker then returns a ready indication to the CPU after the cycle length time has been satisfied as indicated by the cycle length feedback.

Integrated circuit microcontroller with on-chip memory and external bus interface and programmable mechanism for securing the contents of on-chip memory

Abstract: A data processor with memory within a single integrated circuit package provides a programmable "secure mode" of operation to selectively restrict access and protect information stored in its memory. The secure mode of operation is included in addition to a "single chip mode" wherein the data processor accesses both data and instructions strictly from within the single integrated circuit package. An "expanded mode" of operation also exists wherein the data processor may access either internal or external memory for both instructions and data. The secure mode of operation restricts accesses of instructions to memory contained within the single integrated circuit while allowing data accesses to memory either internal or external to the integrated circuit. The secure mode is accomplished by selectively isolating internal data/instruction bus transfer activity from an external data/instruction bus.

Multi-mode DRAM controller

Abstract: The present invention provides a novel multi-mode DRAM controller adaptd to access DRAM chips of a main storage unit of different size and of different mode types. The novel DRAM controller comprises new address generation and control logic for delaying the RAS and CAS control signals to memory and for expanding the number of address bits employed to address memory chips having a greater number of addresses by at least one address bit.

Electrical waveform generator means and methods

Abstract: An electrical waveform generator and a method for electrical waveform generation are provided which includes a central processing unit (13) to first provide sequential points of a selectable waveform in digital form and store them in digital memory (15). A memory controller (14) then generates the waveform by sequencing those points through a digital to analog converter (17). Previous instruments required large memory capacity to handle all of the data points necessary to produce a wide variety of waveforms. The present invention uses mathematical notation to define and store selectable waveforms and calculates the data points when a curve is selected or defined for use. Memory controller (14) uses concatenated looping during the sequencing of points to the converter (17) for the purpose of making the data memory (15) more efficient. The single waveform generator of the present invention may be used in many of the various applications of waveform generators including automated test equipment having industry standard communication buses for control.

Method for shortening memory fetch time relative to memory store time and controlling recovery in a DRAM

Abstract: A method for reducing fetch time in a computer system provides a memory fetch cycle that is shorter than the memory store cycle. Each chip of the computer system has at least one dynamic random access memory array (DRAM) and a small high speed cache static random access memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and recovery in the DRAM. The RAS starts DRAM recovery for a fetch cycle at or near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that control DRAM recovery while fetching during DRAM data from the SRAMs, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.

Spare memory arrangement

Abstract: A spare memory arrangement in which a defective chip in a memory array can be electronically replaced with a spare chip of identical construction. A defective memory chip is first detected and located by a suitable means, such as an error correction code (ECC), check sum, or parity check. A sparer chip is constructed to be actuated upon a read to the defective memory chip to replace the defective chip with a memory spare chip. The sparer chip includes a cross-point memory (CPM) cell having an address register for receiving data from a central processing unit (CPU) and routing the data to and from the spare memory chip. The cross-point memory (CPM) cell is actuated by control input from the (CPU).

Programmable electronic device

Abstract: The programmable electronic device, such as a radio, includes a memory for storing program information. A controller, such as a microprocessor, is connected to the memory for programming and reading the memory. A keypad is provided for data entry and is connected to the microprocessor. A magnetic switch, such as a Hall effect switch, is located within the radio and controls the program enable line of the microprocessor. The Hall effect switch is actuated by an externally supplied magnetic field for enabling programming of the memory of the radio.

Memory controller for using reserved DRAM addresses for EMS

Abstract: A memory controller which can map EMS addresses into the DRAM behind video RAM addresses or other reserved areas of memory. A single chip has both a DRAM decoder and an EMS decoder operating in parallel. A DRAM decoder examines received addresses and provides an enable signal to a DRAM timing circuit if the address is within the DRAM range and not for a reserved group of addresses. A separate EMS decoder provides a translated address when a received address is within an EMS window. The EMS decoder also provides an EMS timing signal to the DRAM timing circuit.

The 68040 processor. I. Design and implementation

Abstract: The design of the 68040, a third-generation, full-32-b microprocessor in the Motorola 68000 family, is presented. The 68040 integrates over 1.2 million transistors on one chip and can execute the complete 68020 microprocessor and 68882 floating-point coprocessor instruction sets. Pipelined integer and floating-point execution units that operate concurrently with separate internal memory controllers and an autonomous bus controller contribute to its high performance level. Physical caches of 4 kB each for instruction and data reside on chip. Separate address-translation caches of 64 entries apiece operate in parallel with the instruction and data caches. This arrangement provides complete memory management in a virtual, demand-paged operating system. The design team explains its total approach and the workings of the integer and floating-point units. >

Enhanced locked bus cycle control in a cache memory computer system

Abstract: An enhanced processor lock cycle management system for computer systems including a processor 10 and a cache memory controller 12 which accommodates existing methodologies and provides an enhanced mode wherein processor lock cycles are not passed to the controlled 12 but control of the system bus 14 by controller 12 is maintained by inhibiting hold requests to the controller 12 by other system elements.

Methods and apparatus for maintaining cache integrity whenever a cpu write to rom operation is performed with rom mapped to ram

Abstract: Methods and apparatus for maintaining cache integrity in a computing system that includes a central processing unit (CPU), Random Access Memory (RAM), Read Only Memory (ROM), and a local memory controller for controlling cooperation between said CPU, RAM and ROM, wherein said computing system is capable of supporting a ROM mapped to RAM mode of operation, and further wherein said local memory controller, whenever said ROM mapped to RAM mode is enabled, (1) implements a snoop cycle to detect CPU write ROM operations and, upon detecting such an operation, (2) provides a cache invalidation signal to the CPU. The CPU utilizes the invalidation signal, along with the invalidation address on the local bus coupling the CPU and memory controller, to invalidate any cache data entry corresponding to the main memory address targeted by the CPU write ROM operation. The invalidation takes place while the write operation is in progress.

Data processing system and memory controller for lock semaphore operations

Abstract: A local processor is connected to one port of a dual port memory controller. A bus having a BURST signal line is connected to the other port. The memory controller controls access to a local memory. A remote processor can perform a semaphore operation on a semaphore stored in the local memory by translating a LOCK signal from the remote processor into a bus BURST signal that is activated for a period allowing the remote processor to read and modify the semaphore. While the semaphore operation is being performed, the local processor can access the local memory.

Three port random access memory in a network bridge

Abstract: A network bridge with a three port interface to random access memory is presented. The network bridge includes a system processor, a random access memory, a first memory access controller, a second memory access controller and a three port interface to the random access memory. The random access memory is used to store data packets received by the network bridge from the first network and the second network. The three port interface to the random access memory includes a first port connected to the first memory access controller, a second port connected to the second memory access controller and a third port connected to the system processor. The three port interface allots to the first memory access controller, to the second memory access controller and to the system processor access to the random access memory. The access to the random access memory is allotted so that the first memory access controller, the second memory access controller and the system processor all have equal access priority. The three port interface access cycle is approximately three time as fast as the access cycle of the system processor, the first memory access controller and the second memory access controller. This eliminates the need for local buffers between the memory access controllers and the networks and allows the system processor and the memory access controllers to access the three port interface simultaneously with a minimum of access collisions.

Non-volatile memory usage

Abstract: A page printer including a print engine (15) and a con­troller (11) which includes a non-volatile memory (16) having an EEPROM (17) and a chip RAM (18). A microproces­sor (12) under program control manages the placement of data in the EFPROM (17) of the non-volatile memory (16). The EEPROM (17) and the associated chip RAM (18) are structured to have a control block and a data storage portion. The control block includes pointers indicating the locations in the non-volatile memory where data is stored. If a data location becomes faulty, the value of the pointer to that location is changed so that the point­er points to a previously unused portion of the non-vola­tile memory.

IC chip having volatile memory cells simultaneously loaded with initialization data from uniquely associated non-volatile memory cells via switching transistors

Abstract: Initial data and/or control bits of registers within a digital integrated circuit are simultaneously loaded from localized non-volatile memory cells provided as part of the circuit. Such loading is accomplished each time the circuit is initialized, such as when power is first turned on to a system in which the circuit is a part. An important use of this technique is with a computer peripheral circuit chip such as a serial communications controller.

System having microprocessor local memory expansion capability through removable coupling of local memory expansion boards directly to the high speed microprocessor local bus

Abstract: This invention relates to a personal computer having facility for ready variation in the amount of memory capability available on the microprocessor local bus The personal computer has a microprocessor, a high speed local bus coupled to said microprocessor, a system bus, a bus controller coupled to and providing communication between the local bus and system bus, and a local bus memory facility coupled to and physically separable from the local bus The local bus memory facility is provided by a substrate, preferably a printed circuit card, for mounting and providing coupling connections among components mounted thereon, at least one volatile memory component mounted on the card, and a memory controller mounted on the card and coupled to the volatile memory component, local bus and bus controller, with the memory controller regulating communications between the volatile memory component and microprocessor

Method and apparatus for detecting cursors

Abstract: Apparatus and methods are disclosed which are most advantageously used with a digital computer for detecting the location of multiple cursors in a computer memory having parity bits. In one embodiment of the present invention, the normal parity checking scheme of the computer memory is modified, such that the parity bit is used to detect data locations containing cursor data. Writing new data to the frame buffer is implemented as a read-modified-write cycle. In another embodiment of the present invention, the parity checking of the computer memory is no longer used as such. Instead, the memory controller has a mode that forces the parity bit to one of two states, independent of the contents of the data location. Rather than writing to the frame buffer as a read-modify-write cycle, the memory controller detects the location of the cursor by reading the state of the parity bit while writing the contents of the data location associated with the parity bit. As a result of implementing the present invention, the CPU spends less time manipulating the cursors while maintaining a high frame buffer access bandwidth.

Parallel polygon/pixel rendering engine

Abstract: A parallel polygon/pixel rendering engine for a digital map capable of producing real-time linear shaded, three dimensional, raster graphics for video generation. The apparatus is suitable for use with avionic display systems, particularly digital map displays which include an instruction and interpreter unit and an image scanner. The apparatus comprises a raster engine, a memory interface and a bit mapped memory. The raster engine further includes a raster engine control and generic interpolation polygon processor interface, an edge interpolator, a line interpolator and a controller for the edge and line interpolators. The raster engine control is electrically connected to receive data from the instruction interface unit and is further electrically connected to the edge interpolator and interpolator controller. The edge interpolator is adapted to receive data from the raster engine control and the line interpolator is electrically connected to receive data from the edge interpolator. A first edge pipeline is connected to a second output of the raster engineer control and a second edge pipeline is connected to an output of the first edge pipeline as well as an output of the edge interpolator. An output from the second stage of the edge pipeline and a plurality of outputs from the line interpolators are then fed to a memory interface which is connected to receive data from the plurality of outputs. A bit mapped memory is also connected to receive data from the memory interface and control signals from a bit mapped memory controller. The bit map memory controller controls the memory interface components and the bit map memory during both normal and test modes.

Data processing system including a memory controller for direct or interleave memory accessing

Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.

Flash writing circuit for writing test data in dynamic random access memory (dram) devices

Abstract: A flash writing circuit for testing of dynamic random access memory (DRAM) devices comprises a generally conventional DRAM device and includes additional elements for writing identical data in each memory cell via bit lines connected to the memory cells but without the use of the conventional I/O lines normally used to write data into the memory cells.

Data protected work station computer - requires special software for access and monitors system to detect unauthorised manipulation

Abstract: A security protection system is provided to control access to a computer and ensures that the memory controller can only be accessed with the use of special software. Operations are coded to limit which can be performed without the relevent software. - The secured hardware port is monitored and any damage or attempt to manipulate results in the memory being blocked. The system operates with a host computer and a security computer.