Showing papers on "Memory controller published in 1993"

Secure memory card

Abstract: A secure memory card includes a microprocessor on a single semiconductor chip and one or more non-volatile addressable memory chips. The microprocessor chip and non-volatile memory chips connect in common to an internal card bus for transmitting address, data and control information to such non-volatile memory chips. The microprocessor includes an addressable non-volatile memory for storing information including a number of key values, application specific configuration information and program instruction information. Each chip's memory is organized into a number of blocks or banks and each memory chip is constructed to include security control logic circuits. These circuits include a number of non-volatile and volatile memory devices which are loaded with key and configuration information under the control of the microprocessor only after the microprocessor has determined that the user has successfully performed a predetermined authentication procedure with a host computer. Thereafter, the user is allowed to read out information from blocks only as defined by the configuration information.

Method and apparatus for execution of operations in a flash memory array

Abstract: A flash memory system includes a user interface and array controller The user interface receives the user command issued by the processor and has the ability to queue a plurality of commands for execution The user interface further functions as an arbiter to control the priority of commands to be executed The array controller performs the operations on the flash array such as program and erase The array controller consists of a general purpose processor with program memory which is programmable by the user The program memory stores one or more algorithms that can be executed by the array controller The algorithm is selected according to the command received at the user interface The algorithms can be customized simply by programming the program memory The system further provides an interrupt mechanism which enables the flash memory system to perform a context switch of a higher priority command with the lower priority, but currently executing, command

Serial architecture for memory module control

Abstract: An expandable memory system including a central memory controller and one or more plug-in memory modules, each memory module having an on-board memory module controller coupled in a serial network architecture which forms a memory command link Each memory module controller is serially linked to the central memory controller. The memory system is automatically configured by the central controller, each memory module in the system is assigned a base address, in turn, to define a contiguous memory space without user intervention or the requirement to physically reset switches. The memory system includes the capability to disable and bypass bad memory modules and reassign memory addresses without leaving useable memory unallocated.

Protected programmable memory cartridge having selective access circuitry

Abstract: A computer system for high-performance video and audio manipulations comprising a locked memory cartridge and an audio/video/compact disk (CD) drive controller/coprocessor. The computer system has a central processing unit (CPU) with at least one bus associated therewith, with the bus having at least one bus line. The cartridge comprises a readable memory, a memory control circuit, a lock control circuit, and a connector all in circuit communication with each other. The connector allows the memory, the memory control circuit, and the lock control circuit to be pluggably connected in circuit communication with the CPU. The memory control circuit scrambles some of the bus lines, thereby scrambling the data in the memory on reset, and unscrambles the bus lines responsive to inputs from the lock control circuit. The lock control circuit monitors the bus, waiting for a proper combination of bus values to be asserted onto the bus, at which time the lock control circuit causes the memory control circuit to unscramble the bus lines. The audio/video/CD drive controller/coprocessor comprises a CPU interface, a CPU cache, a memory controller, a memory bus arbitrator, a DRAM refresher, a video controller, a CD drive controller, a digital signal processor (DSP) sound coprocessor, and a "blitter" graphics coprocessor in an integrated package.

Buffer memory data flow controller

Abstract: A data flow control system for regulating the flow of data through a buffer memory in a data storage system controller. The data flow controller system includes an up-down counter that is decremented for every byte of data that is placed into the controller's buffer memory, and incremented for every byte of data that is taken out of the buffer memory. The counter is preset to an initial value that represents the minimum amount of data that must be in the buffer memory before that data can be released to the storage system or to the computer interface, thereby permitting validation of the data prior to release. The value of the counter represents the amount of data that is in the buffer memory less the initial offset value. Detector circuitry coupled to the counter enables or disables the storage system or the computer interface depending upon the validity of the data in the buffer memory and the operational status of the storage system and the computer interface. An additional feature of the invention permits using the buffer memory as a cache for data read from the storage system. Intermediate status information about the buffer memory is generated in order to permit the storage system controller microprocessor to anticipate operational states, and improve data transfer efficiency. By directly controlling the data flow through the buffer memory, the storage system controller microprocessor is not directly involved in all aspects of data transfers, and therefore it is not required to operate at the higher speeds necessary with present day and future storage systems.

Cache memory support in an integrated memory system

Abstract: A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. Efficient L2 cache memory support is provided based on a system controller having an integrated L2 cache controller and a graphics controller that supports an integrated memory system. The memory connected to the graphics controller may be partitioned into two sections, one for graphics and one for system use. Additionally, the system controller may or may not have attached additional memory for system use. L2 cache support is provided for all system memory, regardless of the controller that it is connected to.

Bus architecture for integrated data and video memory

Abstract: A bus architecture and protocol for integrated data and video memory. A high speed dedicated memory bus is coupled to a memory controller. The memory controller is in turn coupled to a multiple processor bus interconnecting one or more processors. Single in-line memory modules (SIMMs) incorporating dynamic random access memory (DRAM), video RAM (VRAM), and static nonvolatile RAM (SRAM) are coupled to the memory bus. Bus control signals forming a bus protocol, and address and data lines from the memory controller are shared by all memory modules operating on the memory bus. Certain control signals invoke specific operations on memory modules or are ignored, depending on the type of memory module receiving the control signal. The memory modules incorporate the consistent protocol by virtue of a consistent control signal pin out. The SIMMs further incorporate buffering and conversion functions, thereby relieving the memory controller of service overhead associated with these functions. Integrating all forms of memory into a single data and video memory architecture permits a highly functional dedicated memory bus to be connected to the computer system.

Shared-buffer-type ATM switch having copy function and copy method thereof

Abstract: In a shared-buffer-type ATM switch including a multiplexer, a shared buffer memory, a demultiplexer, a buffer memory controller, a cell copy section is disposed between the multiplexer and the memory. The copy section produces a plurality of copies of a broadcast cell according to information of a copy information table and adds associate routing information to each copied cell so as to write the cells in the memory. In response to an indication from an output counter, the cells are read from the memory to be distributed to output ports, thereby implementing a broadcast function.

Method and apparatus for refreshing a selected portion of a dynamic random access memory

Abstract: A system for refreshing selected portions of a dynamic access memory (DRAM) subsystem of a computer A memory controller of the present invention includes a RAM device for storing a plurality of region descriptors used to inhibit the refresh of address ranges of the DRAM that do not contain valid data, thereby conserving energy required to refresh the entire DRAM The controller includes logic circuitry connected between a refresh period timer and the RAM device for inhibiting receipt by a RAS generator of a refresh pulse when a generated refresh address falls within the refresh address range defined by the region descriptor A refresh address output by a refresh address counter compared to the region descriptors in the RAM device, and if the region descriptors indicate that the row addressed by the refresh address does not contain valid data, the RAS generator is inhibited from producing a RAS pulse Logic instructions are inserted into memory allocation and memory deallocation subroutines of the computer's operating system for writing the region descriptors to the RAM device

Disk drive controller with a posted write cache memory

Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface. A posted write memory system is connected as a selectable disk drive to the disk interface. The posted write memory system includes mirrored, parity checked and battery backed semiconductor memory to allow posted write data to be retained during power down conditions with only a very small change of data loss.

Method for determining speeds of memory modules

Abstract: A microcomputer system with a data destination facility provides for accessing dynamic RAMs of different speeds faster or slower depending on the dynamic RAM speed. When the data destination facility maps the dynamic rams, it also saves a bit indicating whether the block of RAM is a high or low speed RAM. When the memory controller attempts to access a certain location, the data destination facility then returns the value of the speed bit associated with that block of memory to the memory controller state machine, which then omits or adds clock cycles to the memory access depending upon the speed of the memory. Further, in setting up the data destination facility, the system initialization routine determines SIMM sizes by first touching the memory locations at which the SIMMs are occupied to determine if there is memory there, and then determines the SIMM speeds based on a combination of the SIMM sizes and the SIMM identification codes returned through a standard serial shift register.

Integrated memory cube structure

Abstract: An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N×M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.

Random access memory power management system

Abstract: Method and apparatus for power management of a RAM subsystem of a computer. Blocks of data stored at various addresses throughout the RAM subsystem are packed into unallocated memory space at the lowest possible physical location within the RAM subsystem and then are compressed. The packed and compressed data is then copied into the minimum number of RAM devices comprising the subsystem needed to store such data. The remaining RAM devices are either deenergized, if they comprise static RAM, or not refreshed, if they comprise dynamic RAM, thereby reducing the power consumption of the subsystem. Upon a command to return from the reduced power consumption mode, the above steps are executed in the reverse order and the blocks of data are copied to their original memory address locations in said RAM subsystem, using a table that is compiled during the packing step. The invention is implemented by computer program instructions executed in the computer CPU to operate a memory controller connected to the RAM subsystem.

Memory subsystem having a static row memory and a dynamic RAM

Abstract: A computer memory subsystem is comprised of one or more Dynamic Random Access Memory (DRAM) arrays with on-chip sense latches for storing data outputted from the DRAM, an on-chip Static Random Access Memory (SRAM) functioning as a Distributed Cache and an on-chip multiplexor. A first data bus interconnects the sense latches, the SRAM and the multiplexor. A second data bus interconnects the multiplexor and the SRAM. A memory controller generates signals which cause information to be extracted from the DRAM while the contents of the SRAM is unchanged or vice versa.

Processor that performs memory access in parallel with cache access

Abstract: A computer system includes an accessible memory controller, an accessible cache controller, and circuitry for accessing the accessible memory controller and the accessible cache controller simultaneously. Certain preferred embodiments of the present invention also include a deassertable miss line, that is, a line which when deasserted indicates that the data was found in the cache and that the memory access should be cancelled.

Selectable interface between memory controller and memory simms

Abstract: A computer system is provided which includes a CPU having a memory controller interconnecting the CPU to a bus. The bus has card receptacles having pin receiving sockets electrically connected to the bus to receive the pins of memory cards. The memory controller is connected to logic which will identify the type of memory card which is inserted in the pin sockets. From this identification combinational logic is provided that, in response to the identification of the type of card, will direct the appropriate signals from the memory controller to the appropriate sockets depending upon which type of card is plugged into the socket. In this way, a given socket configuration can accept different types of memory cards having different pin signal configurations without physical modification of the sockets.

System using a memory controller controlling an error correction means to detect and correct memory errors when and over a time interval indicated by registers in the memory controller

Abstract: A burst error scrubbing system and method consecutively detects and corrects errors in all of memory, beginning with data stored at the first address of memory and continuing until data stored at the last address of memory is read, corrected and written back to memory. Burst error scrubbing is not performed during a refresh cycle but instead is programmable so that the burst scrubbing can be performed at a specific time interval.

Reconfigurable memory processor

Abstract: A process in memory chip has been designed to combine memory and computation on the same integrated circuit in a way that makes use of the bandwidth that results from the combination. The chip contains multiple single-bit computational processors that are all driven in parallel. Error correction logic is also incorporated into the chip to detect and correct errors in memory, data as they occur.

Method and apparatus for down-loading instructions from a host computer system to a memory in a peripheral controller for execution by a core microprocessor in the peripheral controller

Abstract: A method and apparatus for downloading instructions and other information to a peripheral controller for use in an Industry Standard Architecture (ISA) compatible computer provides a system which downloads instructions from the ISA compatible computer to an random access memory (RAM) accessible by the peripheral controller. The peripheral controller then executes these instructions to emulate the functions of conventional INTEL 8042 and 8742 series integrated circuits. The peripheral controller also provides other features not provided by the conventional 8042 or 8742 by executing other downloaded instructions located in the RAM.

Random access cache memory controller and system

Abstract: A memory cache apparatus compatible with a wide variety of bus transfer types including non-burst and burst transfers. In burst mode, a "demand word first" wrapped around quad fetch order is supported. The cache memory system decouples the main memory subsystem from the host data bus so as to accommodate parallel cache-hit and system memory transfer operations for increased system speed and to hide system memory write-back cycles from the microprocessor. Differences in the speed of the local and system buses are accommodated, and an easy migration path from non-burst mode microprocessor based systems to burst mode microprocessor based systems is provided. Various memory organizations are accommodated including direct-mapped or one-way set associative, two-way set associative, and four-way set associative.

A memory controller with an integrated graphics processor

Abstract: The paper describes the SX graphics accelerator. It is a programmable processor built into a workstation memory system. The goal of the SX is to achieve performance comparable to that of low end 2D and 3D graphics processors and to surpass low end imaging performance, at the lowest possible cost. The SX contains an integer vector processor, with an instruction set tailored to the needs of image processing and multimedia as well as 2D and 3D graphics. It can directly access data in both video and main memory, allowing accelerated processing on images up to 512 Mbyte in size. The SX offers a cost-effective method of providing a rich graphics and image processing capability compared to traditional workstation and accelerator approaches. >

Control for computer windowing display.

Abstract: A windowing control for a video display includes a programmed controller (17), a video display (43) including a screen and a raster for scanning the screen, a first memory (30) having a first area for storing data to be displayed in a first window defined on the screen and a second area for storing data to be displayed in a second window on the screen and a second memory (39) for storing the addresses of the data to be displayed in the first and second windows and the transitions between the windows The controller includes a processor (17) programmed to load data into the first and second memory means and a memory controller (36) for initiating the transfer of data from the first and second memory to a pixel multiplexer (40) The processor (17) is also programmed to load new address data into the second memory means for each complete raster scan so that the position of the data within the window has the appearance of horizontal (panning) or vertical (scrolling) movement

Method and apparatus for performing memory protection operations in a single instruction multiple data system

Abstract: In a multiprocessor system, memory accesses by the individual processing elements are checked by a common controller The controller includes a table of values defining valid memory locations for a task The controller verifies the address value used by each instruction to ensure that, it is within a valid memory area for the particular task Additional circuitry for the controller and processing elements allows finer control, of memory accessibility The multiprocessor system may be coupled to a host computer through a buffer Data is serially written into the buffer by the host and is read out of the buffer in parallel by the multiprocessor system The buffer used in this system includes apparatus which calculates an error correction code from a serial data stream and passes this code, along with the data, to the multiprocessor system The multiprocessor system includes apparatus which processes the data in parallel to handle errors occurring during transfers as indicated by the code

Microprocessor arranged to synchronously access an external memory operating at a slower rate than the microproccessor

Abstract: A microprocessor is provided which executes synchronous accesses to an external memory whether the external memory is operating at the same frequency as the operating frequency of the microprocessor or whether the external memory is operating at a frequency which is one-half the microprocessor operating frequency. The microprocessor includes a rate control input for receiving a rate control signal having a first level indicative of the microprocessor frequency being equal to the external memory frequency or a second level indicative of the microprocessor frequency being twice the external memory frequency. A memory access control is coupled to the rate control input and is responsive to the rate control signal, an internal microprocessor clock, and the external memory clock for causing the microprocessor to access the external memory in synchronism with the external memory clock when the external memory frequency is either equal to the microprocessor frequency or is one-half the microprocessor frequency.

Memory subsystem for bitmap printer data controller

Abstract: A DRAM memory controller for a printer having a single host CPU and a bitmap memory. The CPU initiates data transfers synchronously to a system clock for filling the bitmap memory, and a DMA controller initiates data transfers asynchronously to the system clock for transferring data from the bitmap memory to a print engine. The controller includes a first sequencer for controlling synchronous data transfers initiated by the host CPU, a second sequencer for controlling asynchronous data transfers initiated by the DMA controller, a refresh request generator for generating a refresh request signal which is asynchronous to the system clock, and a third sequencer for controlling memory refresh and for controlling arbtitration betwween the first, second, and third sequencers. Also provided is a method of transferring data between a bitmap memory and a print fifo in a printer. The method includes the steps of initiating a single data write transfer to a location in a dynamic RAM; reading a word of data from the location in the dynamic RAM to a first buffer using a first page-mode DRAM access; and writing data from a second buffer to the same location in the dynamic RAM using a second page-mode DRAM access.

Method for controlling DRAM memory in a microcomputer

Abstract: There is provided a microcomputer including therein a DRAM controller, the DRAM controller including a refresh controller for refreshing a DRAM and an access controller for controlling the access to the DRAM whereby the need of a DRAM controlling external circuit that suffers from severe timing adjustment is eliminated and hence the DRAM is made directly connectable to the microcomputer.

Memory bandwidth optimizations for wide-bus machines

Abstract: The authors describe and evaluate the effectiveness of some code improvement techniques that are designed to take advantage of wide-bus machines (WBMs): that is, a microprocessor with a memory bus width at least twice the size of the integer data type handled by the processor and assumed by the programmer. They discuss some compiler optimizations that take advantage of the increased bandwidth available from a wide bus. The investigations show that WBMs can expect reduction in memory bus cycles on the order of 5 to 15%. Using new code improvement algorithms designed to exploit the availability of a wide bus, the studies show that, for many memory-insensitive algorithms, it is possible to reduce the number of memory loads and stores by 30 to 40%. >

Clock generation and distribution system for a memory controller with a CPU interface for synchronizing the CPU interface with a microprocessor external to the memory controller

Abstract: A clock generation and distribution system for a memory controller in a computer system is described. The memory controller includes a CPU interface circuit-that interfaces with a microprocessor, a bus controller interface circuit that interfaces with a bus controller, and a main memory controller circuit coupled to a memory for controlling memory operations of the memory. The clock generation and distribution system includes a clock generation circuit for generating a first clock signal in accordance with an input clock signal. A delay circuit delays the first clock signal to be a delayed first clock signal. The delay circuit has a controllable delay. An electrical connection circuit external to the memory controller transfers the delayed first clock signal to the (1) the microprocessor, (2) the bus controller, (3) the CPU interface circuit, and (4) the bus controller interface circuit such that the CPU interface circuit is synchronized with the microprocessor and the bus controller interface circuit is synchronized with the bus controller by the delayed first clock signal. The electrical connection circuit generates a signal transfer delay to the delayed first clock signal. The delay circuit controls the controllable delay such that the delayed first clock signal with the signal transfer delay is also synchronized with the input clock signal.

Code segment replacement apparatus and real time signal processor using same

Abstract: A sequence of instructions for a processor executing a plurality of real time programs is supplied from a memory having a set of memory locations. A controller is coupled to the memory for replacing a program with a replacement program. The controller disables writes in response to instructions in the sequence from a particular group of memory locations with idle or no-operation instructions in response to a command. A memory interface is coupled to the memory and to the controller through which new instructions for the replacement program are written to the particular group of locations. The technique is applied especially for audio signal processors with a need for dynamic replacement of active voice programs.

Printed matter inspecting system

Abstract: PURPOSE:To detect a fine print defect while holding an inspecting accuracy by conducting a linear transformation with a gradient of an input image as a rotary parameter and correcting the gradient of the image according to a transformed result. CONSTITUTION:Input image data of a frame memory 104 is sent to a correcting unit 105, a size correcting unit 106 and a printed surface slicing unit 107 by an operation of a CPU 108 and a memory controller 115 through an image bus 110. A gradient of one side of a contour of a set of pixels of stored input image data of the memory 104 is obtained by the unit 105, with this gradient as a rotary parameter a gradient of the image data is corrected by linear transformation such as affine transformation, etc., a screen size from a pixel set is detected, a size of the image data is corrected by the unit 106, and image data in which gradient/size correction are already conducted is sent to an inspection image memory 112. An input image data of the memory 112 is compared with reference image data in a reference image memory 111 at a pixel unit by a difference unit 113, and propriety is decided based on a cumulative value of differences of pixels by a discriminator 114.