Showing papers on "Memory refresh published in 1981"

Signal transfer timing control using stored data relating to operating speeds of memory and processor

Abstract: A memory controlling apparatus retains time information prepared based on performance of a memory and a processor, and determines timing of signal exchange between the memory and the processor based on the time information. An access time to the memory is reduced while maintaining a flexibility to a change of the access time due to increase of memory capacity or reconfiguration of the memory.

A fault-tolerant 30 ns/375 mW 16Kx1 NMOS static RAM

Abstract: A fault-tolerant 30950 mil/SUP 2/ (19.9 mm/SUP 2/) 16K/spl times/1 static MOS RAM has been fabricated with a single polysilicon E/D NMOS process. Using circuit techniques normally restricted to dynamic RAMs, but adapted for asynchronous operation, the device achieves a typical access time of 30 ns while dissipating only 375 mW. Among the topics discussed in a new single-polysilicon memory cell configuration, the first truly asynchronous bootstrap circuit, an active bit-line equilibration and precharge scheme, and a new power-efficient substrate bias generator. Also described is an on-chip redundancy scheme which consumes approximately 2 percent of the total chip area, does not compromise access time and can be programmed using standard test equipment.

Asynchronously equilibrated and pre-charged static ram

Abstract: In a static RAM fully asynchronous active equilibration and pre-charging of the RAM's bit lines (24) provides improved memory access time and lower active power dissipation. Each change in the memory's row (34) address is sensed for developing a clock pulse (50) of a controlled duration. The clock pulse (50) is received by a group of equilibrating transistors (46) and a group of pre-charging transistors (46) which are coupled to the memory's bit lines. When the clock pulse (50) occurs, all the above-mentioned transistors (46) conduct to effect simultaneous equilibration and pre-charging of the bit lines (24).

Memory protection system

Abstract: A memory protection system includes an auxiliary power supply source for maintaining information stored in a random access memory when the main power supply is terminated. When the main power supply voltage level becomes lower than a preselected level, a detection unit develops a control signal for applying a disabling signal to a chip selection terminal included in the random access memory, whereby a load such as a central processor unit connected to the random access memory is electrically disconnected from the random access memory to minimize the power dissipation.

A 100ns 64K dynamic RAM using redundancy techniques

Abstract: A 64K×1 dynamic RAM with 100ns access time, fault-tolerant circuitry, high-speed serial data output and on-chip refresh circuitry, without the use of pin 1 for control, will be reported.

Redundancy scheme for an mos memory

Abstract: An MOS memory has a main array of memory cells (10, 12) and a plurality of spare memory cells (22, 24). Typically, each memory cell is tested for operability by a conventional probe test. A redundancy scheme is provided for substituting spare memory cells for memory cells found to be defective. An on-chip address controller (38-50) responds to the probe test finding a defective cell by permanently storing and rendering continuously available a fully asynchronous electrical indication of the address of the defective cell. The address controller (38-50) compares its stored data with memory cell information received during normal memory operation, and generates a control signal indicative of the receipt of an address which corresponds to a defective cell. A spare cell selector (106, 108) responds to the control signal by electrically accessing a spare memory cell and by prohibiting access of the defective memory cell.

Memory system having an alternate memory

Abstract: A memory system having both a primary memory and an alternate memory. The alternate memory stores data to be substituted for data stored at memory locations in the primary memory that have defective cells. The alternate memory includes a byte memory and a bit memory. The byte memory stores bytes of data that are to replace bytes having multiple bit errors in the primary memory. The bit memory stores bits to replace single bits in any byte in the primary memory that has a single bit error. A mapping memory controls access to the primary memory and the alternate memory. The memory devices in the primary memory have either all row defects or all column defects in order to reduce the size of the mapping memory.

I/O Adapter with direct memory access to I/O control information

Abstract: A data proessing system includes a processor, a memory, a direct memory accessing (DMA) control unit and an input/output adapter. A memory area of a given capacity is reserved in the memory for storing control information transferred between the processor and the adapter. For transfer of the control information, the adapter accesses the control information stored in the memory area through direct memory accessing under control of the DMA control unit while the processor can make access to the control information through a memory read/write command. By storing at the predetermined area of the memory the control information transferred between the processor and the adapter, the quantity of hardware and the number of IC's required for implementing the adapter can be significantly reduced. Conflicting access requests to the main memory area by the processor and adapter are prevented through time-division control of the memory bus.

Memory patching system

Abstract: A memory patching system which transfers permanent-type information in a read-only memory (ROM) to a random access memory (RAM) and modifying contents of the RAM in accordance with patch information in an eraseable programmable ROM is disclosed.

Pause apparatus for a memory controller with interleaved queuing apparatus

Abstract: A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for storing memory requests to be processed. The memory controller further includes control apparatus connected to monitor bus activity. In response to certain bus activity conditions occurring during multiword transfer operations, the control apparatus operates to lengthen the time between successive multiword transfers of data to the bus so as to ensure that new requestors having lower priorities than a memory controller gain access to an available queue notwithstanding the amount of bus delay incurred in transmitting their memory requests.

ROM security circuit

Abstract: A control circuit to disable the operation of a semiconductor microprocessor memory device in the event of an unauthorized attempt to access the memory. A logic circuit generates a control signal in response to receiving a predetermined binary bit pattern of a plurality of chip select signals. The control signal enables the memory device for operation. If the binary bit pattern is not presented, the memory device is disabled for operation.

Non-volatile memory system for intelligent terminals

Abstract: An intelligent terminal comprising a first memory system (bubble memory) for storing data including a plurality of function programs; a second memory system (static RAM) and a processor operatively coupled to the static RAM to execute instructions therefrom at high speeds. A keyboard is used for selecting a function program to be executed and a direct memory access controller is used for transferring data, including a function program which is selected by the keyboard, from the bubble memory to the static RAM to enable the processor to execute the selected function program. A comparator is used for determining the end of a selected function program, and a static scratch pad RAM is used to store changes made in data to be returned to the bubble memory.

Electronic teleprinting apparatus including a removable programmed EPROM

Abstract: A data processing apparatus is provided with a keyboard and a programmable read-only memory, for example of EPROM type, for durably preserving data which define the manner of operation of the apparatus. A programming circuit connected to the apparatus allows a new memory of the same type to be programmed either by automatic recording of data contained in the original EPROM memory, or by data entered by means of the keyboard in order to make available a new read-only memory provided with data modified relative to the data of the original memory.

Semiconductor memory formed of memory modules with redundant memory areas

Abstract: A semiconductor memory has a plurality of modules or boards each with a plurality of memory integrated circuits and redundant memory areas. For receiving of information for replacement circuiting of faulty bit locations in a memory circuit with redundant memory areas, a volatile auxiliary memory is provided in the memory circuit. Each structural unit, which is easily exchangeable in the course of maintenance jobs which encompass a plurality of memory circuits such as a printed circuit board, has associated with it a programmable non-volatile read-only memory for receiving the replacement circuit information for all memory circuits which are combined in the structural unit. The programming of the read-only memory preferably proceeds during testing of the structural unit.

Calculator with constant memory

Abstract: A calculator having constant memory utilizing a classical CMOS metal gate process, a low power microcomputer with on-chip and external constant memory capability. Incorporation of a switched negative voltage and a non-switched negative voltage to the appropriate P (-) wells enables the power hungry clocked logic to be turned off while power is maintained on the internal static RAM, on the digit latches, and on the R-lines which connect to both the internal and external RAM. Thus, semi-non-volatile memory (constant memory) capability may be achieved with a low standby current.

Refresh circuit for dynamic memory of a data processor employing a direct memory access controller

Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a "D-type" latch (24) whose output, in turn, sets the highest priority DMA channel (0) request line (DREQ0), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACK0) indicating the cycle is completed.

HI-CMOSII 4K static RAM

Abstract: This paper will discuss an 18ns/150mW fully static 4096×1b RAM, using double poly HI-CMOSII technology with 2μm gate length.

Electron beam pattern generation system

Abstract: Bit pattern data stored in an external memory unit (8) is read out under the control of a microprocessor (9) for being compressed in a data compressing unit (10) and then stacked in a memory unit (30). At the time when storing data in the memory unit (30), all the stripe data constituting one chip frame are written in a state capable being made high speed sequential access to at the time of the read-out without need of dividing a memory bank into portions for the individual stripes but by continuously using the address space covering the entire memory areas. This is effected by a memory management unit and a memory module management unit provided in the memory unit (30).

An 8Kx8 dynamic RAM with self-refresh

Abstract: The device uses a standard NMOS one-transistor cell and is fabricated with a double polysilicon HMOS technology using polysilicon word lines and folded metal bit lines. Self-refresh is implemented with an on-chip timer, arbiter, and refresh counter. A high-speed arbiter resolves conflicts between refresh cycles and memory accesses. A `ready' output is provided to the processor. A multiplexed bus is provided in the array to carry column addresses and also I/O data paths. Another multiplexed bus is used for data lines between the input buffers, write buffers, secondary sense amplifiers, and output buffers. Redundant rows and columns are used for increased manufacturing yield. Polysilicon fuses are electrically programmed to select redundant elements.

CRT Refresh memory system

Abstract: A logic memory control system for accommodating plural read/write requests to a video terminal display memory is provided without the need for multiplexing common busses shared by the video terminal logic devices accessing the display memory, or for compromising video terminal data transfer rates.

Memory protection circuit for an electronic postage meter

Abstract: An electronic postage meter includes a memory protection circuit. The memory protection circuit prevents the inadvertent writing of spurious data into memory locations in the nonvolatile memory during a power down cycle. The memory protection circuit works in conjection with a WRITE voltage terminal associated with the nonvolatile memory. Means couple a first voltage source providing a predetermined polarity voltage to the WRITE voltage terminal when a predetermined power condition exists such that the nonvolatile memory is enabled to have data written into memory locations. When the predetermined power condition does not exist, the means utilize a second different voltage source to change the voltage level at the WRITE voltage terminal to insure that data is not written into the memory locations.

Digital signal processor with symmetrical transfer characteristic

Abstract: A digital memory is provided which contains digital data words representative of a desired symmetrical transfer characteristic of a digital signal processor. Digital signals which are to be processed are applied to the address inputs of the memory, producing output signals in conformance with the desired transfer characteristic. Advantage is taken of the symmetrical nature of the response characteristic to minimize the size of the memory. Data words corresponding to only a portion of the full dynamic range of the digital signal processor are stored in the memory, and memory locations are addressed and read out in accordance with the value of a polarity-determining bit of the input digital signal, with the output signals being translated over the required full dynamic range in accordance with the value of the polarity-determining bit. In a preferred embodiment of the invention, the memory is a random access memory, with stored data values being altered in response to a user control to change the transfer characteristic of the processor.

Microprogrammed control unit with multiple branch capability

Abstract: A microprogrammed control unit with multiple branch capability comprises in addition to a control memory, a first auxiliary read/write memory (21) having low parallelism and a second auxiliary read/write memory (30) having high parallelism. The reading of a microinstruction from the control memory also causes the reading of an information from the first auxiliary memory, such information being used to address the reading of the second auxiliary memory. The information read out from the second auxiliary memory specifies jump conditions (JC1, JC2, JC3) to be examined and jump addresses (JA1, JA2, JA3) and extends the information contained in the microinstruction read out from control memory. Thus it is possible to associate jump (or branch) microinstructions to operative microinstructions and particularly multiple branch microinstructions to curtail the design time of the microprogram and the control memory size devoted to store them. A priority network 40 coupled to the second auxiliary memory determines the priority to be followed during the concurrent examination of several jump conditions and selects the jump address among several possible addresses according to the highest priority verified jump condition.

Memory with reference voltage generator

Abstract: A reference voltage generator useful in a memory having memory locations capable of storing more than two states provides references which are used to determine which state is stored in a selected memory cell. The output of the reference voltage generator is connected to comparator circuitry which also receives the output from the selected memory cell. The reference voltage generator generates each one of the required voltages every time a row is selected in the memory. The comparator circuitry serves as a sense amplifier and provides a memory output.

Data processing system having interlinked slow and fast memory means

Abstract: A data processing system having a large slow main memory and having a small fast memory is disclosed with means for allowing slow memory calls to fast memory routines and means for allowing returns from programs executing in the fast memory so as to return to program execution in the slow main memory. Also disclosed is circuitry for selectively deactivating the main memory and for selectively activating the fast memory responsive to particular ones of data signals output from the main memory, and means for selectively deactivating the fast memory and for selectively deactivating the main memory responsive to predefined ones of data signals output from the fast memory, thereby allowing program calls embedded in the slow main memory to transfer execution control to the fast memory, and providing retransfer of execution control from the fast memory to the slow main memory in response to a RETURN code embedded in the fast memory. Thus, memory size and speeds may be selectively ratioed to obtain higher overall data processing system throughput.

Parasitic memory expansion for computers

Abstract: A memory expansion circuit for expanding computer memory capacity requiring a minimum of alterations to the host system is disclosed. The memory expansion circuit is parasitic in that it fully exploits address lines, data input and output lines, and control lines already available in the existing host computer system, and it is suitable for use with both static and dynamic memory devices. In a preferred embodiment, a bank of memory devices which responds to a single memory read or write operation in the host computer system is removed, and the parasitic memory circuit containing a number of banks of memory devices is inserted in its place thereby providing a software-selectable number of memory banks to replace the one removed. The method is particularly adaptable for use with contemporary 8-bit microprocessors and especially to systems which are not built around a buss architecture.

Microcomputer with automatic refresh of on-chip dynamic RAM transparent to CPU

Abstract: A microcomputer device is disclosed containing a ROM for program memory, a read/write memory, and a CPU in a single integrated circuit. Input/output ports, interrupt and operating mode controls are memory mapped in the same logical address space as the program and read/write memory. The read/write memory is an array of one-transistor type dynamic storage cells in which data bits are stored in capacitor; refresh of this dynamic RAM is accomplished in a manner transparent to the CPU by an automatically-incremented address counter. Each data bit uses two one-transistor cells in a balanced, complementary array.

Semiconductor IC memory

Abstract: Disclosed is a semiconductor IC memory which has memory cells for storing given data; data lines coupled to the memory cells for transferring data stored in the memory cell; decoders having a sense point and coupled to the memory cells and data lines, for selecting one of the memory cells to couple the selected memory cell with the sense point, the potential of the data line coupled to the selected memory cell being changed with the stored data of selected memory cell; and a sense amplifier coupled to the sense point for sensing the stored data of selected memory cell and providing a read out data corresponding to the sensed stored data. Each of said memory cells has a predetermined threshold level which determines the sense point potential. The predetermined threshold level is selected from four fixed levels. The sense amplifier includes comparators coupled to the sense point for comparing the sense point potential with given comparison levels and providing a comparison result corresponding to the predetermined threshold level; and a selection logic coupled to the comparators and responsive to the logical state of comparison result, for providing an output corresponding to two bits of binary data stored in the selected memory cell and used as the read out data.

Apparatus for the reduction of the short-channel effect in a single-polysilicon, one-device FET dynamic RAM array

Abstract: A one-device, FET dynamic random access memory array is disclosed wherein a problem arising from the short-channel effect is reduced in single-polysilicon, one-device field effect transistor dynamic random access memory arrays where a portion of a word line is used as an electrode of a memory cell storage capacitor. When such word lines are accessed, boosted voltages can appear across the source-drain of FET devices of unaccessed memory cells causing them to conduct and spuriously lose information. This problem is minimized in such memory arrays by opening a pair of bit line switches so that the potential on an unselected bit line remains at the potential to which it was precharged. In this manner, the potential difference across the source-drain of the FETs of unselected memory cells can never exceed the potential to which all the bit lines are precharged.

Pull-up circuit for a memory

Abstract: A pull-up circuit for a memory provides an additional natural transistor between a power supply and diode-connected transistors which reduces the voltage on bit sense lines sufficiently to allow selected column select transistors to turn on prior to a memory cell being enabled. Additional control circuitry further reduces the voltage to the diode-connected transistors when no memory cells have been selected to be enabled to compensate for the reduction in voltage drop across the natural transistor when no current is flowing through it.