Showing papers on "Memory refresh published in 1991"

Method of recording data in memory card having eeprom and memory card system using the same

Abstract: A method of recording data in a memory card having an EEPROM, and a memory card system using the same are provided. A memory card has at least two collective erasure type EEPROM chips where at least one of which is conditioned for a spare memory. When an access of the kind needing overwriting is made to the memory card, data stored in memory locations of the addresses of a corresponding EEPROM chip, except for the address where overwriting is to occur, are copied in the spare memory, and then the EEPROM chip of interest and the spare memory are replaced with each other. The EEPROM chips may be replaced with a plurality of memory blocks or clusters defined in a block erasure type EEPROM.

Method of operating a synchronous memory having a variable data output length

Abstract: The present invention is directed to a method of operating a memory device wherein the memory device includes a plurality of memory cells. The method comprises providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be output onto a bus in response to a read request. The method further includes issuing a first read request to the memory device, wherein in response to the first read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to a first external clock signal and a second external clock signal. In one preferred embodiment, the method may further include providing a code which is representative of a number of clock cycles of the first and second external clock which are to transpire before data is output by the memory device onto the bus. The memory device stores the code in a programmable register on the memory device. In this preferred embodiment, the first amount of data corresponding to the first block size information is output after the number of clock cycles of the first and second external clock transpire. The number of clock cycles may be a whole number or a fraction.

Field-programmable redundancy apparatus for memory arrays

Abstract: A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over standard signal paths of the integrated circuit semiconductor memory array and with standard voltage levels. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundancy apparatus may comprise nonvolatile memory means, such as EEPROM's, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.

Multi-level memory cell with increased read-out margin

Abstract: A dynamic semiconductor memory device for storing a signal corresponding to two bits of digital data in a single memory cell. A memory cell consisting of two transistors and one capacitor is formed. Logic is provided to convert two bits of data to two levels of charge with two different polarities. The result is a memory device which requires only 11/2 elements per bit of storage in contrast to the two elements per bit of storage needed in conventional memory cells.

Floating gate nonvolatile memory with reading while writing capability

Abstract: A floating gate nonvolatile memory. The memory includes a first memory array and a second memory array. A first address register is provided for storing a first address for the first memory array. A second address register is provided for storing a second address for the second memory array. A multiplexer is coupled to the first memory array and the second memory array at one end and an output of the memory device at the other end for selectively coupling one of the first memory array and the second memory array to the output at a time. Array select circuitry responsive to an incoming address is provided for selecting the first memory array for a reprogramming operation and the second memory array for a read operation. The array select circuitry directs the first address to the first address register and the second address to the second address register. The array select circuitry controls the multiplexer for coupling the second memory array to the output during the reprogramming operation of the first memory array.

Disk emulation for a non-volatile semiconductor memory

Abstract: A non-volatile semiconductor memory 34 that is erased in blocks includes an active block for storing first data and a reserve block for storing second data which is a copy of the first data made during a clean-up operation prior to erasure of the active block. The non-volatile semiconductor memory also includes a mapping table for mapping a logical address of an allocation unit to a physical address of a sector within the non-volatile semiconductor memory.

Flash memory circuit and method of operation

Abstract: A memory circuit for storing words of data has two memory banks each formed by a plurality of memory devices connected in parallel. In a first mode, the memory circuit responds to an initial request for access and an address signal by reading data from a storage location in one of the memory banks. Subsequent requests for access to contiguous storage locations do not require an address signal, instead a control mechanism responds by generating an address to read data alternately from storage locations in the first and second memory banks. In a second mode, the memory circuit responds to every request for access to the memory circuit by enabling access to the first or second memory bank as indicated by an address which accompanied the request. The memory devices of a given bank are erased and programmed in parallel. However, when a given storage location is found to contain one or more bits that were not erased, another erase command is sent to only those memory devices associated with a bit that was not erased. Similarly, when a word of data has not been stored properly, only those memory devices which failed to store a bit are placed into the write state for another programming attempt.

Read only memory for storing multi-data

Abstract: A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.

Method and apparatus for substituting spare memory chip for malfunctioning memory chip with scrubbing

Abstract: A computer memory maintainence apparatus tests operating system storage and identifies a malfunctioning memory chip in an on-line memory array by detecting and recording all permanent data errors using data comparison along with data complementation and substitutes a spare memory chip for the malfunctioning one for all memory read commands. All write commands are performed on both spare memory and the malfunctioning memory chip. All contents of defective chip are copied to the spare chip. The computer system maintains the scrubbing and a recording counter for each of the data bits in an ECC memory data word. The sparing logic in the memory storage system maintains the bit steering logic and controls for the spare chip. When a counter is incremented above a threshold sparing is invoked to replace the failing bit position. The system writes to the defective and spare chips in parallel even after bit steering is invoked.

Hidden refresh of a dynamic random access memory

Abstract: A DRAM allows for hidden refresh of its memory cells. The refresh is performed during a refresh segment of the clock cycle. In a preferred embodiment, immediately before the beginning of each clock cycle the DRAM selects a word line for a row of memory cells for which a data access is to be performed. The DRAM also selects at least one word line for at least one row of memory cells for which a refresh is to be performed. During the refresh cycle, a refresh is performed on every memory cell row which is selected for data access or which is selected for refresh. After the refresh cycle, during a data access segment of the clock cycle, the DRAM continues to select the word line for the row of memory cells for which a data access is to be performed; however, the DRAM no longer selects the at least one word line for at the least one row of memory cells selected for refresh. During the data access segment of the clock cycle, the data access is performed on the row of memory cells which remain selected.

Memory controller with integrated delay line circuitry

Abstract: A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of devices is described. The memory controller apparatus interfaces the microprocessor and the plurality of devices. The microprocessor functions asynchronously with the plurality of devices. The memory controller apparatus comprises a delay line circuitry coupled to receive a selected request for accessing the memory array from one of the microprocessor and the plurality of devices, the delay line means further including means for generating a plurality of memory timing control signals. The memory timing control signals are used for accessing the memory array. The delay line circuitry functions independently of any clock signal. The delay line circuitry is only triggered by the selected request. The memory controller apparatus further comprises a memory state circuitry coupled to the delay line circuitry for controlling sequence and timing of the memory timing control signals. The memory state circuitry is clocked by the memory timing control signals. A method of generating memory timing control signals in a memory controller apparatus is also described.

Memory system having two-level security system for enhanced protection against unauthorized access

Abstract: A memory system, having security against unauthorized accessing of the contents of the memory system, comprises a first alterable memory (6), a second non-alterable memory (14, 16) and a data bus (5) for allowing external access to data stored in the memory system during a test mode of operation. The first alterable memory (6) comprises an options register (10) having a security bit (SEC) which, when programmed to an active state, prevents external access to the data stored in the first alterable memory during the test mode. The first alterable memory (6) further comprises a first data memory (8) having at least one security byte (VALSEC) which, when programmed to a predetermined state, prevents external access to the data stored in both the first alterable memory (6) and the second non-alterable memory (14, 16) during the test mode.

First-in first-out semiconductor memory device

Abstract: The number of bits of data items read in parallel fashion and the number of bits of data items written in parallel fashion are related to be at least a whole number multiple of 2, thereby to achieve enhancement in the efficiency of data transfer between a semiconductor memory device and the exterior thereof. Further, in a semiconductor memory device of FIFO type, the number of stored data items is calculated using the values of a write counter and a read counter, thereby to achieve the accurate acquisition of the number of stored data items even when the operations of reading and writing data items coincide. In a semiconductor memory device having a built-in address counter, the value of the address counter or an external address signal is selected on the basis of an external instruction in order to address a memory cell, thereby to achieve facilitation of random accesses to memory cells and also the clearing of the data items of any desired memory cells.

Electronic still camera including an EEPROM memory card and having a continuous shoot mode

Abstract: An electronic still camera using a memory card as a picture recording medium, and a memory card applicable thereto and implemented by an EEPROM (Electrically Erasable Programmable Read Only Memory). A picture signal generated by a CCD array and representative of a picture is routed through an amplifier and an analog-to-digital converter to a signal processing circuit. The picture signal is subjected to interpolation and other similar processing by the signal processing circuit, coded by a compressing circuit, and then written to a buffer memory. These steps proceed on a real time basis. The buffer memory is constituted by a storage device having a reading speed and a writing speed which are different from each other. A memory card controller reads data out of the buffer memory and writes them in the memory card at a low speed matching the memory card.

Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers

Abstract: A dynamic random access memory includes memory cells located at intersections of word lines and differential bit line pairs. A row decoder activates a word line in response to a row address. A first sense amplifier coupled to each bit line pair then increases the small differential voltage of the bit line pair to positive and negative power supply voltages. The first sense amplifier is then isolated from the bit lines so that the bit lines may be equalized. The contents of memory cells along the activated word line are stored in corresponding first sense amplifiers, and the memory functions as a by-one static random access memory during successive page-mode cycles. At the end of the page-mode cycles, the first sense amplifiers are recoupled to the bit lines, and second sense amplifiers update modified data and refresh the charge stored in the memory cells. Performance is improved in at least three ways, including improved write speed, decreased SER by reducing subthreshold leakage, and reduced power consumption.

Single chip microcomputer having unauthorized memory space access protection

Abstract: A single-chip microcomputer connectable to an external memory for expanding the address space, and having a first mode of operation in which the available memory region is both the region of an internal ROM and the external memory, and having a second mode of operation in which the available memory region is the region of the external memory only. An inhibiting device is provided for inhibiting the switching from the second mode to the first mode, thereby ensuring that the contents of the internal ROM cannot be read-out.

Floating gate non-volatile memory with deep power down and write lock-out

Abstract: A non-volatile memory is described. The memory includes a memory array that includes a main block and a boot block. The memory also includes a control input for receiving a control signal. The control signal can be in a first voltage state, a second voltage state, and a third voltage state. Circuitry means is coupled to receive the control signal at the control input for (1) allowing the boot block to be updated when the control signal is in the first state and for (2) generating a power off signal to switch the memory into a substantially powered off state when the control signal is in the third voltage state. A method of controlling a non-volatile memory is also described.

A static memory allocation system

Abstract: A memory allocation system is made up of a unit for storing the information about the memory volume required at the time of initializing an executable program in the control information of the file for storing the program by obtaining the necessary memory volume when the program is translated, assembled or compiled, a unit for reading the information about the memory volume required at the time of initializing the program stored in the control information of the file, when the execution format program is loaded, a unit for statically allocating a memory commensurate with the read memory volume; and a unit for dynamically allocating a memory, when the memory availability is deficient for executing the program.

Refresh control arrangement and a method for refreshing a plurality of random access memory banks in a memory system

Abstract: A memory controller and a method for controlling a memory including at least one memory bank including a plurality of storage locations. The memory controller receives memory access requests over a bus in a digital computer system and, in response initiates a memory access operation in connection with a storage location. The memory controller comprises a memory access control circuit that receives memory access requests over the bus and for performing a memory access operation in connection with a storage location in response thereto. A memory refresh control circuit includes a yellow refresh control circuit and a red refresh control circuit, both of which control refresh of the memory bank(s). The yellow refresh control circuit initiates a refresh operation in connection with a memory bank while the memory access control circuit is performing a memory access operation. In that connection, the yellow refresh control circuit initiates a refresh operation in connection with a memory bank other than the bank with respect to which the memory access control circuit is performing a memory access operation. The red refresh control circuit, on the other hand, initiates a refresh operation in connection with at least one memory bank and concurrently disables said memory access control circuit from performing a memory access operation.

Memory-resource-driven arbitration

Abstract: A method and apparatus to improve memory performance in a computer bus system. Memory is divided into interleaved blocks and memory addresses are mapped into block identification numbers. Master devices keep track of which parts of memory are busy by storing memory block identification numbers in local queues whenever memory is accessed. Block identification numbers are removed from local queues when the memory transaction is complete. Master devices arbitrate for access to the bus for memory transactions only if the target memory block identification number is not in the local queue.

Memory IC testing apparatus with redundancy circuit

Abstract: A testing apparatus for a memory IC with a redundancy circuit includes a first memory, a counter, a second memory and a comparator. The first memory has a memory area for row addresses or column addresses of a target memory with a redundancy circuit, and stores row addresses or column addresses of defective bits of the target memory. The counter counts the number of defective-bit containing rows or columns of the target memory. The second memory stores a number of rows or columns of spare memory cells provided in the redundancy circuit. The comparator compares a count value of the counter with the number stored in the second memory. When the count value of the counter exceeds the number of rows or columns of spare memory cells stored in the second memory, it is considered unrepairable and test is terminated. When the former value does not exceed the latter, memory cells in a defective-bit containing row or column in the target memory are replaced with memory cells in an associated row or column in the redundancy circuit based on the row addresses or column addresses stored in the first memory.

Security circuit for protecting data stored in an internal memory of a microcomputer

Abstract: A security circuit for protecting data stored in an internal memory of a microcomputer has a first memory for storing an externally applied security code and a latch circuit for latching a key code in order to read data stored in the internal memory A comparator determines whether or not the security code in the first memory and the key code in the latch circuit are in agreement and outputs comparison results for storage in a second memory A read control circuit uses the comparison results stored in the second memory as the basis for prohibiting reading of data in the internal memory when the security code and the key code are not in agreement, and for using an externally applied output control signal as the basis to control reading of data stored in the internal memory when there is agreement

Pipelined, time-sharing access technique for an integrated multiport memory

Abstract: A pipelined, time-sharing access (PTA) technique that realizes an integrated multiport memory for high-speed signal processing is described. N/2-port memory cells, with less area and a wider operating margin, are used for the N-port memory function. Memory cell access for multiple ports is performed serially within one cycle, instead of being an ordinary parallel operation. Memory operation is divided into three pipeline cycles-address selection, memory cell access, and data I/O operation-to reduce the cycle time. A 64-kb four-port memory was fabricated with conventional two-port memory cells to verify the effectiveness of this technique. A 16 ns memory operation with a wide margin was observed under a 3 V supply voltage. >

Apparatus for generating test signals

Abstract: An apparatus for generating test signals, preferably for use in an integrated circuit tester, comprises a sequencer, a Vector Memory and a Waveform Memory. The Vector Memory is addressed by the sequencer and contains coded waveform information, which is, in turn, decoded into control information by the Waveform Memory. For this purpose, the data outputs of the Vector Memory control the address inputs of the Waveform Memory. The data outputs of the Waveform Memory control circuitry like a formatter or a comparator which link the waveform information with timing information from one or more edge generators. The formatters, comparators etc. are, in turn, in connection with a device under test. The present apparatus provides full flexibility in the generation of formats and waveforms and, in particular, timing and format changes "on the fly", i.e. without additional delay. Flexibility may be increased if the Waveform Memory is reprogammable.

Data storage control system capable of reading data immediately after powered on

Abstract: A data control system includes an external memory unit for storing data, a volatile memory for storing at-least-once accessed data from the external memory unit, a nonvolatile memory for storing frequently-accessed pieces of data among the data stored in the volatile memory, and a memory control unit for controlling the external memory unit and the nonvolatile memory. The frequently-accessed data is stored in the nonvolatile memory, so that when the system is powered down, the nonvolatile memory does not lose the frequently-accessed data. When the power is on, the frequently-accessed data can be again accessed rapidly.

Programmable memory timing method and apparatus for programmably generating generic and then type specific memory timing signals

Abstract: The present invention operates within a data processing system with multiple DRAM memory modules, providing programmable memory timing through the use of a RAM within the memory controller unit of the data processing system. This RAM, termed the MCRAM, is used to store the timing information for memory operations. In particular, the MCRAM stores for each of the memory operations, Read, Write, and Refresh, the relevant information for RAS, CAS, LD, and AD timing signals. The presently preferred embodiment of the invention contemplates a particular programming process wherein the MCRAM is initially loaded with generic timing information which is acceptable to all possible DRAM memory modules. Following this loading operation, the processor obtains the ID number of the DRAMs within a particular memory module. This ID number is used in a look-up table to obtain the vendor-specific optimal timing for DRAMs corresponding to this ID number. The processor then writes this optimal timing information into the MCRAM. Thereafter, all memory operations to this particular memory module utilize this optimal timing information.

Processing device including a memory circuit and a group of functional units

Abstract: A processing device includes an imitation multiport memory circuit (10) interconnecting inputs and outputs of a group of functional units (F1,...FN), all operating under control of a single series of very long program instructions. The memory circuit (10) comprises a plurality of separate memory units (15), each having a read port (12) connected to a respective functional unit input, and a crossbar switching circuit (18) connected between the functional unit outputs and write ports of the separate memory units. The memory circuit (10) provides substantially the same performance as a true multiport memory but requires a smaller circuit area, allowing a larger processing device to be integrated in one chip than previously. Collisions for access to a memory unit write port can be resolved without rescheduling by use of a delay element (21,70) and/or an additional write port (82) to a memory unit.

Method for data transfer for a semiconductor memory using combined control signals to provide high speed transfer, and semiconductor memory for carrying out the method

Abstract: In a method for data transfer between a plurality of memory cells and at least one input/output terminal of a semiconductor memory, and a semiconductor memory for carrying out the method, a memory cell address is defined by a control signal for a data transfer. A data transfer operation from or to the memory cells is controlled with an address control signal and an output enable control signal for defining a memory cell address with one of the two signals. A data transfer operation is subsequently initiated at a given logical linkage of the two control signals. An ensuing data transfer is controlled with the other of the two control signals.

Memory cell with known state on power up

Abstract: A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read, selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to reading. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation. Selective doping of the pull-up transistors of the inverters in the memory cell controls the initial state of the memory cell after the memory cell is powered up.

Dynamic-type semiconductor memory device operable in test mode and method of testing functions thereof

Abstract: A dynamic-type semiconductor memory device has a test mode of simultaneously carrying out functional testing on a plurality of bits of memory cells. In data writing in the test mode, data inverted from the write-in data is written in at least a 1-bit memory cell out of the plurality of bits of memory cells selected simultaneously, and the same data as the write-in data is written in the remaining memory cells. In data reading in the test mode, the data of those of the memory cells selected simultaneously, in which the inverted data is written are inverted and read, while the data of the remaining memory cells are read as they are. Logic processing is carried out on the read-out data of the plurality of bits, so that a logic value indicating acceptability of the semiconductor memory device is output, depending on a result of determination as to whether or not the read-out data is the same as each other.