Showing papers on "Memory refresh published in 2001"

Non-volatile semiconductor memory

Abstract: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

Digit line architecture for dynamic memory

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

High performance battery backed ram interface

Abstract: A disclosed gaming machine provides a gaming machine with a non-volatile memory storage device and gaming software that allows the dynamic allocation and de-allocation of memory locations in a non-volatile memory. The non-volatile memory storage devices interface to an industry standard peripheral component interface (PCI) bus commonly used in the computer industry allowing communication between a master gaming controller the non-volatile memory. The master gaming controller executes software for a non-volatile memory allocation system that enables the dynamic allocation and de-allocation of non-volatile memory locations. In addition, the non-volatile memory allocation system enables a non-volatile memory file system. With the non-volatile memory file system, critical data stored in the non-volatile memory may be accessed and modified using operating system utilities such as word processors, graphic utilities and compression utilities.

Method and apparatus for supporting heterogeneous memory in computer systems

Abstract: A memory controller capable of supporting heterogeneous memory configurations enables seamless communications between a bus and memory modules having different characteristics. Thus, owners of computer systems need no longer replace entire memory arrays to take advantage of new memory modules; some memory modules may be upgraded to a new type while other memory modules of an older type remain. The memory controller receives memory requests from multiple processors and bus masters, identifies a memory module and memory access parameters for each request, accesses the memory and returns the resulting data (during a read request) or stores the data (during a write request). In some systems, the memory controller of the present invention is a two-tier memory controller system having a first memory controller coupled to the bus and to the second tier of memory controllers or RAM personality modules that translate between the first memory controller and a particular type of memory module. Typically, between the tiers a protocol is used which is representative of a typical clocked synchronous dynamic random access memory (SDRAM), although another protocol could be used. From the perspective of the processor bus or host bus coupled to the front end of the first memory controller, the entire memory controller system behaves as a single memory controller. From the perspective of memory, the back end of the RAM personality module is seen as a memory controller designed specifically to be configured for that memory type. Consequently, although the front end of the RAM personality module can be standardized across the system, compatible with the back end of the first memory controller, and in most embodiments of the present invention, the back end of the RAM personality module differs among the controller modules in the second tier, according to the variety of the memory modules in the memory system.

Apparatus for implementing a buffered daisy-chain connection between a memory controller and memory modules

Abstract: A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and the last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain or in the case of the first and last memor module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-multiplexing so that a lesser number of lines interface with each junction circuit.

Flash memory control method and apparatus processing system therewith

Abstract: A semiconductor file system features a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating correspondence between physical and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information. The controller determines a physical sector address. The control section is for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory.

Memory controller, flash memory system having memory controller and method for controlling flash memory device

Abstract: A memory controller includes decision means responsive to a request to write user data issued by a host computer for determining whether progressive data writing for writing user data to a target page designated by a host address is possible, and write means responsive to an affirmative determination by the decision means for writing user data to the target page without performing an inter-block data transfer. Thus, a series of data write operations for completing data writing can be performed at high speed because the frequency of inter-block data transfers is low.

Method and apparatus for memory self testing

Abstract: A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence of generated memory addresses derived from the self-test instruction to a sequence of re-mapped memory addresses. The programmable re-mapper performs this re-mapping in response to programmable mapping selection data. The re-mapping of the generated memory addresses to re-mapped memory addresses ensures that the memory cell accesses performed during execution of the memory self-test are consistent with the associated memory cell physical access pattern regardless of the particular implementation of the memory array.

Computer system with adaptive memory arbitration scheme

Abstract: A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.

Memory mapping system and method

Abstract: A debug system generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device for used in electronic design automation (EDA). The FPGA device (Behavior Processor) operates to execute in hardware code constructs previously executed in software. When some condition is satisfied (e.g. If . . . then . . . else loop) requiring intervention, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response. A memory block from a logic device is mapped to a memory device in a re-configurable hardware unit using a memory mapping system including a conductive connector driver, a memory block interface, and evaluation logic in each logic device, the connector driver, the interface, and the connector controller, the evaluation logic providing control signals used to evaluate data in the hardware model and to control write/read memory access between the logic device and the memory device via the driver and interface.

Configuration memory integrated circuit

Abstract: A configuration memory for storing information which is in-system programmable. The programming of the configuration memory may be performed using JTAG (IEEE Standard 1149.1) instructions. Furthermore, the configuration of a programmable logic device using the configuration data in the configuration memory may be initiated with a JTAG instruction. Pull-up resistors are incorporated within the configuration memory package.

Technique and apparatus for performing write operations to a phase change material memory device

Abstract: A technique includes, in response to a request to write data to memory cells of a phase change memory device, placing the memory cells in a state that is shared in common among the memory cells. Also, in response to this request, the data is written to the memory cells.

Buffer to multiple memory interface

Abstract: Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least on e buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The at least one buffer allows the memory interface to be split into first and second subinterfaces. The first sub-interface is between the chipset and the buffer. The second sub-interface is between the buffer and the memory modules. The method also includes interleaving output of the memory ranks in the memory modules, and configuring the at least one buffer to properly latch data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.

Real time application accelerator and method of operating the same

Abstract: An apparatus and method for accelerating execution of an application running on a data processing system coupled to a memory system (100) through a data network (120). Generally, the apparatus includes a memory matrix (110) in the memory system (100). The memory matrix (110) has a number of memory devices (200) arranged in banks (205) each with a predetermined number of devices, a memory controller (210) coupled to the banks for accessing the devices, and a processor (265) coupled to the controller and through the network (120) to the data processing system. The controller (210) includes at least one application programming interface configured to store, manipulate, and retrieve data in the devices based on a property of the data. Preferably, the memory matrix (110) is SQL enabled. In one embodiment, the devices (200) are Random Access Memory devices, and the controller (210) is adapted to provide on-demand random access to data stored anywhere in the memory matrix (110).

Semiconductor integrated circuit, computer system, data processor and data processing method

Abstract: A memory having a data processing function is connected with a memory network such as a memory bus. A memory controller writes data to be processed in a predetermined area in the memory having the data processing function. The memory having the data processing function processes the written data and stores resultant processed data. Thereafter, the memory controller reads the stored resultant processed data. Accordingly, work data (intermediate data obtained during the processing) is not transferred to the memory controller through the memory bus but is processed within the memory having the data processing function. As a result, the data processing ability can be improved. In the memory having the data processing function, a processing specification for the processing to be executed is written immediately before executing the processing. Accordingly, no work data is transferred through the memory bus between a CPU and the memory serving as a work area for the processing. Thus, the data processing ability can be improved.

Method and apparatus for using data compression as a means of increasing buffer bandwidth

Abstract: A method and apparatus for increasing the bandwidth of a memory controller system are provided. According to the invention, data received at an interface of a memory controller system is compressed in the memory controller by a compression engine for storage in associated memory. The address of the data written to memory is maintained in a memory controller. When data is read from the memory for provision to an interface of the memory controller, the memory manager retrieves the data from memory and provides it to a decompression engine. The decompression engine restores the data to its original, uncompressed form. The data is then provided to the appropriate interface.

The Impulse memory controller

Abstract: Impulse is a memory system architecture that adds an optional level of address indirection at the memory controller. Applications can use this level of indirection to remap their data structures in memory. As a result, they can control how their data is accessed and cached, which can improve cache and bus utilization. The Impulse design does not require any modification to processor, cache, or bus designs since all the functionality resides at the memory controller. As a result, Impulse can be adopted in conventional systems without major system changes. We describe the design of the Impulse architecture and how an Impulse memory system can be used in a variety of ways to improve the performance of memory-bound applications. Impulse can be used to dynamically create superpages cheaply, to dynamically recolor physical pages, to perform strided fetches, and to perform gathers and scatters through indirection vectors. Our performance results demonstrate the effectiveness of these optimizations in a variety of scenarios. Using Impulse can speed up a range of applications from 20 percent to over a factor of 5. Alternatively, Impulse can be used by the OS for dynamic superpage creation; the best policy for creating superpages using Impulse outperforms previously known superpage creation policies.

Flash memory controller with updateable microcode

Abstract: A flash memory controller with a volatile program and data memory is disclosed. The controller loads microcode and data into the program and data memory from a flash memory array upon powerup of the controller. If an error occurs during the download or the microcode does not exist in the flash memory array, then the controller loads microcode and data into the program and data memory from the host computer. In some embodiments of the invention, an initial code is downloaded to the controller so that an evaluation of the configuration of the controller and the flash memory can be communicated to a host computer. The host computer then downloads for storage into the flash memory a tailored microcode and restarts the controller so that the tailored microcode is loaded from the flash memory and executed. In some embodiments, a protection circuit is provided to protect the microcode from accidentally being erased from the flash memory. Additionally, in some embodiments, an interleaved data structure is utilized to minimize wait times during read and write operations to the flash memory.

Semiconductor memory and method for controlling the same

Abstract: A semiconductor memory operates in a write mode and a read mode. The memory includes memory cells, pairs of bit lines connected to the memory cells, sense amplifiers having first and second I/O terminals connected to the bit lines, column selection gates connected to the associated sense amplifiers, and a control circuit. The control circuit controls the sense amplifiers and the column selection gate, so that selected column selection gate turns on before the sense amplifiers are activated during the write mode. The write data is applied to the first I/O terminals of the sense amplifiers. The semiconductor memory thus produced according to the present invention has a reduced circuit size.

Dynamically-tunable memory controller

Abstract: A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit. Dynamic tuning may also utilize a unique binary search engine circuit arrangement that updates one of two registers with an average of the current values stored in such registers based upon the result of a test performed using that average value. By selectively updating such registers, a fast convergence to an optimum value occurs with minimal circuitry.

Method and architecture to calibrate read operations in synchronous flash memory

Abstract: Architecture to calibrate read operations in non-volatile memory devices. In one embodiment, a synchronous flash memory is disclosed. The synchronous flash memory includes a read sense amplifier, a verification sense amplifier, a switch, and an output buffer. The switch alternates electrical connection of the output buffer with the read sense amplifier and the verification sense amplifier. By measuring the distributions of voltage thresholds of erased cells versus voltage thresholds of programmed cells, differences in offsets between read state and write state of memory cells are determined. A specific margin is determined to ensure proper reads of the memory cells.

Memory built-in self-repair using redundant words

Abstract: A word oriented memory Built-In Self-Repair (BISR) methodology is described without modifying the memory module. Faulty addresses and its data are stored in the redundancy logic immediately after its detection during test. Fuse boxes can be connected via scan registers to the redundancy logic.

The memory gap and the future of high performance memories

Abstract: The first main memories to be used on digital computers were constructed using a technology much slower than that used for the logic circuits, and it was taken for granted that there would be a memory gap. Mercury delay line memories spent a lot of their time waiting for the required word to come round and were very slow indeed. CRT (Williams Tube) memories and the core memories that followed them were much better. By the early 1970s semiconductor memories were beginning to appear. This did not result in memory performance catching up fully with processor performance, although in the 1970s it came close. It might have expected that from that point memories and processors would scale together, but this did not happen. This was because of significant differences in the DRAM semiconductor technology used for memories compared with the technology used for circuits. The memory gap makes itself felt when a cache miss occurs and the missing word must be be supplied from main memory. It thus only affects users whose programs do not fit into the L2 cache. As far as a workstation user is concerned, the most noticeable effect of an increased memory gap is to make the observed performance more dependent on the application area than it would otherwise be. Since 1980, the memory gap has been increasing steadily. During the last ten years, processors have been improving in speed by 60% per annum, whereas DRAM memory access has been improving at barely 10%. It may thus be said that, while the memory gap is not at present posing a major problem, the writing is on the wall. On an Alpha 21264 667 MHz workstation (XP1000) in 2000, a cache miss cost about 128 clock cycles. This may be compared with the 8 – 32 clock cycles in the minicomputer and workstations of 1990 [1]. If the memory latency remains unchanged, the number of cycles of processor idle time is doubled with each doubling of speed of the processor. A factor of four will bring us to about 500 clock cycles.

Asynchronous hidden refresh of semiconductor memory

Abstract: Improved semiconductor integrated circuit random access memory (RAM) features pin-compatible replacement of SRAM devices, while providing low power and high density characteristics of DRAM devices. The refresh operations of a DRAM array are hidden so as to faithfully emulate an SRAM-type interface. The new refresh strategy is based on prohibiting the start of a refresh operation during certain periods but otherwise continuously refreshing the array, rather than affirmatively scheduling refresh at certain times as in the prior art. Short refresh operations are initiated frequently, driven by an internal clock that generates periodic refresh requests, except when a read or write operation is actually accessing the memory array. By isolating the DRAM memory array from I/O structures, external memory accesses are essentially interleaved with refresh operations, rather than temporally segregating them as in prior art.

Memory module system

Abstract: A memory module system includes a plurality of memory integrated circuit fixtures, and a memory integrated circuit is attached on each of the memory integrated circuit fixtures by forced contact method. The attached memory integrated circuit can be removed from a corresponding memory integrated circuit fixture. Memory size of memory module systems can be increased, and defective memory integrated circuits can be replaced easily by users.

Method and system for distributed power generation in multi-chip memory systems

Abstract: Techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips) are disclosed. The various voltage levels can be produced by charge pump and regulator circuitry within the memory system. The various voltage levels can be supplied to the multiple memory blocks through a power bus. According to one aspect of the invention, charge pump and regulator circuitry is not only provided within each of the memory blocks of a memory system, but also the charge pump and regulator circuits are not used to supply voltage signals to their own memory blocks. Instead, the charge pump and regulator circuits are used to supply voltage signals to other memory blocks.

Hot-replace of memory

Abstract: A method of replacing a memory module in a computer system. Specifically, a method for replacing a memory module in a segment of a redundant memory system, without powering-down the memory system.

Memory module resync

Abstract: A technique for resynchronizing a memory system. More specifically, a technique for resynchronizing a plurality of memory segments in a redundant memory system after a hot-plug event. After a memory cartridge is hot-plugged into a system, the memory cartridge is synchronized with the operational memory cartridges such that the memory system can operate in lock step. A refresh counter in each memory cartridge is disabled to generate a first refresh request to the corresponding memory segments in the memory cartridge. After waiting a period of time to insure that regardless of what state each memory cartridge is in when the first refresh request is initiated all cycles have been completely executed, each refresh counter is re-enabled, thereby generating a second refresh request. The generation of the second refresh request to each of the memory segments provides synchronous operation of each of the memory cartridges.

Consolidation of allocated memory to reduce power consumption

Abstract: A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage. When allocating memory, the memory is allocated from the sorted page list so that memory is preferentially allocated from those memory devices that are already receiving the highest usage.

Memory interface and method of interfacing between functional entities

Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.