Showing papers on "Network switch published in 1993"

Data Server, Control Server and Gateway Architecture System and Method for Broadcasting Digital Video on Demand

Abstract: A data processing system is disclosed for providing digital video information on subscriber demand, for very large video data files. The system enables rapid response to the requests by network subscribers, independent of the number of video files offered for selection. The data processing system is coupled through a data switch to a subscriber communications network.

High speed data transfer over twisted pair cabling

Abstract: A method provides for a first network node in a plurality of network nodes to transmit a data packet to a hub. The hub and the network nodes are interconnected within a local network system. Control signals are exchanged between the first network node and the hub. The exchange of control signals is done in a first signal frequency range. A data packet is sent from the first network node to the hub. The data packet is sent using data signals within a second signal frequency range. The first signal frequency range and the second signal frequency range do not overlap.

Connection of mobile devices to heterogenous networks

Abstract: An improved apparatus for connecting a mobile end system to a communications network includes a mobile end system with storage that is assigned a first unique identity code. An interface with a first transmitter is assigned a second unique identity code and is linked to the mobile end system via a first communications channel. A data switch with a second transmitter is assigned a third unique identity code, and is linked to the interface via a second communications channel. The data switch is also linked to the communications network via a third communications channel. The mobile end system transmits at least the first unique identity code to the interface, which transmits a least the first and second unique identity codes to the data switch, which in turn transmits at least the first, second and third unique identity codes to the communications network. A method of communicating data packets bidirectionally between two mobile end systems or between a mobile end system and a fixed end system through a communications network includes the steps of assigning unique identity codes to each mobile end system and to an interface device and a data witch for each mobile end system, setting up communication channels between the end systems, identifying the routing scheme to be used for the packet transmission, and establishing bidirectional communications between the end systems.

Electrically programmable inter-chip interconnect architecture

Abstract: A user-programmable inter-chip interconnect architecture, which may be used for providing programmable interconnections among a plurality of integrated circuits, is disclosed. A plurality of main circuitry in the core region of an integrated circuit is connected through connection nodes to a programmable peripheral switch network in the frame region of the integrated circuit. The peripheral switch network may be programmed by the user to obtain the desired signal-propagating paths between said connection nodes and bonding pads of the peripheral switch network, or among bonding pads of the peripheral switch network. The peripheral switch network has intersecting wiring channels attached to the bonding pads and the connection nodes. Programmable junctions may be present at the intersections of the wiring channels. A substantial number of desired interconnections may be achieved that have only one such programmable junction in the signal-propagating path. When a plurality of integrated circuits including this architecture arc mounted on a substrate that provides fixed conductive leads between the bonding pads of the integrated circuits, user-programmable, highly flexible, high-performance two-point and multi-point connections among the main circuitry of the integrated circuits are obtained.

Design and performance analysis of the algorithms for channel allocation in cellular networks

Abstract: The authors consider the problem of dynamic channel allocation in cellular networks. Each cell can use any channel, subject to the interference constraints. Channel allocation algorithms are executed by the network switch in a centralized way. The authors show how to design and use objective functions aimed at proper channel allocation and improvement of network performance. As a figure of merit of network performance, they consider the blocking probability in the network as a whole, and the maximum blocking probability in any particular cell of the network ("hot-spot" in the network). They designed three specific channel allocation policies, based on three different objective functions. Compared with two other benchmark policies, the approach shows significant improvement. Performance analysis of various channel allocation policies is virtually impossible without simulations, which are prohibitively time-consuming in the case of small blocking probabilities. The authors propose an original approximate method based on a short simulation and an analytic approximation. The method exhibits good accuracy and significant improvement in efficiency. >

Detection of a relative location of a network device using a multicast packet processed only by hubs

Abstract: Within a network, which includes hubs and bridges, the relative location of a first device with respect to a subset of hubs on the network is determined. In response to an instruction, the first device broadcasts a multicast packet. The multicast packet crosses bridges and is processed only by hubs. When a hub receives the multicast packet from the first device, the hub records a first port of the hub over which the second device received the multicast packet. The subset of hubs may then be interrogated to determine over which port of each of the subset of hubs the multicast packet was received.

Switching hub which implements a virtual bus for interconnecting stations on a CSMA network

Abstract: An apparatus for interconnecting a plurality of segments each of which operates in accordance with a bus protocol specifying collision detection and propagation operations. The apparatus includes a switching mechanism including a backplane having P signal paths and P switch ports each with an input and an output. The input of each switch port is connected to a different one of the P signal paths and at each switch port it connects a selectable one or more of the P signal paths to the output for that switch port. The apparatus also includes a plurality of port circuits each connected to a different one of the ports of the switching mechanism. Each port circuit includes an interface to which one of the plurality of segments is connected and through which that port circuit receives a data signal from and transmits a data signal to the attached segment; an auto-partition state machine connected to the interface for that port circuit receiving the data signal from the segment connected to that port circuit's interface and generating therefrom a single output signal on the output line of that port circuit, the auto-partition state machine performing partitioning functions for that port circuit' s segment; and a control state machine receiving a signal over the input for that port circuit and using that signal to implement the collision detection and propagation operations of the bus protocol for the segment connected to that port circuit.

LAN management system in electronic switching apparatus

Abstract: A switching apparatus for constructing a system integrating a telephone switching network and a LAN includes: line interface sections, each connected to a transmission line for transmitting a signal on which low-speed data and high-speed data are multiplexed; a low-speed data switch for switching low-speed data demultiplexed in each line interface section; a high-speed data switch for switching high-speed data demultiplexed in each line interface section; and a processor for monitoring and controlling the data traffic passing through the low-speed data switch and high-speed data switch. An address in a designated position in the high-speed data demultiplexed in each line interface section is read out, whereby the association between the low-speed data terminal and high-speed data terminal is identified and stored. By referring to this association, management of LAN terminals can be performed using the maintenance operation procedures used in a conventional electronic switching apparatus.

Switch-based microchannel planar apparatus

Abstract: Disclosed is a modularly expandable switch-based planar apparatus for inserting multiple bus-based processor cards and/or expansion cards and interconnecting the said cards via a multi-stage switch network which resides on the invention planar. The switching network is built into the planar. The cards require no modification or change of any kind, since the connection to the planar is made as if the planar contained the standard MicroChannel interconnection. However, the disclosed planar implements bus converter units to convert the standard bus interface provided by the cards to the switch network interface, so that functions provided by the cards can communicate in parallel over the switch network.

Isochronets: a high-speed network switching architecture

Abstract: An overview is given of a switching architecture for high-speed networks called Isochronets, which time-divide network bandwidth among routing trees. Traffic moves down a routing tree to the root during its time band. Network functions such as routing and flow control are entirely governed by band timers and require no processing of frame header bits. Frame motions need not be delayed for switch processing, allowing Isochronets to scale over a large spectrum of transmission speeds and support all-optical implementations. The network functions as a media-access layer that can support multiple framing protocols simultaneously, handled by higher layers at the periphery. Internetworking is reduced to a simple media-layer bridging. Isochronets provide flexible quality of service control and multicasting though allocation of bands to routing trees. They can be tuned to span a spectrum of performance behaviors outperforming both circuit and packet switching. >

Method and apparatus for determining if a data packet is addressed to a computer within a network

Abstract: A system is disclosed that allows a computer system within a network environment to determine whether a data packet is to be processed by a particular computer system. This is accomplished through an address matching scheme that provides for an LED indication that the computer is to utilize the data packet provided by the network. In so doing, the system provides more capability to the computers on a network to operate more efficiently.

A burst-level adaptive input-rate flow control scheme for ATM networks

Abstract: An input rate flow control mechanism, the burst level feedback scheme, is introduced and studied. Burst level information is used to gain performance improvement. An analytical methodology, based on queuing models, is presented for the analysis and performance evaluation of this scheme. Performance results are shown to illustrate the features of the analytical technique and to demonstrate the performance improvement obtained by the scheme. This input rate control method is shown to be effective for traffic regulation at the access to an asynchronous transfer mode (ATM) network loaded by highly bursty stations. The analytical tools developed allow the system designer to evaluate the proper level of input regulation that should be used to guarantee acceptable queue-size and delay levels at the source station's buffer and at the buffer of the shared network switch. >

Network adapter which places a network header and data in separate memory buffers

Abstract: A computing system is connected to a network. The computing system (10) includes a main memory (11) and a network adapter (12). The network adapter (12) receives a network packet from the network. The network adapter (12) determines a location of a split between a header of the network packet and data contained in the network packet. The network adapter (12) places the header for the network packet into a first memory buffer in the main memory (11) and places the data contained by the network packet beginning at a second memory buffer in the main memory (11). A portion of the first memory buffer which is not filled by the header for the network packet is filled with pad data.

On the design of a local switch for heterogenous multi-subsystem interconnect

Abstract: Before heterogenous networks evolve to all-ATM, multimedia communications are likely to cross over different networks operated at various speeds and protocols. An effective multimedia interconnection network or the so called switching hub must be able to handle various traffic patterns such as continuous, isochronous and connectionless data. Due to the limitations of current implementation such as backplane bus and shared memory the authors present a new platform, multi-subsystem interconnect (MSI) model which is based on a parallel and fast packet switching technique. The main part of MSI is a time-multiplexed space division switching fabric with the capability of simultaneous path resolution and packet transfer. The whole structure consists of a set of reusable building blocks. In realization the interface hardware can be implemented with a few ASICs applicable for different subsystems. >

Wide-address spaces: exploring the design space

Abstract: In a recent issue of Operating System Review, Hayter and McAuley [1991] argue that future high-performance systems trade a traditional, bus-based organization for one where all components are linked together by network switches (the Desk-Area Network). In this issue of Operating System Review, Leslie, McAuley and Mullender conclude that DAN-based architectures allow the exploitation of shared memory on a wider scale than just a single (multi)processor. In this paper, we will explore how emerging 64-bit processors can be used to implement shared address spaces spanning multiple machines.

The 5ESS® wireless mobile switching center

Abstract: The growing market for wireless telecommunications services is resulting in a strong movement toward digitizing these services. Currently, three digital wireless standards are specified. Each includes a mobile switching center (MSC) as the centralized network switching and call control entity. The MSC must be adaptable to a variety of network and service environments, and must support a broad range of sophisticated end-user services. AT&T's 5ESS® Switch supports the MSC function for two of the three digital wireless standards, and is an integral component of the AT&T MSC product for the third standard. Reuse of the existing hardware platform, designing wireless functionality as incremental extensions of the existing software architecture, and support of intelligent network (IN) capabilities on the 5ESS MSC, results in a uniquely matched solution for providing wireless services in a wide variety of network environments and applications.

A hardware implementation of channel allocation algorithms based on a space-bandwidth model of a cellular network

Abstract: A hardware device called Channel Allocator is proposed to speed up channel allocation and to select the appropriate channel allocation algorithm according to the current traffic requirements and/or interference conditions. The main advantage of Channel Allocator is its high efficiency in allocation of available radio channels (order of nanoseconds). Channel Allocator belongs to the architecture of the network switch. Several channel allocation algorithms can be incorporated within Channel Allocator at the same time. If the traffic and/or interference conditions change, Channel Allocator selects the channel allocation algorithm (among the available) which provides a desired performance for the new conditions. >

The reliability of LEC telephone networks

Abstract: The reliability of local exchange carrier (LEC) networks is described using data obtained from diverse sources. These sources are Bellcore's Outage Performance Monitoring (OPM) process, which is designed to collect information on switch outages lasting two minutes or longer, the Automated Report Management Information System (ARMIS), which supplies reports to the US Federal Communications Commission (FCC) to show industry trends in network reliability, and the US General Accounting Office (GAO), which has recently collected information on each outage lasting at least 15 min and affecting at least 10000 lines during 1990 and 1991. The data show that the availability of network switches is at least 99.9981%, meaning that 99.9981% of the time a customer wants to make an intraoffice call, the switch will be up. The chance that the path between two switches is available is 99.9986%. For interoffice calls involving two switches, the availability of the interoffice network is estimated to be 99.9948%. >

An OC-12/STS-3c/ATM interface for gigabit network applications

Abstract: The implementation of an experimental OC-12/STS-3c/ATM transmission interface for use in the AURORA Gigabit Testbed is described. This interface maps four streams of asynchronous transfer mode (ATM) cell data from network switch nodes and computer hosts into the Synchronous Optical Network (SONET) STS-3c transmission format and multiplexes these channels onto a single OC-12 (622 Mb/s) optical signal for transmission to remote network nodes. The interface also performs the reverse demultiplexing functions. It has been tested in both a stand-alone configuration and in one of its intended applications, as an element in an interface between a workstation and an OC-12 ATM/SONET network. This application represents the first known demonstration of a 622-Mb/s ATM workstation interface. >

Master microchannel apparatus for converting to switch architecture

Abstract: Disclosed is a conversion apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel~ bus, to more progressive switch interconnection protocol and architecture. The invention extends existing the bus-based architecture to perform parallel and clustering functions by enabling the interconnection of thousands of processors. A conversion apparatus is disclosed for controlling the transfer of data messages from one nodal element across a switch network to another nodal element by using direct memory access capabilities controlled by intelligent bus masters. This approach does not require interactive support from the processor at either nodal element during the message transmission, and frees up both processors to perform other tasks. In addition, the communication media is switch-based and is fully parallel, supporting n transmissions simultaneously, where n is the number of nodes interconnected by the switching network.

Cluster model for optimal double-loop connected network

Abstract: This paper investigates the solution of the optimization problem that appears in the design of double loop structured local area computer networks or interconnection networks Double loop structure is a regular, two-connected network, designed for packet communications The studies of degree two network connection schemes is based on the circular graphs of degree four These graphs are regular, vertex-symmetric, and maximally connected, and such optimal graph exists for any given number of nodes Every four of two-connected nodes consists a cluster, so cluster is a component with four input and four output link in the network The proposed cluster network forms the optimal connection of a circular graph We demonstrate how to construct one such network for any number of nodes and examine their network properties The problem of routing is also addressed, and two routing rules are investigated that take advantage of the network regular structure >

Medium access control bridge device

Abstract: PURPOSE:To efficiently transfer data between ports by standardizing packet transfer formats between ports in a MAC bridge where ports of various kinds of LAN system exist together and adding an identifier indicating the protocol classification of a source port to a packet. CONSTITUTION:Reception data from a CSMA/CD LAN is generally broadcasted to another port through an interface 11 by a bus interface 12. At this time, an identifier field indicating the CSMA/CD LAN is added to the packet. Meanwhile, the reception packet from another port has the identifier field discriminated by a bus interface 13 to discriminate the protocol. A conversion circuit 14 converts the paket on a token ring to the CSMA/CD format, and a selecting circuit 15 selects the use of data passing circuit 14 or the user of data directly received from the circuit 13. This selection is indicated by the analysis result of the identifier field of the reception packet in the circuit 13.

An artificial neural network and knowledge-based method for reasoning causes of power network faults

Abstract: Understanding the cause of a fault in an electric power system in the system operation is essential for quick and adequate recovery actions such as the determination of the propriety of carrying out forced line charging and the necessity of network switching, and efficient patrolling. In this paper, the authors discuss a technique using an artificial neural network and knowledge-base for reasoning causes of power network faults and present the results obtained from a verification in which this technique was applied to a prototype system. >

Parallel BLAS and BLACS for numerical algorithms on a reconfigurable network

Abstract: We study basic parallel linear algebra algorithms: matrix product, matrix transposition, broadcast and scattering operations, and their chaining (rank-2k updates). For all those basic routines, we compare one method using a fixed 2D-torus topology and another one using the capabilities of reconfiguration of the interconnection network. Generally, distributed-memory machines use fixed networks such as multidimensional tori or hypercubes. Today, machines that can be reconfigured during program execution are available. Thus, a large number of possibilities are available to the programmer, who can adapt his configuration during runtime to suit both best algorithm and data distribution. Obviously, this dynamical reconfiguration introduces an overhead through the setting of the network switch. This overhead must be taken into account in the cost of the whole computation. Using complexity analysis, we show the advantages and the drawbacks of the switching solution.

Switch-based personal computer interconnection apparatus

Abstract: Disclosed is a modularly expandable switch-based apparatus which is used to interconnect multiple Personal Computers as nodes of a parallel system. The invention includes a bus-based expansion card which is inserted into a card slot in each of the Personal Computers to provide an adaption from the Personal Computer MicroChannel to the interface to a multi-stage switch network. Thus, the disclosed invention provides a means for extending the MicroChannel architectures to either massively parallel systems or thousands of I/O device taps or a combination of the two. This is accomplished by using electronic switches to interconnect various Personal Computers, where each computer has a unique local bus that can be composed of 1 to 8 MicroChannel taps (card slots). An expansion card containing a bus architecture converter unit is used in one expansion card slot in each Personal Computer to adapt the node to the switch network. The result is that the Personal Computers are fully interconnected and capable of sending data, communications, and/or messages between any two Personal Computers, which become nodes of the parallel system.

Adaptive Channel Allocation in Cellular Networks With Multi-User Platforms

Abstract: This paper proposes a hardware solution to the efficient utilization of cellular networks with single-and multi-terminal platforms. In such networks, a mobile platform (e.g., an airplane) can carry more than one wireless terminal. A good utilization of available channels as a shared resource is important for quality and efficient communications in the network. In this paper, we propose the Integrated Channel Manager (ICM), an architecture for fast adaptive channel allocation. It is an integrated controller connected to the system bus within the network switch. Its main advantage is a fast allocation of available channels when a request for a call initialization or a hand-off exists. Its efficiency is achieved via channel allocation functions supported by a hardware with high degree of parallelism. The ICM supports both single and multiple hand-offs. It allows an efficient rejection of a call when the call cannot be supported. Thus, it reduces the processing overhead for rejected calls.

Network switching system

Abstract: PURPOSE:To simplify the circuit and provide automatic and easy switching to an effective network in the case of fault or abnormality occurrence, and to eliminate a break against a permanent fault. CONSTITUTION:A centralized control station 1 and a general station 3 output outputs detection signals when the levels of reception from networks 21 and 22 detected by level detecting circuits 111 and j112 are higher than a prescribed level L. A logical decision circuit 12 outputs an abnormality detection signal 17 according to the detection signals to switch the level detecting circuits 11. A network control circuit 19A controls transmission by switching based on the abnormality detection signal 17 and a network control circuit 19B controls switching to a stand-by mode according to the abnormality detection signal 17.

Congestion control in integrated service networks

Abstract: In this dissertation we study the design of adaptive decentralized control schemes to control the traffic characteristics of connections. We examine how the arrival rate of traffic at network switches can be adjusted using explicit feedback based congestion control mechanisms. We investigate how such modulation may be achieved for three classes of applications, namely data, image and video. We show that the use of predictive control mechanisms can be used to effectively counter the effects of the relatively large time delays in high speed networks. We study the performance of the control mechanisms both in terms of the utilization of network resources as well as the service quality seen by users. Our results demonstrate that well designed, feedback-based congestion control mechanisms perform well in high speed integrated service networks. In this dissertation we also investigate how scheduling mechanisms at network switches may be used to allocate bandwidth dynamically between different classes of traffic. We show that the use of fairly simple techniques can improve performance when the service quality requirements of different traffic classes differ significantly.

Design and implementation of ArbNet-II

Abstract: ArbNet-II is a local network intended to provide an alternate local network solution that is robust and flexible in configuration, and is capable of supporting concurrent transmissions at the packet level. The network consists of two main components, the network interface unit and the switch; the former performs medium access control while the latter routes packets within the sub-network. This paper focuses on the design and implementation experience of an experimental prototype network, and presents the results of a preliminary performance measurement.