Showing papers on "Reading (computer) published in 2001"

Flashtoaster for Reading Several Types of Flash-Memory Cards, With or Without a PC

Abstract: A flash-memory-card reader reads and writes multiple types of flash-memory cards, including CompactFlash, and the smaller SmartMedia, MultiMediaCard, Secure Digital, and Memory Stick. A converter chip converts the different card signals for transfer to a host personal computer (PC). Serial-to-parallel data conversion is performed for the smaller card formats with serial data interfaces, but not for CompactFlash with a parallel-data interface. A single slot has a 50-pin connector for CompactFlash cards or passive adapters. The passive adapters have the CompactFlash form factor and a smaller connector fitting smaller flash cards. Passive adapters have no components but simply wire the smaller connector to the CompactFlash connector. A pin mapping allows card-type detection by sensing the LSB address pins of the CompactFlash interface. A larger CompactFlash reader has multiple slots for each card type. The reader is connected to the PC by a cable, or located within the PC chassis in a drive bay. A stand-alone reader copies images from the flash-memory card to a removable disk media. Pressing a button initiates image transfer.

Electrically alterable non-volatile memory with N-bits per cell

Abstract: An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The programming signals include at least a first programming signal which programs the cell by a first increment and a subsequent programming signal which programs the cell by a second increment smaller than the first increment. As the cell is being programmed to a selected state, its programming status is verified independently of reference values bounding the memory states. For this purpose, a signal indicative of the programming status (e.g., the cell's bit line signal) is compared with a reference signal corresponding to the selected state but having a value different from the reference value or values bounding the selected state. The programming operation can thus be controlled without actually reading the memory state of the cell.

Method and system for securing local database file of local content stored on end-user system

Abstract: A method and system for forming a data table in memory on an end user system. The data table forming a library index of storage locations to electronic digital content in memory. The method consists of retrieving an encrypted file from storage. The file has a beginning, an end and a trailer section located just prior to the end. The file is read from the end a predetermined distance to verify if an identifier is present. Reading and decrypting the trailer section from the file read. Determining if there are any updates in the trailer section. In the case there are no updates in the trailer section then decrypting the reference table containing one or more data table location indicators for data items with the first decrypting key. Next, decrypting one or data items with the first decrypting key. Populating the data table with data items at locations specified in the reference table.

Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system

Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

Method and apparatus to operate a memory cell

Abstract: Briefly, in accordance with an embodiment of the invention, a method and an apparatus to read a phase change memory is provided, wherein the method includes zero biasing unselected memory cells during reading of a selected memory cell.

Self-writing of servo patterns in disk drives

Abstract: A method and system for self-servo writing a disk drive by transferring a servo reference pattern by magnetic printing onto at least one storage surface of a reference disk, wherein a resulting printed reference pattern includes embedded servo information providing servo timing and transducer head position information; assembling the disk drive including the steps of installing at least said disk into the disk drive and enclosing said disk and the data transducers within a housing sealed against particulate contamination from an eternal ambient environment; reading the printed reference pattern from said disk via at least one transducer head to generate a readback signal; sampling the readback signal at a sampling rate to generate a sampled signal; processing the sampled signal waveform specturm to generate a recovered signal including the embedded servo information and a fundamental frequency of the sampled signal; using the servo information from the recovered signal to precisely position and maintain the data transducers at concentric track locations of disk storage surfaces; and self-writing disk drive servo patterns onto the storage surfaces at the concentric track locations with the data transducers in accordance with disk drive servo pattern features.

Image forming device

Abstract: PROBLEM TO BE SOLVED: To provide an image forming device capable of more definitely, and more efficiently performing appropriate density control corresponding to various originals with the different density condition, etc., by providing the image density controlling means equipped with plural controlling means, and selecting control system of image density controlling means, based on the original density information. SOLUTION: Based on the control sequence of ROM 14, the original reading (scanning) operation is started after a lamp 5 is turned on, photometric value is averaged (10msec unit for instance), from a light receiving sensor 10 stored in RAM 13 within a specific time, and the average value (original density information) is compared with the predetermined threshold. At this time, if the average value becomes equal to or above the threshold (when original density is comparatively dark), 'real time controlling system' is selected as the controlling system of the transferring bias output circuit 17 for the developing bias circuit 16, in predicting the presence of low density image part in the original center part, etc., and on the contrary, if the average value becomes smaller than the threshold, 'hold controlling system' is selected as the controlling system.

System, method, and device for playing back recorded audio, video or other content from non-volatile memory cards, compact disks, or other media

Abstract: A secure software package for original equipment manufacturers to run in electronic devices in order to access and dynamically decrypt encrypted audio video or other content from a memory storage device such as a memory card, optical or hard disk such that the user interface of the device need only send simple commands and the decrypted content is output.

System and method for performing scalable embedded parallel data decompression

Abstract: A parallel decompression system and method that decompresses input compressed data in one or more decompression cycles, with a plurality of tokens typically being decompressed in each cycle in parallel. A parallel decompression engine may include an input for receiving compressed data, a history window, and a plurality of decoders for examining and decoding a plurality of tokens from the compressed data in parallel in a series of decompression cycles. Several devices are described that may include the parallel decompression engine, including intelligent devices, network devices, adapters and other network connection devices, consumer devices, set-top boxes, digital-to-analog and analog-to-digital converters, digital data recording, reading and storage devices, optical data recording, reading and storage devices, solid state storage devices, processors, bus bridges, memory modules, and cache controllers.

Card reading device for service access

Abstract: A read device (1) for reading an interface card (10) is disclosed. The card (10) is configured for insertion into the read device (1). The card (10) comprises indicia (14) formed thereon and a memory (19) having data stored therein for communicating with an external device. The read device (1) comprises a substantially transparent touch sensitive membrane (8) arranged to overlay the interface card (10) upon receipt of the card (10) in the read device (1). The read device (1) also comprises a central processing unit for sending a service identifier, and a specific portion of the data to the external device. The specific data is related to a user selected indicia (14), wherein the external device provides a service identified by the service identifier upon receipt of the data.

User terminal for channel-based internet network

Abstract: A user terminal for a channel-based network, the user terminal including a set-top box (131), a display (132), and one or more input devices (133). The set-top box includes a non-volatile memory (219) for storing a semi-permanent copy of a channel table downloaded from a server via the Internet. The channel table includes a list of channel numbers, associated Internet site names, and associated Internet addresses. The user terminal also includes a volatile memory (218) for storing a temporary copy of the channel table during user sessions. The channel numbers and associated Internet site names are read from the volatile memory and displayed in a menu-like manner. A user selects an Internet site name from the displayed menu, and enters the channel number associated with the selected Internet site name using a numeric keypad provided on an input device that is similar to a television remote control. The user terminal then accesses the selected Internet site by reading the Internet address associated with the entered channel number from the volatile memory, and transmitting the Internet address onto the Internet.

Multi-bit-per-cell memory system with numbers of bits per cell set by testing of memory units

Abstract: A manufacturing method for a multiple-bit-per-cell memory tests memory arrays in the memory and separately sets the number of bits stored per cell in each memory array. Memory arrays that testing proves are accurate when writing, storing, and reading a larger number of bits per cell are set to store more bits per cell, and memory arrays that cannot accurately write, store, or read as many bits per cell are set to store fewer bits per cell. The setting of the numbers of bits per cell for the respective memory arrays can maximize the memory capacity when some arrays perform better than expected. When the memory arrays perform worse than expected, the setting of the numbers of bits per cell can salvage the memory device even if the memory cannot provide the expected memory capacity.

Page-erasable flash memory

Abstract: The invention concerns a page-erasable flash memory (MEM1) comprising a memory plane (FMA) including a plurality of pages comprising each floating gate transistors connected by their gates to word lines (WL1), a word line decoder (XDEC1) connected to the memory word lines, and means for applying a positive erasing voltage (VER+) to the source or drain electrodes of all the floating gate transistors of a sector comprising a page to be erased. The invention is characterised in that the word line decoder (XDEC1) comprises means (ADi) for applying, during erasure of a page, a negative erasing voltage (VPOL, VER-) to the gates of the transistors of the page to be erased, while applying a positive inhibiting voltage (VINHIB, VPCX) to the gates of the transistors of at least one page not to be erased. The memory also comprises means controlling at least a page of the memory, designed to perform a first reading of the page by applying a first reading voltage (VREAD) to the gates of the transistors of the page, perform a second reading of the page by applying a second reading voltage (VVRFY) to the gates of the transistors of the page, and reprogram transistors of the page if the two readings yield different results (W1, W2).

Decoder apparatus and methods for pre-charging bit lines

Abstract: Methods and apparatus are disclosed for reading memory cells in a virtual ground memory core, wherein a memory cell is selected to be read and an adjacent memory cell is precharged so as to mitigate leakage current associated with the adjacent cell Decoder circuitry and methods are disclosed for selecting the memory cell to be read and the adjacent cell to be precharged, which may be used in single bit and dual bit memory devices, and which provide drain-side or source-side current sensing in the read operation

Memory device, method of accessing the memory device, and reed-solomon decoder including the memory device

Abstract: A memory device employs multiple dual-bank RAMs to allow simultaneous write/read operations. The memory may be utilized in a high-speed block pipelined Reed-Solomon decoder for temporarily storing input codewords during pipelined processing. A memory controller enables writing to and reading from the dual-bank RAMs during each of successive frame periods such that each bank of the dual-bank RAMs is read every given number of frame periods and is written every same given number of frame periods, and such that a read bank is contained in a different one of the dual-bank RAMs than is a write bank in each of the successive frame periods.

Nonvolatile semiconductor memory device

Abstract: A nonvolatile semiconductor memory device disclosed herein includes: a reference cell held in an ON-state; a reference cell held in an OFF-state; a driving transistor which is turned ON by a signal for reading out data from a memory cell, to supply a current to the memory cell; driving transistors which have a same construction and characteristics as the driving transistor and also which are turned ON by that signal to supply a current to the reference cells; and a sense-amplifier which has a first input terminal supplied with an output voltage of the driving transistor and a second input terminal supplied with an average (VRon+VRoff)/2 of output voltages VRon and VRoff of the driving transistors respectively.

Photographic prints carrying meta data and methods therefor

Abstract: A photographic print includes a sheet, such as a sheet of photographic paper, having a front face and a back face, and one or more images printed on the front face of the sheet. The photographic print includes meta data in a human invisible format attached to the sheet of photographic paper, the meta data including information related to the photographic print. The meta data may be encoded digital data stored on magnetic material such as a sheet of magnetic material that is attached to the photographic print. The meta data may also be printed on substantially transparent optical material in a format that is invisible to the human eye. The meta data may also be a magnetic material or optical material that is mixed with the ink used to print the one or more images on the photographic print. The meta data attached to the photographic prints may be read using a meta data scanner capable of reading the meta data and displaying the meta data in a visual or audio format.

Apparatus supporting multiple memory card formats

Abstract: An apparatus is described that is capable of receiving a number of different types of flash memory cards using a single slot. The apparatus includes a housing that defines a slot to receive different types of removable memory cards. The slot includes a central region of a first height and outer regions of a second height. A plurality of electrically conductive contact areas are disposed within the slot. The apparatus may receive, for example, any one of a Smart Media flash memory card, a Memory Stick flash memory card, a Secure Digital flash memory card, and MultiMedia flash memory card.

Method for fast wake-up of a flash memory system

Abstract: A system and method for enabling a fast wake-up of a flash memory system, without compromising the integrity of the flash data structures and without risking loss of data. This is achieved by storing translation tables in the flash, but adding some means for the software to invalidate them in a way that is detectable whenever reading them. Possible implementations include adding a checksum value that makes the sum of all entries equal some fixed known value, or adding a validity flag to the stored tables, enabling the tables to be invalidated at will. In addition, one should ask the application software to call a specific function in the translation layer before shutting the system down. The present invention enables fast wake-ups when the application software made an orderly exit and made us store the tables. In the case an orderly exit was not made, the present invention commands a regular wake-up procedure, thereby ensuring data intengrity.

Integrated circuit memory devices that utilize indication signals to increase reliability of reading and writing operations and methods of operating same

Abstract: Integrated circuit memory devices include a data latch circuit having a data input, a control input and a clock input, and a strobe signal input buffer. The strobe signal input buffer is preferably responsive to a data strobe signal and an indication signal. The strobe signal input buffer operates as a filter by selectively passing an inactive-to-active transition of the data strobe signal to the control input of the data latch when the indication signal is active, while blocking passage of the inactive-to-active transition of the data strobe signal to the control input when the indication signal is inactive. These filtering operations are preferably performed to inhibit the occurrence of data errors when excessive timing skew is present between a system clock and a data strobe signal at a given rate of speed. Accordingly, the operating speeds of memory devices according to embodiments of the present invention may be reliably increased. The data strobe signal and an unbuffered version of the indication signal are preferably generated by a memory controller, which may be operatively coupled to many memory banks within an integrated multi-bank memory system.

RAM-incorporated driver, and display unit and electronic equipment using the same

Abstract: The present invention provides a RAM-incorporated driver that enables the writing of moving-image data to a RAM simultaneously with the writing of still-image data to a RAM, at a reduced energy consumption. The RAM incorporated X-driver IC receives still-image data from an MPU and moving-image data that is input by a separate system through a high-speed serial transfer line in accordance with the LVDS standard. An LVDS reception circuit suppresses the consumption of a steady current by which the differential input receiver operates, based on a data validation signal that becomes active when transfer data on the high-speed serial data transfer line from the MPU becomes valid. The still-image data and moving-image data that is received by separate systems is written to a RAM through first and second bus lines, respectively. Reading of still-image data and moving-image data, which is stored in a RAM, as display data is controlled by a display address control circuit.

Dynamic flash memory cells with ultra thin tunnel oxides

Abstract: Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10−17 Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angstroms, in order to add or remove a charge from a floating gate. The method further includes reading the n-channel memory cell by applying a potential to a control gate of the n-channel memory cell of less than 1.0 Volt.

Portable automated banking apparatus and system

Abstract: A transaction apparatus ( 10 ) includes a multifunction card ( 12 ) and a portable terminal ( 14 ). The multifunction card includes a programmable memory ( 18 ) and a magnetic stripe ( 16 ) thereon. The programmable memory on the card is used to store indicia corresponding to account data which is input to the memory by reading with the terminal magnetic stripe data from a plurality of conventional magnetic stripe cards. The programmable memory further includes data representative of cash value as well as instructions, prompt messages and icons presented in conducting transactions. A user is enabled to operate the apparatus to select one of the accounts stored in memory, and to write account data corresponding to the selected account to the magnetic stripe of the card. The user is also enabled to use the apparatus to enter visible indicia such as bar codes and to selectively reproduce the bar codes on the display of the apparatus. The apparatus is also selectively operative to transfer funds between accounts of the user and data representative of cash value stored on the card.

Method and system for processing and using information

Abstract: A method for processing information wherein information is received from a plurality of bar code scanners, preferably reading web codes, the source and destination information for the received information is determined and data from the received information is distributed to at least one destination identified by the destination information.

Non-volatile semiconductor memory device with programming voltage generating system and data programming method

Abstract: On a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

The copy protection of digital audio compact discs

Abstract: The ability of a data reader, such as a CD-ROM drive, to access, extract, or otherwise read the data on a digital audio compact disc provides a problem for the music industry. A user can use his CD-ROM drive to read the data from an audio disc into a computer file, and then that data can be copied. To provide copy protection, errors are deliberately introduced into the data on a CD, but these errors are of a type which are generally transparent to an audio player but which will interfere with the reading of the audio data by a data reader. According to the standards, the data on a CD is encoded into frames by EFM (eight to fourteen modulation). Each frame has sync data, sub-code bits providing control and display symbols, data bits and parity bits, and includes 24 bytes of data, which is audio data for a CD-DA. The standard requires that 98 such frames are grouped into a sector. To provide copy protection, each sector is provided with a non-standard number of frames, for example, has 99 rather than 98 frames. Then the S0 and S1 sub-code synchronisation patterns are placed one frame later than they otherwise would be, but the data within each frame remains the same. An audio player would divide the 24 bytes of data from each frame of the sector into 4 byte samples and continue playing the disc, albeit with an inaccurate time display. Howewer, a data reader used to read audio data from the CD-DA to enable a copy to be made, would produce a copy having a degraded quality of sound.

Polyphase electric rotary machine

Abstract: The invention concerns an electric machine comprising a front bearing (13), a rear bearing (14), a rotor (4) implanted between said bearings and a magnetic target (50) with axial or radial reading device fixed on a target holder implanted between the rotor (4) and one of said bearings. The invention is applicable to motor vehicles.

Universal serial bus flash memory storage device

Abstract: The invention provides a flash memory storage device that is connectable to a computer via a universal serial bus. The universal serial bus (USB) has become a standard serial interface which allows data to be stored in and read from an external memory device at high speed. Therefore, it is advantageous to combine the benefits of a flash memory device with the speed of the universal serial bus. In addition, by designing the flash memory device with a USB interface, the flash memory device appears as a standard USB storage device which permits the host and flash memory device to connect and interact with ease.

Method of managing a defect in a flash memory

Abstract: In a flash memory, error management units which store information on a physical occurrence position of an error which occurred during data reading are prepared by as much as the number of bits which can be corrected by an error correction code, in a redundant portion of a physical page. If the number of positions on which the error have occurred in a same physical page exceeds the number of the prepared error management units, then it is judged that the defect is uncorrectable.