Showing papers on "Redundant code published in 1989"

Method and apparatus for protecting software

Abstract: A method and system for protecting a software program recorded within a storage medium for use with or transmission to computer or processor based hardware comprises inputting a hardware code uniquely associated with the particular hardware and inputting a first software code uniquely associated with the particular embodiment of the software. A first predetermined operation is performed upon the hardware code and the first software code to produce an intermediate code. A unique activation code obtained from the software supplier is inputted and a second predetermined operation is performed upon the intermediate code and the activation code to produce a second intermediate code. The second intermediate code is compared to a second software code uniquely associated with the particular embodiment of the software and stored in a hidden location within the software. The use of the software is enabled only if the second intermediate code and the second software code are identical.

Method and apparatus for protecting computer software utilizing coded filter network in conjunction with an active coded hardware device

Abstract: Filter networks are incorporated within a software protection hardware device which is plugged into a communications port of a computer which device will select bits or combinations of bits emanating from the communications port resulting from commands of a controlling software in use with the computer which is desired to be protected. The filter networks select the bits of a disguised predetermined control code which when matched with a stored reference code results in an output from the filter used to activate functions within the protection device. A stream of bits including a disguised predetermined control code issuing from the computer through the security device are compared with a stored reference code in a programmable memory. When a match occurs an output emanates providing an acknowledgment code to the computer indicating that the hardware device has been plugged in and is a proper one. The stored reference code can be provided by a programmable memory using an intermediate storage register between the programmable memory and the selection network. The intermediate storage register is clocked changing the reference code in a predetermined manner. Accordingly, the reference code is changed in accordance with what is stored in the programmable memory and by the content of an intermediate register at any given time, the effect of which is to continually change the reference code by clocking the intermediate register.

A multiplication-free multialphabet arithmetic code

Abstract: A recursion for arithmetic codes used for data compression is described which requires no multiplication or division, even in the case of nonbinary alphabets. For this reason, such a code admits a simple and fast hardware implementation. The inputs to the code are, in addition to the symbols to be encoded, either the symbol probabilities or, more simply, the corresponding occurrence counts. Hence, the code is applicable in conjunction with stationary and nonstationary models alike. The code efficiency is typically in the range of 97-99%. >

A mechanically verified code generator

Abstract: We describe the specification, implementation and proof of correctness of a code generator for a subset of Gypsy 205 The code generator is specified in the Boyer-Moore logic; its proof is fully machine-checked using the Kaufmann-enhanced Boyer-Moore theorem prover Our code generator sits atop a ‘stack’ of verified system components providing a prototype development environment for constructing highly reliable application Programs

Pcm data transmitting apparatus and method

Abstract: A data transmission and reception apparatus and method capable of selecting either of two modes having the same sampling frequency in which the bit number of one data unit are either m or n (which are integral numbers and m>n), while using the same error correction encoder and decoder for the two modes, by inserting m-n bits of dummy data bits into the n-bit data so as to handle it as m-bit data during the processes of error correction encoding and decoding and eliminating from the error correction encoded data the dummy data and a redundant code of the error correction code formed by the dummy data so that the data transmission rate can be lowered.

Digital signal transmission apparatus

Abstract: A digital signal transmission apparatus in which a digital signal having a header block of a predetermined length is transmitted. The header comprises a synchronization signal and auxiliary data. The auxiliary data is made up of first data or second data and a redundant error detection code. The redundant code is formed so that syndrome patterns of the error detection code are different in order to distinguish the block in which the first data is contained as the auxiliary data on the reception side, from the block in which the second data is contained as the auxiliary data so that a plurality of headers having different contents can be distinguished on the reception side.

Digital computer code word identification system

Abstract: A digital computer system has a central processor unit (CPU). A computer program, entered into the digital computer system for execution thereof, has a program code word embedded at an arbitrary location therein. An addressable programmable array of logic (PAL) is operatively connected to the CPU for receiving a READ signal originated by the CPU at the address of the PAL, the PAL being programmed to output a portion of a preset array code word in a response to the READ signal, and to output the remainder of the array code word in segments in response to subsequent READ signals at the same address. A data bus, connected to receive and transmit the portion and remainders of the array code word to the CPU for comparison with the program code word. The program code word and the array code word are compared and, if identical permit use of the program and do not permit use when the program code word and the array code word are not identical.

Devices for the remote transmission of controls in security

Abstract: Devices for the remote transmission of controls in security constituted by a remote control device comprising a microprocessor equipped with EPROM and programmed in such a way to be suitable to code the output messages according to a fixed base code and a dynamic code, determined for any message performing a predetermined algorithm on the dinamic code employed in the previous transmitted message, and by a receiver connected to the means to control, comprising a microprocessor equipped with an EPROM and programmed in such a way to be suitable to check the code of the received messages on the ground of the same fixed base code of the remote control device and of the dynamic code, which it determines automatically performing the same algorithm of the remote control device on the stored dynamic code of the previous received message, and to transmit a control signal of the means to control after the positive comparison of the two codes of the input message with the base code and the new dynamic code, calculated by itself, taken toghether, being the base codes and part of the instructions for performing the algorithm, as the other instructions are comprised in the program, storable upon assembling of the devices in the EPROMs while the dynamic codes are stored and erased progressively during the various operations of the devices.

Method of software development

Abstract: A program data managing apparatus comprising memories for storing as program data a source code, technique data on a process for making the source code, and intention data on intention to make the source code; a link indicative of the mutual relationship between program data; a display for displaying the relationship between the program data using the link; a link provided to indicate the relationship between a newly developed source code and the original program data from which the new source code derives; and a display for displaying the source code developed stepwise by that link and the related program data.

A form feature oriented coding scheme

Abstract: A form feature oriented coding system for manufacturing planning is presented in this paper. The coding system automatically extracts a code from a part definition data file. The code has a chain-type structure and a variable code length. It contains both general part information and specific geometric description of a turned part. This code can serve as a key to retrieve further part information from the input data file.

Document decompressing system

Abstract: A code parser decodes coded compressed image information into an intermediate code. A code expander operating asynchronously relative to the code parser decompresses the compressed image information in accordance with such decoded information. A window register in the code parser has a length at least as long as the longest code in the intermediate code. When the intermediate code indicates a pattern in one line in a raster scan of an image corresponding to a pattern in an immediately preceding line, the window register and associated circuitry scan the one line and provide for the decompression in such line in accordance with the decompression at the corresponding positions in the preceding line. Such associated circuitry may include two memories, one for even scan lines and the other for odd scan lines. Alternate ones of the memories are activated for information comparison between adjacent lines during alternate line scans. When the same color is to be printed at a number of successive positions in a line, a counter is set to count such number in the expanded line. During this count, the same color is output. The code parser requests successive codes from an external source and acknowledges the receipt of such successive codes. The code expander receives new codes and expansion instructions from the code parser and acknowledges the receipt of such codes. Under certain circumstances, the code parser may not operate on the next code until the code expander has decompressed the information represented by the previous code.

Lempel-Ziv decoder

Abstract: A decoder for data encoded in a form combining a prefix which is a previously coded sub-string and a next data element in the data stream The decoder includes memories for storing code words and data separately Upon receipt of a code word the decoder stores the previously received code word, applies the newly received word to the code word memory to obtain the location of the last data element which is part of the data represented by the newly received code word, and another code word associated with the prefix Upon completion of decoding the latest code word, the first data element of the decoded word is appended to the next previously received code word, and the combination is stored as the equivalent of a code word which is next after the highest code word already received At least one memory is shared for use during encoding and decoding

Using an architectural knowledge base to generate code for parallel computers

Abstract: Code generation for existing parallel computers involves partitioning the work into schedulable units, assigning the resulting computational units to specific processors, and generating the code for interprocessor communication and synchronization. The options for partitioning and mapping depend in detail on the problem being solved and the algorithm and architecture being used. For each new combination of problem, algorithm, and architecture, a new partitioning and mapping must be created and evaluated based on the actual communication costs incurred. If a particular choice of partition and map is found to be too inefficient when the communication cost is analyzed, it is usually necessary to repeat the code generation process from the beginning.Given the complexity of this problem, it is not practical to develop a general algorithmic approach. A more promising approach is to develop restricted code generation strategies which are suitable for a class of problems and architectures, and compilers which use heuristic advice to guide code generation.In this paper we present a compiler for distributed memory parallel computers which perform automatic program partitioning, mapping and communication code generation under the guidance of a strategy rule-base. All partitioning and mapping is performed automatically, and communication primitives are generated. We describe the compiler system and present an example code generation strategy for iterative elliptic partial differential equation solvers.

Central processor condition code method and apparatus

Abstract: A method and apparatus is disclosed for control of a central processor in response to a branch instruction using two separate, subsequently updated condition codes. Computer architecture is provided wherein the condition codes which determine the processor state result from the execution of instructions prior to the currently executing instruction. When the preceding instructions are executed, condition codes are set and maintained in a first condition code register. The first condition code is transferred to the second condition code register, and the first condition code register is updated to reflect the result of the current instruction execution. Any condition code state such as a branch used by the third instruction is based on the condition code state maintained in the second condition code register. The processor is provided with code which compiled according to the present invention, provides improved processor performance by reducing delays in instruction execution. If the current instruction is a condition code dependant instruction such as a branch instruction, this third instruction will execute based on the condition code maintained in the second condition code register.

Encoding/decoding system for optical recording/reading

Abstract: A system for encoding/decoding an 8-bit binary code into/from a 4/11 channel code is disposed such that an 8-bit binary code is encoded into a 11-bit channel code by adding a 3-bit extension code as a parity code which keeps the number of "1"s in the channel code at four. When the 8-bit binary code cannot be encoded by this rule, it is converted to a temporary 8-bit code by a table encoder and then a 3-bit extension code is added. The 4/11 channel code is decoded referring to the 3-bit extension code, which indicates the encoding rule by which the 4/11 channel code has been generated. When the 4/11 channel code is detected to have been encoded by the bits-adding rule, an original 8-bit binary code is derived from the 4/11 code by removing the 3-bit extension code. When the 4/11 channel code has been encoded by the table-encoding rule, it is decoded by a table decoder.

Inter-module code analysis techniques for software maintenance

Abstract: The research described in this thesis addresses itself to the problem of maintaining large, undocumented systems written in languages that contain a module construct. Emphasis is placed on developing techniques for analysing the code of these systems, thereby helping a maintenance programmer to understand a system. Techniques for improving the structure of a system are presented. These techniques help make the code of a system easier to understand. All the code analysis techniques described in this thesis involve reasoning with, and manipulating, graphical representations of a system. To help with these graph manipulations, a set of graph operations are developed that allow a maintenance programmer to combine graphs to create a bigger graph, and to extract subgraphs from a given graph that satisfy specified constraints. A relational database schema is developed to represent the information needed for inter-module code analysis. Pointers are given as to how this database can be used for inter-module code analysis.

A definition optimization technique used in a code translation algorithm

Abstract: Data flow analysis is used to optimize variable definitions in a program that translates microprocessor object code to a higher order language.

Programmable controller with stored tokenized source code

Abstract: A programmable controller executes a compiled version of a ladder diagram type control program to control the functions of a piece of equipment. The compiled program includes not only the machine language instructions but also a tokenized version of the source code which was used to generate various portions of the machine language instructions that cannot be easily used to regenerate the source code and ladder diagram. This facilitates the editing of the program as the original ladder diagram may be recreated from a com-bination of the object code and a tokenized version of the source code.

A source code documentation system for Ada

Abstract: The chief virtues of the Web system are that it encourages consistency between code and documentatio n and it supports the production of high-quality typeset documentation in a uniform style . With Web th e source code and documentation of a program are combined in a single file . There are two programs, Weav e and Tangle, which produce Tl typesetting commands and compilable source code, respectively, from the Web file . Since Tangle automatically organizes the code fragments into a compilable order as it extract s them from the Web file, the author is freed of syntactic constraints imposed by the programming language , and can structure the Web file in a way that makes the final typeset documentation most readable . Anyon e who has attempted to typeset computer program code manually and maintain consistency between sourc e code and typeset documentation for succesive versions of a program will readily appreciate these virtues .

Reference manual for the LIFE2 computer code

Abstract: LIFE2 is a PC-compatible computer code that analyzes the service lifetime of a WECS component. The LIFE2 code is written in Fortran and has the option of using either a fatigue analysis or a linear fracture mechanics analysis. This document contains information on what the code expects as input and what can be expected as output from the code. Also included are two example problems. 11 refs., 9 figs., 1 tab.

Parallel Processing a Three-Dimensional Free-Lagrange Code: a Case History

Abstract: A three-dimensional, time-dependent free-Lagrange hy drodynamics code has been multitasked and autotasked on a CRAY X-MP/416. The multitasking was done by using the Los Alamos Multitasking Control Library, which is a superset of the CRAY multitasking library. Autotasking is done by using constructs which are only comment cards if the source code is not run through a preprocessor. The three-dimensional algorithm has pre sented a number of problems that simpler algorithms, such as those for one-dimensional hydrodynamics, did not exhibit. Problems in converting the serial code, orig inally written for a CRAY-1, to a multitasking code are discussed. Autotasking of a rewritten version of the code is discussed. Timing results for subroutines and hot spots in the serial code are presented and suggestions for additional tools and debugging aids are given. Theo retical speedup results obtained from Amdahl's law and actual speedup results obtained on a dedicated machine are presented. Suggestions for designing large parallel codes are given.

Parallelizing a large scientific code - methods, issues, and concerns

Abstract: Objectives of this study were to develop techniques and methods for effective analysis of large codes; to determine the feasibility of parallelizing an existing large scientific code; and to estimate potential speedups attainable, and associated tradeoffs in design complexity and work effort, if the code were parallelized by redesign for a distributed memory system (NCube, iPSC hypercube), or straight serial translation targetting a shared memory system (CRAY2, SEQUENT). MACH2, the code under study, is a 2-D magnetohydrodynamic (MHD) finite difference code used to simulate plasma flow switches and nuclear radiation. A taxonomy relating functional levels of a code to levels of parallelism is presented and used as a model for analyzing existing large codes. It is shown that although parallelizing lower level code segments (e.g. algorithms and loops) on shared memory systems is generally easier to accomplish, in some cases an entire large code is most easily parallelized at a high level; via domain and functional decomposition. Also a multi-decomposition scheme is introduced in which acceptable load balances can be achieved for functional decompositions and heterogeneous data partitionings.

Method for securing secret code data stored in a data memory, and circuitry for carrying out this method

Abstract: The invention relates to a method and circuitry for securing code data stored in a code data memory (1a) prior to analysis, in which the signals at the code data memory outputs provide an indication of the contents of the code data memory. According to the invention, a blocking circuit (4), controlled by a blocking logic circuit (9), is provided at the code data memory outputs, which it blocks as soon as entered control data fails to match the code data.

Program language translator

Abstract: PURPOSE: To shorten time required for source analysis, and to improve the efficiency of translation processing by executing the source analysis only for a corrected part at the time of the translation of a source program after correction. CONSTITUTION: After the correction of the source program, differential information 6 between the source program 4 before correction and the source program 5 after correction is delivered to a source analyzing means 1 by a hysteresis information control means 7. Then, a differential intermediate code 9 corresponding to the differential information 6 is substituted for a part corresponding to the corrected part of an intermediate code 8 before correction generated and preserved last time by the source analyzing means 1 by a substituting means 11. The substituted intermediate code 10 is delivered to a code generating means 3, and an object program 2 equivalent in a meaning to the source program 5 after correction is generated. Thus, when the source program is corrected and altered, since the source analysis is executed only for the corrected part, the source analysis need not be executed for the whole source program, and the processing time is shortened, and the processing efficiency is improved. COPYRIGHT: (C)1991,JPO&Japio

Code data control system

Abstract: PURPOSE: To execute retrieval easily without being restricted in terms of hardware on a screen by converting the code data into the image data, registering it in a storage means and dealing it as a document. CONSTITUTION: When the code data is registered in a reception spool file 1, a conversion processing A is started and the code data of the reception spool file 1 is converted from an EBCDIC code and an IBM KANJI (Chinese character) code into a JIS code showing characters such as corresponding alphabets and KANJI. Then, the JIS code is converted into the character image data presented by a concerned JIS code from the JIS code and the image data being a converted result are sequentially registered in an image information file 2. Then, the image data of an image information file 2 is transmitted to a document file system F and is registered in an optical disk 3 in a registration processing B. Thus, easy retrieval is executed without being restricted in terms of hardware on the screen. COPYRIGHT: (C)1991,JPO&Japio

Parallel processing a three-dimensional free-lagrange code

Abstract: A three-dimensional, time-dependent free-Lagrange hydrodynamics code has been multitasked and autotasked on a CRAY X-MP/416. The multitasking was done by using the Los Alamos Multitasking Control Library, which is a superset of the CRAY multitasking library. Autotasking is done by using constructs which are only comment cards if the source code is not run through a preprocessor. The three-dimensional algorithm has presented a number of problems that simpler algorithms, such as those for one-dimensional hydrodynamics, did not exhibit. Problems in converting the serial code, originally written for a CRAY-1, to a multitasking code are discussed. Autotasking of a rewritten version of the code is discussed. Timing results for subroutines and hot spots in the serial code are presented and suggestions for additional tools and debugging aids are given. Theoretical speedup results obtained from Amdahl's law and actual speedup results obtained on a dedicated machine are presented. Suggestions for designing large parallel codes are given.

Graphically-oriented linear analysis of plane frames subjected to complex loadings on microcomputers

Abstract: Computer program FRAME11 performs a linear elastic analysis of plane frames subjected to complex loading conditions Enhancements are made to an existing FORTRAN code using currently available hardware and software The original code runs on a minicomputer with alphanumeric terminals, while the enhanced version runs on a microcomputer with an improved user interface that includes panel-oriented input and extensive use of graphics Low level assembly language routines are written to provide functions for manipulating screens, and calls to a commercial software package provide functions for graphical capabilities The existing code is integrated with the new program as subroutines, but no other modifications are made to facilitate avoidance of new error sources Panel-oriented input eases the user's burden of creating and editing problems Graphical representation of input data allows error-checking before execution of the code In addition to the conventional numerical presentation, output data from analysis is also displayed graphically A menu structure controls access to various capabilities of the software package FORTRAN 77 is used as the primary language for new code development (A)