Showing papers on "Registered memory published in 1986"

Semiconductor integrated circuit with nonvolatile memory

Abstract: A semiconductor integrated circuit with a non-volatile memory has a plurality of nonvolatile data memory elements arranged in a matrix and a means for reading data from the memory elements in accordance with an address signal which specifies a position in the matrix. A protecting data memory element for storing at least one-bit protection data is disposed in the matrix. Whether operations such as programming (i.e., writing), erasing or reading with respect to the data memory elements will be allowed or inhibited is determined in accordance with the contents of the protecting data memory element. In other words, data security in an arbitrary area of the matrix can be accomplished based on the content of the protecting data memory element.

System for simulating memory arrays in a logic simulation machine

Abstract: A method and apparatus for simulating memory devices in a logic simulation machine include a finite state machine (FSM) having input/output (I/O) sources, instruction storage resources, a real memory resource, and instruction execution resources. A plurality of memory device ports to be simulated are defined and associated with corresponding respective subsets of the I/O resources of the FSM. Permutated sets of simulated memory array access signals, such as data, address, and control, are bound to selectable ones of the simulated memory ports and stored in the FSM, with the parameters of the memory operation established by the simulated signals. Stored sets of access instructions, representative of memory access operations, are augmented by the simulated signals and executed by the FSM against the real memory resource. All array instructions representing the same memory array share the same address space in the real memory resource.

Semiconductor memory device having serial writing scheme

Abstract: An improved semiconductor memory which can achieve high-speed data processing is disclosed. The memory comprises a memory array, a random access port for accessing a desired one of memory cell in accordance with row and column addresses, a serial read circuit for consecutively reading data from the selected row one by one and a serial write circuit for consecutively writing data to the selected row one by one without specific column address information.

Multiprocessor memory management method

Abstract: In a multiprocessor system (FIG. 1), memory (22) of each adjunct processor (11-12) comprises global memory (42) and local memory (41). All global memory is managed by a process manager (30) of host processor (10). Each processor's local memory is managed by its operating system kernel (31). Local memory comprises uncommitted memory (45) not allocated to any process and committed memory (46) allocated to processes. The process manager assigns processes to processors and satisfies their initial memory requirements through global memory allocations. Each kernel satisfies processes' dynamic memory allocation requests from uncommitted memory, and deallocated to uncommitted memory both memory that is dynamically requested to be deallocated and memory of terminating processes. Each processor's kernel and the process manager cooperate to transfer memory between global memory and uncommitted memory to keep the amount of uncommitted memory within a predetermined range.

Integrated circuit with memory self-test

Abstract: A memory array included with logic circuitry on an integrated circuit is tested by a technique that reads and writes a specified sequence of test bits into a given memory word before progressing to the next word. A checkerboard pattern of 1's and 0's is written into the physical memory locations. This provides for an improved worst-case test while allowing case of implementation for the test circuitry. The test results from a comparator circuit may be compressed to provide one (or a few) test flags indicating whether the memory passed the test, requiring a minimal number of test pads or terminals for the chip.

Semiconductor memory having error correcting means

Abstract: A semiconductor memory having an error correcting function is provided, which has a device by which the user finds no difficulty in making use of the semiconductor memory and can test it with ease In the semiconductor memory, a signal indicative of the completion of the preparation for reading/writing is outputted from the memory so that the user, after detecting the output of this signal, performs reading/writing data To facilitate tests, such as a memory cell test for a redundant bit (check bit), an encoding circuit test and a decoding circuit test, the present invention provides that the arranged tests can be made independently of each other

Memory system with operation error detection

Abstract: A memory system for a computer detects data errors, address errors and operation errors to increase the reliability of data stored in the memory system. Address errors are detected by encoding address parity information into the data check field of each memory location. A signal is generated in each memory module indicating the status of operations of that memory module and is transmitted to the processor subsystem of the computer for comparison with a signal indicating the status of operations of the processor subsystem to insure that all memory modules and the memory control in the processor are receiving the same commands.

Read in process memory apparatus

Abstract: A cache memory subsystem couples to main memory through interface circuits via a system bus in common with a plurality of central processing subsystems which have similar interface circuits. The cache memory subsystem includes multilevel directory memory and buffer memory pipeline stages shareable by at least a pair of processing units. A read in process (RIP) memory associated with the buffer memory stage is set to a predetermined state in response to each read request which produces a miss condition to identify the buffer memory location of a specific level in the buffer memory which has been preallocated. The contents of the buffer memory stage are maintained coherent with main memory by updating its contents in response to write requests applied to the system bus by other subsystems. Upon detecting the receipt of data prior to the receipt of the requested data which would make the buffer memory contents incoherent, the cache switches the state of control means associated with the RIP memory. Upon receipt of the requested data, the directory memory is accessed, the RIP memory is reset and the latest data is forwarded to the requesting processing unit as a function of the state of the control means.

Display apparatus having an image memory controller utilizing a barrel shifter and a mask controller preparing data to be written into an image memory

Abstract: A data processing apparatus for image display includes a character generator, a bit map type image memory, a CPU for accessing the character generator and the image memory to control the data stored in the image memory, a display, and a display controller for reading out the data stored in the image memory in accordance with a command from the CPU and supplying the readout data to the display. The image display apparatus further includes an image memory controller having a barrel shifter for parallelly shifting the data supplied from the CPU by a designated number of bits, a mask controller for outputting a mask data to restrict a write range of the data supplied from the CPU and a write controller for operatively combining the data from the barrel shifter and the data read from the image memory in accordance with the mask data to prepare a write data and supplying the write data to the image memory.

A memory test apparatus

Abstract: To provide a memory test apparatus enabling to test a high-performance memory having two or more memory functions, the apparatus of the present invention includes a pattern generator (l5) for generating an algorithmic pattern to be inputted to a first memory block (2) having a first memory function of a memory under test (l) having at least two memory functions, an auxiliary pattern generator (l6) for storing an output (7) from the algorithmic pattern generator (l5) and for outputting an expected value (25) to a second memory block (3) having a second memory function of the memory (l) at a preset timing based on the stored output (7), a comparator (l7) for comparing outputs (l0, ll) from the first and second memory blocks (2, 3) with expected values for the memory functions, respectively, and a memory (20) for storing an output (27, 28) from the comparator (l7). Since algorithmic pattern generator (l5) and the auxiliary pattern generator (l6) are included, the present invention has such an effect that even if the first and second memory blocks (2, 3) of the memory under test (l) operate asynchronously, the data transfer function therebetween and the performance related to the operation timing can be tested and that a highly precise memory test apparatus can be provided.

Memory access buffering in multiprocessors

Abstract: In highly-pipelined machines, instructions and data are prefetched and buffered in both the processor and the cache. This is done to reduce the average memory access latency and to take advantage of memory interleaving. Lock-up free caches are designed to avoid processor blocking on a cache miss. Write buffers are often included in a pipelined machine to avoid processor waiting on writes. In a shared memory multiprocessor, there are more advantages in buffering memory requests, since each memory access has to traverse the memory- processor interconnection and has to compete with memory requests issued by different processors. Buffering, however, can cause logical problems in multiprocessors. These problems are aggravated if each processor has a private memory in which shared writable data may be present, such as in a cache-based system or in a system with a distributed global memory. In this paper, we analyze the benefits and problems associated with the buffering of memory requests in shared memory multiprocessors. We show that the logical problem of buffering is directly related to the problem of synchronization. A simple model is presented to evaluate the performance improvement resulting from buffering.

Image memory having standard dynamic RAM chips

Abstract: An image memory comprising a plurality of memory cell columns for memorizing image data, common word lines for connecting memory cells of these memory cell columns, a scanner for sequentially designating memory cells of the column on the basis of a clock signal, a column address counter for counting the clock signal to output a column address signal, a write column selector responsive to the column address signal to select a memory cell column into which image data is written, a write buffer for writing image data into the designated memory cell of the memory cell column selected by the write column selector, a read column selector for selecting a memory cell column different from the memory cell column selected by the write column selector, and a read buffer for reading image data from the designated memory cells of the memory cell column selected by the read column selector. The image memory is capable of performing write and read operations at the same time. For performing refresh operation simultaneously with read/write operation, a read/write/refresh selector may be provided instead of a read/write selector provided in the column address counter. Further, for realizing write and read operation at the same time even when a write clock signal is different from a read clock signal, the memory cell columns may be divided into a plurality of memory cell column groups, e.g., odd and even memory cell groups.

Arrangement for expanding memory capacity

Abstract: An expandable memory connected to a central processing unit includes several memory modules which transfer configuration signals serially to the central processing unit by way of an interface circuit. The interface circuit also selects ones of the memory modules for access by the central processing unit according to the configuration signals.

Technique for determining maximum physical memory present in a system and for detecting attempts to access nonexistent memory

Abstract: A method for determining the maximum amount of physical memory present in a data processing system that can be configured to have one or more memory modules where the memory modules may be one of several types having different amounts of memory locations. By having signals indicating the presence of a memory module and the module type directly available with minimal intervening logic, a diagnostic process can accurately determine the amount of memory present in the system and reduce the possibility of a failed memory module going undetected. A method is also descibed using these memory module present and module type signals for detecting an attempt by either the central processor or an input/output controller to access a memory location that is not physically present within the data processing system.

Programmable memory with memory cells programmed by addressing

Abstract: A programmable memory includes a memory matrix (34) with a row decode circuit (36) and a column decode circuit (48) operable in the program mode to select one of the memory elements in the memory matrix (34). A current boost circuit (50) is operable to provide increased current to the selected cell such that selection of the cell opens the fuse associated therewith to change the logic state. The pins associated with the column and row addresses have multiple mode functions such that in the normal operating mode they can be assigned other tasks and in the programming mode are utilized primarily for addressing of the memory cells.

A Pattern Recognition and Associative Memory Approach to Power System Security Assessment

Abstract: As the cost of computer memory continues to decline faster than that of processors, it may be realistic to effectively apply pattern recognition methodology to security evaluation of an electric power system. Efficient implementation techniques are developed to achieve assessment in real time with a modest level of memory requirement. The basic idea is to recognize the unknown security of a particular system state operation from stored knowledge about similar operating patterns. Two efficient data structures are proposed here for its implementation. First, a distributed memory device, an associative memory is developed for recognition. This particular memory is found to be capable of parallel pattern matching along with reduced computer storage. Second, for an efficient implementation of the memory structure, these associative memories are configured in a hierarchical structure which not only expands storage capacity but also utilizes the speed of tree search. This structure provides a basis of an error-free, rapid, and memory-saving recognition algorithm.

Display managing arrangement with a display memory divided into a matrix of memory blocks, each serving as a unit for display management

Abstract: In a display managing arrangement comprising a display memory and a display memory controller for accessing the display memory to display a selected area of an image datum with the selected area scrolled on the image datum or otherwise subjected to management, the display memory is divided into memory blocks arranged as an N-row M-column matrix. Each memory block is for use as a unit of the management and is divisible into memory elements arranged as an n-row m-column matrix. When the memory elements of the display memory are assigned with serial memory element addresses along each row of the memory elements of the display memory and then along a next column-wise downward row, the memory controller may access the memory elements of selected ones of the memory blocks in block parallel by specifying the serial memory element addresses for each memory block on the one hand from a least memory element address in the memory block under consideration consecutively to the serial memory element address which is equal to the least memory element address plus the number m less one. On the other hand, the serial memory element addresses are specified discretely along one of the m columns by adding products of a step value mM and multipliers variable from zero to the number n less one to one of the serial memory element addresses that is congruent with the least memory element address modulo the step value. On storing the selected area in the display memory, the image datum may likewise be accessed.

Computer system capable of interruption using special protection code for write interruption region of memory device

Abstract: A computer system capable of interruption using a special protection code for a write interruption region of a main memory, including a subsidiary memory connected with a central processor unit and the main memory. The subsidiary memory delivers a translated real address code and protection codes including ordinary protection codes and the special protection code. Checking of the special protection code in the special protection code check number is carried out when the special protection code from the subsidiary memory is present and an access instruction from the central processor unit is a write instruction. Thereby, writing into a region beyond a stack region in the main memory is possible and the information of execution of the write interruption to the region beyond the stack region in the main memory is transmitted to the central processor unit.

Performance evaluation of vector accesses in parallel memories using a skewed storage scheme

Abstract: This paper presents and evaluates a scheme for reducing the average memory access time in a vector processing architecture. This scheme uses data skewing to distribute vectors among the modules of a parallel memory system in such a way that, for typical vector access patterns, the average number of memory conflicts is reduced. It also employs both address and data buffers in each module to smooth out the transient irregularities that occur in some vector access patterns.Most previous data skewing techniques were developed to provide conflict-free access for a limited set of access strides. While the proposed scheme does not eliminate all conflicts, it improves the average performance over non-skewed parallel memories by significantly reducing the number of conflicts for a wide range of strides. Also, this effect is much less dependent on the number of memory modules than the skewing schemes used to obtain conflict-free access.

Memory test circuit

Abstract: A memory test circuit in which test data is simultaneously written into plural memory cells of a semiconductor memory device and then subsequently read from the plural memory cells to assure reliable operation of the memory device. A logical sum and a logical product are formed of the test data read out from the plural memory cells. The logical product and the logical sum are subjected to an exclusive-or operation, the result of which is indicative of whether or not the test data was correctly written into the memory cells.

Buffer memory control system

Abstract: A buffer memory control system for executing an immediate instruction, including a block fetch control unit for generating a first move-in complete signal indicating that the move-in of the heading subblock from a main memory to the buffer memory is completed. In response to the first move-in complete signal, the fetch and store operation starts without waiting for the completion of the move-in of a full block.

Integrated electronic memory circuit with internal timing and operable in both latch-based and register-based systems

Abstract: An integrated electronic memory circuit is provided which includes memory circuitry for storing binary data in an array of memory locations; first data signal providing circuitry for providing input data signals to the memory circuitry, for storage by the memory circuitry as binary data at respective memory locations; and write signal generator circuitry for generating a write signal causing the memory circuitry to accept input data signals from the first data signal providing circuitry for storing in the array.

Integrated circuit memory with common address register and decoder

Abstract: An integrated circuit memory which can be applied, for example, to a memory device of a dialogue type tool information interface for an NC machine tool or a memory unit of various identification cards, comprises a fixed memory unit where necessary information is fixedly stored and the information cannot be rewritten, and a rewrite memory unit where necessary information among information of various sorts supplied from the interface or the card read/write apparatus can be rewritten if necessary, and the fixed memory unit and the rewrite memory unit are integrated in one chip or a single body of one module.

Modelling, measurement, and simulation of memory interference in the CRAY X-MP

Abstract: Memory interleaving and multiple access ports are the key to a high memory bandwidth in vector processing systems. Each of the active ports supports an independent access stream to memory among which access conflicts may arise. Such conflicts lead to a decrease in memory bandwidth and consequently to longer execution times. We present some analytical results regarding the access in vector mode to an interleaved memory system. In order to demonstrate the practical effects of our analytical results we have done time measurements of some simple vector loops on a 2-CPU, 16-bank CRAY X-MP. By corresponding simulations we obtained the number and type of memory conflicts that were encountered.

Postage meter with a non-volatile memory security circuit

Abstract: An electronic postage meter with a non-volatile memory security circuit apparatus is disclosed The security circuit comprises means for limiting the amount of time the memories may be continuously enabled, means for preventing simultaneous enabling of both memories and means for preventing the write enabling of a memory if the write enable signal is active before a memory select signal is active The circuit prevents memory access when a conflict is sensed across in an output related to the non-volatile memories The security circuit provides additional protection to the non-volatile memory so that valuable critical accounting information located therein cannot be modified or destroyed

Virtual Memory for the Sprite Operating System

Abstract: Sprite is an operating system being designed for a network of powerful personal workstations. A virtual memory system has been designed for Sprite that currently runs on the Sun architecture. This virtual memory system has several important features. First, it allows processes to share memory. Second, it allows all of the physical pages of memory to be in use at the same time; that is, no pool of free pages is required. Third, it performs remote paging. Finally, it speeds program startup by using free memory as a cache for recently-used programs.

On the use of registers vs. cache to minimize memory traffic

Abstract: Single-chip computers are becoming increasingly limited by the access constraints to off-chip memory To achieve high performance, the structure of on-chip memory must be appropriate, and it must be allocated effectively to minimize off-chip communication We report experiments that demonstrate that on-chip memory can be effective for local variable accesses For best use of the limited on-chip area, we suggest organizing memory as registers and argue that an effective register spilling scheme is required We introduce a heuristic algorithm for register spilling within basic blocks and demonstrate that trace optimization techniques can extend the use of the algorithm to global allocation Through trace simulation, we show that the use of registers can be more effective in reducing the bus traffic than cache memory of the same size

High speed intelligent distributed control memory system

Abstract: A highspeed, intelligent, distributed control memory system is comprised of an array of modular, cascadable, integrated circuit devices, hereinafter referred to as "memory elements." Each memory element is further comprised of storage means, programmable on board processing ("distributed control") means and means for interfacing with both the host system and the other memory elements in the array utilizing a single shared bus. Each memory element of the array is capable of transferring (reading or writing) data between adjacent memory elements once per clock cycle. In addition, each memory element is capable of broadcasting data to all memory elements of the array once per clock cycle. This ability to asynchronously transfer data between the memory elements at the clock rate, using the distributed control, facilitates unburdening host system hardware and software from tasks more efficiently performed by the distributed control. As a result, the memory itself can, for example, perform such tasks as sorting and searching, even across memory element boundaries, in a manner which conserves, is faster and more efficient then using, host system resources.

Semiconductor memory including a selectively disabled redunancy circuit

Abstract: A semiconductor memory device comprises a main memory 101 and a spare memory 102. When a part of the memory cells of the main memory 101 are defective, these defective memory cells are replaced by memory cells in the spare memory 102. The space memory 102 is decoded by the decoder circuit 104. The decoder circuit 104 is capable of decoding the spare memory 102 using a signal of an instruction memory 107. The instruction memory 107 is selectively enabled or disabled by an instruction control circuit 108. Consequently, in a state in which the instruction memory 107 is disabled by the control circuit 108, a spare memory selection signal is not provided from the instruction memory 107 to the decoder circuit 104 and the semiconductor memory device normally decodes the main memory including defective memory cells. As a result, the addresses and the like of the defective memory cells can be determined.

Semiconductor memory equipped with test circuit for testing data holding characteristic during data programming period

Abstract: An electrically programmable read only memory including a plurality of memory cells each composed of a field effect transistor having a floating gate is disclosed. The memory is featured by a test circuit which has a first circuit responding to a first control signal to raise all word lines up to a programming voltage and a second circuit responding to a second control signal to raise all digit lines up to the programming voltage. It is thereby detected whether or not electrons injected into the floating gate of the programmed memory cell are carried away during a data programming operation period.