Showing papers on "Registered memory published in 1998"

Power control system for synchronous memory device

Abstract: A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.

Low latency shared memory switch architecture

Abstract: A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.

Memory controller supporting DRAM circuits with different operating speeds

Abstract: A computer system including synchronous dynamic random access memory (SDRAM) circuits that are capable of operating at different frequencies. A memory controller generates multiple clock signals with appropriate frequencies for use by the SDRAM memory devices. Asynchronous data queues are used to provide data transfers between the SDRAM memory and the processor or other bus master devices residing on a peripheral bus. Upon initialization, the computer system determines the type of SDRAM devices present and provides status information to the memory controller which, in response, generates appropriate clock signals to the SDRAM memory circuits.

Phantom resource memory address mapping system

Abstract: A phantom-resource memory address mapping system reduces access latency in a memory configured as a stacked-hybrid or filly-interleaved hierarchy of memory resources. The address mapping system comprises memory access circuitry having a topology that combines an interleaved-based translation function in parallel with a stacked-based translation operation. The translation functions operate in conjunction with a phantom-resource memory mapping technique. The memory address mapping system reduces the latency incurred when accessing data in response to a memory reference address, while allowing flexibility with respect to the sizes and amounts of memory resources (e.g., modules, arrays and banks) that may be populated in a data processing system.

Circuits, system, and methods for processing multiple data streams

Abstract: An audio information processing subsystem (200) is disclosed which includes a stream processor (100) for simultaneously processing multiple streams of audio data. Processing subsystem (200) also includes a program memory (202) coupled to stream processor (100) for storing instructions for controlling processing system (200) and a data memory (203/204) also coupled to stream processor (100). Additionally, a direct memory access circuitry (208) is provided for controlling direct memory accesses to a selected one of program memory (202) and data memory (203/204).

Memory interface controller

Abstract: The present invention relates to a memory interface controller for a data transmission system. A memory interface controller is capable of randomly accessing a memory using an associative memory and variably processing data using an extended memory. There is provided a memory interface controller which includes a control logic unit for selectively outputting signals; a comparand register for storing a sequence number; an associative memory for outputting a match address; a priority address encoder for outputting a priority match address; an external memory controller for outputting an empty address of the associative memory; an external tended memory controller for outputting a priority empty address; and an extended memory address and control signal generator for generating an address and a control signal (enable/read/write).

Memory system including a memory module having a memory module controller

Abstract: A system (300) that has a system memory controller (304) and memory module (306, 308). The memory modules (306, 308) include memory module controller (310, 316) coupled to the system memory controller (304) and a plurality of memory devices (312-315, 317-320) coupled to the memory module controllers (310, 316).

Microcontroller system having allocation circuitry to selectively allocate and/or hide portions of a program memory address space

Abstract: A microcontroller system has a first and a second block of non-volatile programmable memory and includes a program memory space allocation circuitry. In a first mode of operation, the first and second blocks of programmable memory are prevented from being written by commands external to the microcontroller system. In a second mode, however, the first and second blocks of programmable memory are prevented from being written by commands external to the microcontroller system but the second block of programmable memory can be written based upon execution of commands stored in the first block of programmable memory. By having circuitry to so allocate the programmable memories, the security of the programmable memories is enhanced.

Non-volatile data storage unit and method of controlling same

Abstract: A non-volatile data storage unit having a data input and a volatile memory device for storing data. The volatile memory device is preferably a latch circuit made up of a pair of cross-coupled inverter circuits which store the data in complementary form. A non-volatile memory device, such as a pair of flash memory cells, is included which also store data in complementary form. Control circuitry is provided for controlling the operation of the data storage unit, including circuitry for transferring data from the data input to the volatile memory device and circuitry for programming the non-volatile memory device with data from the volatile memory device. The storage unit also preferably includes circuitry for transferring data stored in the non-volatile memory device to the volatile memory device, with such transfer typically taking place after an interruption of power to the storage unit.

Nonvolatile semiconductor memory device with soft-programming to adjust erased state of memory cells

Abstract: A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data "0" can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

Method and system for managing a display image in compressed and uncompressed blocks

Abstract: A virtual frame buffer controller in a computer's display system manages accesses to a display image stored in discrete compressed and uncompressed blocks distributed in physical memory. The controller maps conventional linear pixel addresses of a virtual frame buffer to pixel locations within blocks stored at arbitrary places in physical memory. The virtual frame buffer controller maintains a data structure, called a pointer list, to keep track of the physical memory location and compression state of each block of pixels in the virtual frame buffer. The virtual frame buffer controller initiates a decompression process to decompress a block when a pixel request maps to a pixel in a compressed block. The block remains decompressed until physical memory needs to be reclaimed to free up memory. A software driver for the virtual frame buffer controller performs memory management functions, including adding to a free memory list when the virtual frame buffer requires more memory and reclaiming memory previously allocated to a block of pixels whose state has changed from a compressed to an uncompressed state, or from a decompressed back to a compressed state.

Memory module system having multiple memory modules

Abstract: There are provided a memory controller, a plurality of memory modules, and an external data bus common to the plurality of memory modules. The plurality of memory modules each include a plurality of memory chips, a plurality of internal data buses connected between a corresponding memory chip and an input/output terminal, a logic chip, and a plurality of switch transistors each connected between a corresponding internal data bus and a corresponding input/output terminal to turn on/off in response to a control signal from the logic chip. The plurality of switch transistors in a memory module selected by the memory controller are turned on, and the plurality of switch transistors in the memory modules other than the selected memory module are turned off. Thus, the capacity of the memory modules may be increased while maintaining high-speed data transfer.

Stackable memory card

Abstract: A memory card design which allows for stackable memory cards so that a computer system's memory capabilities can be expanded by connecting a first memory card to sockets of the computer system's motherboard and then stacking subsequent memory cards on top of this first memory card. The memory card design includes connector sockets on a top surface of the card which allow for another card to be plugged into these sockets. Also, a presence detect serial EPROM and steer and encode logic are provided to assign a unique system address to each presence detect. The serial presence detect address select wiring are offset within the stack as are RAS lines so that all lines do not have to be hard-wired through each card of a stack of the present invention.

Methods and apparatus for dual-boot memory selection, update, and recovery in a programmable device

Abstract: Methods and associated apparatus for using a dual-boot capable programmable device and for updating programmed information in such a dual-boot capable programmable device. The apparatus of the present invention includes a primary boot memory device (108), a secondary boot memory device (110), and means for selecting between the two memory devices for purposes of "booting" the dual-boot mode device (100, 114..122). In particular, a reset switch (122) of the apparatus of the present invention resets devices in the dual-boot capable programmable device and is coupled to a selection device (114..120). The selection device (114..120) multiplexes signals from the two boot memory devices onto the corresponding bus signals of the dual-boot capable programmable device. When a "long" reset switch activation is sensed (118), the selection device selects a first of the two boot memory devices for coupling to the programmable device. A "short" activation (120) of the reset switch selects the other boot memory device. The present invention also includes methods (200..214, 400..410) for updating the contents of the two boot memory devices so as to avoid an inoperable state encountered due to failure of the update process in a single boot memory device. In particular, both boot memory devices are updated in sequence. The second memory update (206..214) is prevented if the first memory update (200..202) is determined to have failed (204).

Method and apparatus for implementing multiple memory buses on a memory module

Abstract: A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.

Using FET switches for large memory arrays

Abstract: The present invention discloses a method and apparatus for interfacing a memory array to a memory controller using a field-effect transistor (FET) switch. The memory controller has a bus which comprises a plurality of signal lines. The memory array is coupled to the memory controller. The memory array is divided into N groups of memory devices; each group has K memory devices. K memory devices in each of the N groups share memory signal lines. The FET switch couples the bus to one of the N groups of the shared memory signal lines at different times in response to a switch control indication.

Method and apparatus for testing an integrated memory device

Abstract: A method of memory array testing that detects defects which are sensitive to environmental conditions. A repair signature is generated reflecting the repair state of the memory. A memory device is rejected if there is a change in the repair signature of the memory array over the operating range of the device. In one embodiment, an integrated circuit includes a memory array, spare memory elements for repairing defective locations of the memory array, a built-in self-test (BIST) circuit for detecting faults in the memory array, a built-in self-repair (BISR) circuit for causing the failed memory location of the memory array to be replaced with a spare memory element, and a signature generator where the signature is based on a compression of addresses corresponding to failed memory locations, wherein the signature is used to determine that a repair result of the memory array is invariant over different environmental conditions.

Storage management system and auto-RAID transaction manager for coherent memory map across hot plug interface

Abstract: A storage management system for a Redundant Array of Independent Disks (RAID) data storage system and an AutoRAID memory transaction manager for a disk array controller are disclosed. The disk array controller enables a consistent, coherent memory image of the data storage space to all processors across hot-plug interfaces. To external processes seeking to read or write data, the memory image looks the same across the hot-plug interface. The disk array controller has two identical controllers, each with its own non-volatile memory, to maintain redundant images of disk array storage space. A hot-plug interface interconnects the two controllers. Each controller has an AutoRAID memory transaction manager that enables sharing of cyclic redundancy check (CRC)-protected memory transactions over the hot-plug interface between the two controllers. The AutoRAID memory transaction managers also have transaction queues which facilitate ordered execution of the memory transactions regardless of which controller originated the transactions. The AutoRAID transaction manager includes first and second bus interfaces, a mirror entity, and a local memory interface. Mirrored read and write transactions are handled atomically across the hot-plug interface.

Memory device and system including a low power interface

Abstract: A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure. The memory controller may be configured to apply control information to the interconnect structure as an encoded device identification word. The memory devices may each include a decoder for interpreting the encoded device identification word. The memory controller may be configured to apply a memory device selection signal to the interconnect structure to selectively enable the memory devices.

Method and apparatus for support of multiple memory devices in a single memory socket architecture

Abstract: An apparatus and method for supporting multiple types and configurations of random access memory devices in a single dual in line memory module (DIMM) socket architecture is provided. Typically, this architecture allows a user to select either SDRAM or EDO to be located in the socket(s) without substantially altering the connectivity between circuit components. A switching arrangement, that can be either active switches or fixed circuit traces, is used to selectively interconnect various control and addressing functions inherent in the microprocessor to appropriate pins of the memory device socket(s) depending upon whether EDO or SDRAM is used. In general, the address lines of the microprocessor are interconnected through a multiplexer and buffer arrangement that divides the address lines into two groups. The address bits are transmitted to the pin connections during each of the row address cycle and the column address cycle of the memory. The interconnections between the multiplexer/buffer and the random access memory are arranged so that a variety of standardized address pin configurations are supported by the same socket.

Memory allocation for long-running server applications

Abstract: Prior work on dynamic memory allocation has largely neglected long-running server applications, for example, web servers and mail servers. Their requirements differ from those of one-shot applications like compilers or text editors. We investigated how to build an allocator that is not only fast and memory efficient but also scales well on SMP machines. We found that it is not sufficient to focus on reducing lock contention - higher speedups require a reduction in cache misses and bus traffic. We then designed and prototyped a new allocator, called LKmalloc, targeted for both traditional applications and server applications. LKmalloc uses several subheaps, each one with a separate set of free lists and memory arena. A thread always allocates from the same subheap but can free a block belonging to any subheap. A thread is assigned to a subheap by hashing on its thread ID. WC compared its performance with several other allocators on a server-like, simulated workload and found that it indeed scales well and is quite fast hut memory more efficiently.

Memory module controller for providing an interface between a system memory controller and a plurality of memory devices on a memory module

Abstract: A memory module controller for providing interface between a system memory controller and a plurality of memory devices on a memory module. The memory module includes first interface circuitry and control logic. The first interface circuitry is configured to receive from the system memory controller a first memory transaction in a first format. The control logic is coupled to the first interface circuitry and configured to convert the first memory transaction into a second memory transaction in a second format for the plurality of memory devices. The second format of the second memory transaction is different than the first format of the first memory transaction.

Apparatus and method for updating ROM without removing it from circuit board

Abstract: An updater device for flash read-only memory is provided. The updater device may be constructed using a power input interface that transfers battery from either a battery or an electrical adapter to the updater device. The updater device has a body containing circuitry that controls the operations of the device. Located in the body is an input, or first, port and an output, or second, port for engaging flash read-only memories. A source flash read-only memory is inserted into the input port and the updater is then placed over the target flash read-only memory so that the updater device engages the target flash memory. A button that is located on the body activates the updating process. First the microprocessor reads data from the source flash read-only memory via a first read-only memory interface located in the input port. Then the microprocessor uses a second read-only memory interface in the second port to erase the target read-only memory. Next, the microprocessor encodes the data read from the source flash memory onto the target flash memory. Before ending the updating process, the updater device confirms that the data encoded on the target flash read-only memory matches that previously read from the source flash read-only memory. During the updating process, the target flash memory is not removed from the attached printed circuit board. Light emitting diodes are attached to the body of the updater device to indicate the status of the updating process. After the newly encoded data on the target flash memory is confirmed a light emitting diode is activated to inform the user whether the target flash memory was properly encoded.

Method and apparatus for updating flash memory resident firmware through a standard disk drive interface

Abstract: A method for updating the content of EEPROM memory used for controlling processes run on a microprocessor used to control the operations of a long term memory array which includes moving an update process stored in the EEPROM memory to a random access memory associated with the microprocessor; and then using the update process stored in random access memory for erasing the contents of the EEPROM memory, and furnishing data to the microprocessor on a sector by sector basis from a host computer through an interface used by the microprocessor to provide data to the long term memory array. The data furnished by the host is written sector by sector to the EEPROM memory until the EEPROM memory has been updated.

Memory simulation system and method

Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. The Memory Mapping aspect of the invention provides a structure and scheme where the numerous memory blocks associated with the user's design is mapped into the SRAM memory devices in the Simulation system instead of inside the logic devices, which are used to configure and model the user's design. The Memory Mapping or Memory Simulation system includes a memory state machine, an evaluation state machine, and their associated logic to control and interface with: (1) the main computing system and its associated memory system, (2) the SRAM memory devices coupled to the FPGA buses in the Simulation system, and (3) the FPGA logic devices which contain the configured and programmed user design that is being debugged.

Method of processing memory requests in a pipelined memory controller

Abstract: A method for processing multiple memory requests in a pipeline. Each memory request is processed in part by a plurality of stages. In a first stage, the memory request is decoded. In a second stage, the address information for the memory request is processed. In a third stage, the data for the memory request is transferred. A request buffer is used to hold each of the memory requests during the processing of each of the memory requests.

Method and apparatus for implementing a serial memory architecture

Abstract: A serial memory architecture. A memory subsystem includes a bus and a first memory module coupled to the bus. The first memory module has a first connector to receive bus signals from the bus and a second connector to output the bus signals. A second memory module has a first connector to receive the bus signals from the second connector of the first memory module. The bus signals are thereby routed through the memory modules in a serial manner. In one embodiment the memory modules include one or more 90° routing paths between connectors and the devices of the memory modules. In one embodiment, trace lengths are matched.

Memory controller for interchanging memory against memory error in interleave memory system

Abstract: In a memory system having a plurality of banks which forms interleave groups for independently forming an interleave, when a memory error is detected in an operating system resident space, the group having the error is interchanged with another group that has not had any error yet. After a group interchange, a page having the error is also deallocated. When a determination is made that the group interchange causes deterioration of performance, a bank deallocation can be also executed. As this criterion for determination, it is possible to employ a policy that a bank is deallocated when a capacity of a bank including an erroneous sub-bank is equal to or less than a predetermined rate of all the memory capacity and an interleaving factor is less than the interleaving factor of an interchange partner after the bank deallocation.

SIMM/DIMM memory module

Abstract: A memory module configured such that it can be operated as a first memory module such as a (Single In-line Memory Module) SIMM or as a second memory module such as a (Dual In-linc Memory Module) DIMM module without requiring external switching circuitry. This is accomplished by providing a memory module card with a circuit thereon that is designed to emulate a DIMM module when plugged into a DIMM socket as found in the latest computer architectures and to emulate a SIMM module when plugged into a SIMM socket as found in older computer architectures. The memory module is provided with memory devices (DRAMS or SDRAMS) and interconnecting bypass devices (CMOS transistor pairs) mounted thereon. The bypass devices and are also connected to terminal pads adjacent the first and second edges of the module, such that upon insertion of a first edge into a mating DIMM socket, the bypass devices are activated to interconnect the memory devices as, for example, a 1 bank 168 pin DIMM and upon insertion of the second edge into a SIMM socket, the memory devices are interconnected as, for example, a 2 bank 72 pin SIMM. The present invention decreases the need for manufacturing and maintaining separate SIMM and DIMM inventories and provides the capability of extending and expanding existing computer systems if the memory modules or cards originally designed for the computer are deleted from future inventories or become prohibitively expensive or difficult to locate.

High performance cost optimized memory with delayed memory writes

Abstract: A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.