Showing papers on "Residue number system published in 1996"

An efficient tree architecture for modulo 2 n + 1 multiplication

Abstract: Modulo 2n+1 multiplication plays an important role in the Fermat number transform and residue number systems; the diminished-1 representation of numbers has been found most suitable for representing the elements of the rings. Existing algorithms for modulo (2n+1) multiplication either use recursive modulo (2n+1) addition, or a regular binary multiplication integrated with the modulo reduction operation. Although most often adopted for largen, this latter approach requires conversions between the diminished-1 and binary representations. In this paper we propose a parallel fine-grained architecture, based on a Wallace tree, for modulo (2n+1) multiplication which does not require any conversions; the use of a Wallace tree considerably improves the speed of the multiplier. This new architecture exhibits an extremely modular structure with associated VLSI implementation advantages. The critical path delay and the hardware requirements of the new multiplier are similar to that of a correspondingn×n bit binary multiplier.

Sampled amplitude read channel employing a residue number system FIR filter in an adaptive equalizer and in interpolated timing recovery

Abstract: A sampled amplitude read channel is disclosed for disk storage systems which asynchronously samples an analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector. To increase the speed of the read channel, the FIR filters in the equalizer and interpolator are implemented according to a residue number system. Further, the residue number system implementation of the FIR filters uses "one-hot" encoding to decrease power dissipation.

A new residue arithmetic error correction scheme

Abstract: Automatic detection and correction of errors in the residue number system involves the conversion of residue representations to integers and base extension. The residue number system is generally restricted to moduli that are pairwise relatively prime. In this paper we consider error detection and correction using a moduli set with common factors. A method to construct a moduli set that leads to simplified error detection and correction is presented. Error detection can now be performed by computing residues in parallel. Error correction does not involve base extension any more. It is also shown that, removing all restrictions on the moduli set, leads to more complex error detection/correction algorithms.

A new algorithm for RNS decoding

Abstract: In this brief, a divide-and-conquer based RNS (residue number system) decoding algorithm is proposed. The basic idea of this algorithm is to decompose a set of moduli into groups each of size two moduli and to decode a given number in a two moduli representation. The time complexity of the algorithm used is O(log n), where n is the size of the moduli set. There is no assumption made on the elements of the module set. In addition, the algorithm requires less ROM size and smaller size module adders compared to those required by existing approaches.

A new Euclidean division algorithm for residue number systems

Abstract: We propose in this paper a new algorithm and architecture for performing divisions in residue number systems. Our algorithm is suitable for residue number systems with large moduli, with the aim of manipulating very large integers on a parallel computer or a special-purpose architecture. The two basic features of our algorithm are on one hand the use of a high-radix division method, and on the other hand the use of a floating-point arithmetic that should run in parallel with the modular arithmetic.

A new approach to fixed-coefficient inner product computation over finite rings

Abstract: Inherently parallel arithmetic based on the residue number system (RNS) lends itself very well to implementation of high-speed digital signal processing (DSP) hardware. In most cases, DSP computations can be decomposed to the inner product form Y=/spl Sigma//sub i=0//sup N-1/C/sub i/X/sub i/. Therefore, implementation of the inner product computation over finite rings is of paramount importance for RNS-based DSP hardware. Recently, periodic properties of residues of powers of 2 have been found useful in designing residue arithmetic circuits. This paper presents a deeper insight to the periodicity concepts by applying abstract algebra and number theory methods. Advantage is taken of the fact that the set Z/sub m//sup +/={1, 2, ..., m-1} splits completely, with respect to some g/spl isin/Z/sub m//sup +/, into sets which are closed under multiplication by g modulo m. Properties of such a decomposition of Z/sub m//sup +/ are investigated and the theory is applied to develop new fixed-coefficient inner product circuits for finite-ring arithmetic. The new designs are almost exclusively composed of full adders and they can easily be pipelined to achieve very high throughput. A VLSI implementation study of the new inner product circuits is presented. It shows that, compared with the best method known to date, both smaller area requirements and higher throughput are achieved.

Delay-power product simulation results for one-hot residue number system arithmetic circuits

Abstract: We present Spice simulations which verify previous analytical estimates of the delay-power product of One-Hot Residue adders and multipliers. These simulations show greater than a 50% reduction in the product below binary adders and an order of magnitude reduction for multipliers. Analytical models are derived from these results. They can be used to predict performance for larger moduli.

Superconducting single flux quantum circuits using the residue number system

Abstract: Superconducting single flux quantum (SFQ) circuits are promising for digital signal processing systems. However, conventional binary arithmetic does not take full advantage of the fundamental properties of SFQ circuits. The residue number system (RNS) is intrinsically more compatible with single flux quantum circuits, and provides the advantage of modularity, parallelism, carry-free structure, simple multiplication and fault tolerance. We designed a one-decimal-digit adder to demonstrate this new technology. The exclusive use of simple and robust Josephson shift registers creates large margins, simple circuit architecture and high throughput. These attributes are important for state-of-the-art superconducting technology, and are especially crucial for high temperature superconducting digital circuits. We designed, simulated and extensively optimized a mod 5 adder and its subcells. We laid out the circuits and had them fabricated. We tested the low speed functionality of these circuits using a manual test setup and a LabVIEW automated test setup. All the subcell experimental results show decent operation margins and good consistency with the simulation results, and demonstration of the entire mod 5 adder should be straightforward. An SFQ RNS 8-bit multiplier is proposed. Comparing to superconducting binary bit-serial and bit-parallel 8-bit multipliers, it shows an advantage in design simplicity, operation margins, error rate and throughput, along with its unique feature of simple fault tolerance. We thus believe that RNS, rather than binary, could be the natural language for superconducting digital electronics, especially in the application of digital signal processors.

Fixed point unsigned fractional representation in residue number system

Abstract: Representing fractions is one of the fundamental problems in the Residue Number System (RNS) which is considered an integer number system with no fractional representation. This is one of its main drawbacks and one of the main obstacles in its widespread. In this paper a method for representing fractions in RNS is developed. The addition of fractions is easily implemented using this method. The multiplication operation is also implemented, but of course with more sophisticated procedures relative to the addition operation. The choice of the way to represent a fraction in accordance with this new method is determined using two criteria, the Uniqueness Criterion (UC) and the Precision Criterion (PC). Real numbers representation is also introduced and analyzed. The general equation for real number multiplication which can be considered as the most difficult one in this paper, is introduced.

Computation of fixed-coefficient inner products over finite rings with the use of pass-transistor networks

Abstract: This paper presents new designs of fixed-coefficient inner product circuits for finite-ring arithmetic. These circuits are crucial for residue number system (RNS) based digital signal processing (DSP) systems, where computations can often be decomposed to the inner product form. The approach proposed is based on pass-transistor networks and one-hot data representation. Hardware complexity of the new circuits has been analyzed showing that substantial hardware savings can be achieved, compared to implementations based on the bit-sliced inner product step processor (BIPSP/sub m/). A low-cost double-edge-triggered data register has been developed for the new inner product circuits which can also be used in various other pipelined designs.

An adaptive image coder based on residue number system

Abstract: An efficient coder for adaptive lossy compression of still images is presented. It is based on a computational efficient extraction of the details of image blocks. The Discrete Cosine Transform and an efficient Lattice Vector Quantizer based on the Residue Number System are applied. The coder has a very regular and modular structure, has very low computational complexity, and provides a very efficient signal-to-noise ratio at low bit-rates. No blocking effects are introduced.

High-speed hardware algorithms for Chinese remainder theorem

Abstract: A residue number system (RNS) is one of the candidates for high-speed digital signal processing, because of its parallelism property with carry-free operation. However, RNS possesses a drawback that it requires time-consuming extra modules, binary to residue (B/R) and residue to binary (R/B) converters. To realize the R/B converter, the Chinese remainder theorem (CRT) are often employed. In hardware realization, the CRT can be reduced to multi-operand modular addition, which has usually been realized as several stages of carry propagate adder (CPA). In this paper, high-speed hardware algorithms for the CRT are proposed. We can reduce a number of CPA stage to one with carry save adders (CSA), and two methods, speed or size intensive versions are shown.

WSI oriented design for highly reliable systems based on the residue number system

Abstract: In WSI, a single noise could disrupt the system. However, neither dual system nor triple system can be used as a countermeasure because WSI benefits from the use of a single wafer system. This paper presents a design procedure for noise-tolerant systems in which multiple clock pulses and the features of the residue number system are effectively combined. The design sequence is as follows: (1) The system is designed based on the redundant residue number system. (2) The circuits corresponding to the digits of the residue number system are driven by the clock pulses, each of which has a different phase. (3) A circuit is applied which corrects the noise-induced error through calculation of the remaining correct digits. The reliability of a nonrecursive digital filter is clearly improved by applying the given method. The reliability is, however, reduced by pipelining and the hardware upgrade needed for redundancy is limited to 31%. By applying the given method, coincident noise-induced faults throughout the system are avoided and the redundant hardware is reduced. We have found the method suitable for noise-tolerant systems design of WSI.

RSA decryption using the one-hot residue number system

Abstract: The design of an RSA decryption circuit which uses the One-Hot Residue Number System is presented. Large modulus adders and multipliers are described which reduce the area of previous (barrel shifter-based) designs while preserving their low power and speed. An analytical estimate of the delay-power product of the decryption circuit is computed.

Fault-tolerant data transmission model based on redundant residue number system

Abstract: A fault-tolerant data transmission model based on the redundant residue number system is proposed in this paper It can transmit data correctly between two ends unless the residue errors exceed the error-correcting capability The expression for the probability of error is presented when the channel noise is additive Gaussian noise, and every branch is M-ary orthogonal signaling modulation The expression of the probabilities of undetected error and uncorrected error is also obtained when the RRNS system is single error-checking and single error-correcting model respectively The fault-tolerant data transmission model has not only the properties of parallel transmission but also the properties of series transmission© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering Downloading of the abstract is permitted for personal use only

High-speed custom VLSI DSP systems

Abstract: In this paper we examine the use of a recent innovation, called the logarithmic residue number system or LRNS, as an alternative to conventional DSP processors for implementing multiply-accumulate operations. We have fabricated a custom VLSI processor based upon this technology that is capable of providing substantial acceleration of vector arithmetic operations, convolution, correlation, and Fourier transforms in a relatively small, fast processor core when compared with implementations based on conventional arithmetic. The constituent arithmetic elements can be used as standard cells to implement application specific DSP designs.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Delta-sigma demodulator with large oversampling ratio using the one-hot residue number system

Abstract: A residue number system-based delta-sigma demodulator is presented which demonstrates a significant improvement in oversampling ratio in comparison with equivalent binary designs. The second order design employs a two-stage cascade architecture with two-level internal and four-level output quantization. Analytical estimates show at least a 60% improvement in OSR over binary number system-based designs. Furthermore, latency estimates for a pipelined version show a 70% decrease below binary. These benefits are made possible by the use of the one-hot residue number system, which allows addition and multiplication to be performed equally quickly and simply using barrel shifters and wire transposition. An example implementation of the design is also presented in an Altera 7256 CPLD.

Combinational logic approach for designing RNS multipliers

Abstract: The design of Residue Number System (RNS) multipliers has received considerable attention in the last few years. This paper presents a new approach for designing modular multipliers using a combinational logic technique. The idea is based on constructing a truth table whose inputs are the bits of the multiplicand and the multiplier. The outputs are the bits of the modular product. Realizing any minimized Boolean function is achieved using two levels of gates. Compared to most recent developed approach, our new technique requires less integrated circuit area and operates at a higher speed.

A residue number system implementation of real orthogonal transforms via approximation over a direct product of quadratic number rings

Abstract: Recent work has focused on doing residue computations that are quantization within a dense ring of integers in the real domain. The aims of the paper are to provide and efficient algorithm for approximation of the real input signal with arbitrarily small error as an element of a quadratic number ring, and to prove the restrictions of the RNS moduli used in order to simplify the multiplication in the ring. The proposed approximation scheme can be used for implementation of real-valued transforms and their multidimensional generalizations.

Choosing the system moduli of RNS arithmetic processors

Abstract: Designing an optimal residue number system (RNS) processor in terms of area and speed depends on the choice of the system moduli. In this paper an optimal algorithm for choosing the system moduli is presented. The algorithm takes into consideration several constraints imposed by the problem definition. The problem is formalized as an integer programming problem to optimize an area/time objective function.

Digital signal processing with digit-serial RNS arithmetic

Abstract: Although a great deal of attention has been given to residue number system (RNS) arithmetic in the digital-parallel form, little attention has been given to the digit-serial form. The digit serial form results in slower operating speeds, but it also provides many interesting and potentially useful properties due to the nonweighted properties of the RNS code. This paper discusses two particular scenarios where digit-serial RNS arithmetic is useful: (i) in variable word length sum-of-products processing, and (ii) in fault tolerant adaptive digital filtering based on combining digit-serial RNS arithmetic and a block LMS adaptive algorithm.