Showing papers on "Sampling (signal processing) published in 1989"

Digital subharmonic sampling down-converter

Abstract: A digital subharmonic sampling converter, for use in an analog IF signal demodulator and the like, includes: an analog-to-digital converter (ADC) means receiving the IF analog signal for conversion to a digital data stream by sampling at a sampling rate frequency substantially equal to 4/(2n+1) times the IF signal frequency, where n is an integer greater than zero. A digital mixer means is used to convert the sampled data to baseband. The interleaved sequential in-phase I data words and quadrature-phase Q data words are then sorted into a pair of concurrent I and Q data word streams.

Homodyne down-converter with digital Hilbert transform filtering

Abstract: A homodyne down-converter, for use in an IF signal demodulator and the like, includes an analog-to-digital converter (ADC) which receives the IF analog signal for conversion to a digital data stream by sampling at a sampling rate frequency substantially equal to four times the IF signal frequency. A digital mixer controllably inverts the sampled data to convert the data to baseband, before a circuit removes the effects of DC offset in the analog IF signal applied to the ADC. A discrete Hilbert Transform filter is used for generating streams of sequential in-phase I' and quadrature-phase Q' data words, which are resampled to temporally align the two data word streams at a new data rate, thus effectively removing sample offset without the need for separate misalignment correction circuitry.

Method and circuitry for symbol timing and frequency offset estimation in time division multiple access radio systems

Abstract: In order to correctly demodulate a received sequential burst of symbols in a time division multiplexed/time division multiple access (TDM/TDMA) portable radio digital telephony communications system, proper timing of the sampling time in each received symbol of the burst is necessary. In addition, in order to compensate for component drift, an estimate of the frequency offset between transmitting and receiving units is also required. A method and circuitry for estimating symbol timing and frequency offset is disclosed in which the IF radio signal is sampled and digitized at a sampling rate which is sixteen times the symbol rate. The digitized samples are processed to obtain phase values. A one symbol delay is introduced and differential phase values derived, a differential phase value being derived for each of the sixteen sampling times per symbol. The differential values are collapsed into one quadrant in the phase plane and then expanded back to the full plane. For each of the sixteen sampling times, a separate vector sum is formed of the expanded and collapsed differential phase values over substantially the entire burst. Symbol timing is selected to be the particular one-of-the-sixteen sampling times at which the vector sum has the largest magnitude. Frequency offset is directly determined from the angle in the phase plane of that vector having the largest magnitude.

Perceptual transform coding of wideband stereo signals

Abstract: The author reports on the extension of the entropy-coded perceptual transform coder (ECPTC) to stereo signals. The stereo ECPTC exploits both the redundancy in the stereo signal and the effects of acoustic mixing in the listening environment in order to encode the stereo signal at a bit rate much less than twice that for a monophonic signal. This coder uses the perceptual threshold developed by the author (IEEE J. Selected Areas in Commun. vol.6, no.2, p.314-23, Feb. 1988) along with a noiseless compression scheme to provide a bit-rate reduction of approximately one third compared to that for two independent monophonic channels. Typical rates available from the coder are 64 kb/s for a 6.6-kHz bandwidth, 14-kHz sampling rate transparent monophonic channel, 128 kb/s for a 15-kHz bandwidth, 32-kHz sampling rate stereo channel with FM or better quality, and 192 kb/s for a 20-kHz bandwidth, 44.1-kHz sampling rate stereo channel with perceived quality equal to that of the original signal. The 64-kb/s, 128-kb/s, and 192-kb/s rates correspond to ISDN (integrated services digital network) 1B, 2B, and 3B rates respectively, suggesting applications within the ISDN framework. >

Digital ultrasound system with dynamic focus

Abstract: An ultrasound system for investigating a subject comprises a probe, a signal processing module, and an interconnecting cable. The probe includes an annular phased array transducer defining multiple signal processing channels. The signal processing module includes a controller, a transmitter, a receiver, delay circuitry, and a video section. Within the delay circuitry, each signal processing channel includes an inphase branch and a quadrature branch. Each branch includes an analog-to digital converter (ADC) and a delay first-in-first-out (FIFO) memory. Dynamically variable delays are implemented by varying the sampling and FIFO input rates relative to constant FIFO output rates. The variable clock rates are derived by switching between phase-staggered replicas of a master clock MCLK, which has a rate at the nominal center frequency of the ultrasound signal prior to sampling. The timing circuit used to derive the variable clock rate signal uses a focus FIFO to serve as a timing buffer between the variable clock rate signal and the master clock signal. Inphase data streams from each channel are combined in a pipelined adder; quadrature data streams are similarly combined. An interpolator permits accurate combinations of the summed inphase and quadrature data streams. The resulting combination is directed to the video section for output. Advantages of the disclosed system include low signal processing, memory and data rate requirements, resulting in a more reliable and economical high-performance ultrasound system.

Method and apparatus for determining the error rate of magnetic recording disk drives having a amplitude sampling data detection

Abstract: In a disk drive providing amplitude sampling data detection, the amplitude of an analog read back signal is sampled at data clock intervals. The resulting analog values are converted to digital equivalent values. The digital equivalent values are each compared to an expected digital values that is representative of the data that was originally recorded on the disk, to thereby generate a different value. The resulting collection of difference values are magnitude segregated, and then stored in a plurality of registers, for later use in providing a histogram that is a measure of the disk drive's read error rate.

Digital to analogue converter adapted to select input sources based on a preselected algorithm once per cycle of a sampling signal

Abstract: An n-bit DAC of the kind having at least 2 n -1 sources, typically current sources, especially for use in oversampling ADC's enables a resolution accuracy in excess of 18 bits by selecting the sources in a dynamic manner. A source selection circuit typically an at least 2 n -1 to 2 n -1 multiplexer, connected between the digital input lines and the DAC switches selects the sources based on a predetermined cyclic algorithm which converts DAC errors into noise and shifts the noise energy into unwanted parts of the spectrum.

Echo measurement arrangement

Abstract: A digital signal processor is provided with the facility to range and converge on each of a plurality of echoes occurring at respective locations along a communications line. Specifically, the digital signal processor is arranged to adaptively process samples of a signal that has been transmitted to the communications line correlated with samples of a signal that have been received from the communications line. In the processing of the samples, the digital signal processor separates and measures the magnitude of each echo that it converges on, beginning with a so-called near-end echo. In addition, the digital signal processor calculates the propagation delay of each echo that it converges on using the number of sampling intervals that have been processed in order to position the processor on the dispersion of that echo.

Combining continuous time and discrete time signal processing in a delta-sigma modulator

Abstract: An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which operates as a continuous time integrator. the second, third, and fourth integrator stages are discrete time or sampling integrators. The continuous time first integrator provides the required thermal noise characteristics of the loop filter while the discrete time integrator stages provide loop stability and transfer characteristics which are advantageous to the overall operation of the analog-to-digital modulator.

Phase-locked-loop circuit and bit-detection arrangement comprising such a phase-locked-loop circuit

Abstract: A digital phase-locked-loop circuit is provided for deriving from a sequence of samples (J1, . . . J20) of a band-limited data signal (Vt), the phase of the data signal at the sampling instants. The circuit includes a discrete-time oscillator 10 for generating a sequence of phase values (F2, . . . F20) which characterize a periodic signal (Vk1) having an amplitude which varies as a linear function of time between two constant limit values (E, -E). The frequency of the periodic signal (Vk1) characterized by the phase values is proportional to a control value (I). An interpolation circuit (2) derives from the samples (J1, . . . J20) the relative positions (tf/T) occupied by the detection-level crossings of the data signal (Vt) relative to the sampling instants. A phase detector (3) derives the difference (ΔF) between the actual phase of the data signal (Vt) and the phase as indicated by the phase values (F) from said relative positions (tf/T) and the phase values (F). The discrete-time oscillator (10) is controlled by a digital sequential filter (9) in such a way that the phase difference remains substantially zero.

High precision phase measurement using adaptive sampling

Abstract: The conventional phase measurement techniques introduce error in the phase when the input signals are distorted by harmonics. A novel technique, known as adaptive sampling, for high-precision phase measurement is introduced. A digital signal-processing approach is used in this technique. The maximum sampling rate required for this technique is h+2 samples/cycle of the input signals, i.e. (h+2)f sampless, where h, is the highest harmonic present in the signals and f is the fundamental frequency of the signals. This sampling rate is way below the Nyquist sampling rate (more than 2hf samples/s) when h is a large number. In the adaptive sampling technique the sampling rate is started from three samples/cycle and then is gradually increased until the phase is correctly measured. This phase measurement technique has been verified using synthesized signals. >

Individual identification apparatus

Abstract: An apparatus for identifying an individual includes a reader (7, 25) for reading the input image of a finger (9) of the individual and producing an image signal corresponding to the image of the finger, an adder (23) for adding the image signal output from the reader (7, 25) in a direction perpendicular to a longitudinal direction of the finger and outputting an addition signal, and a memory such as an IC card (33) for storing a previously registered addition signal output from the adder (23). A first signal obtained by regular sampling of the current addition signal from the adder (23) and a second signal obtained by corresponding sampling of the addition signal stored in the IC card (33) are used to generate a coarse position alignment. After the coarse position alignment, the actual current addition signal and the actual stored addition signal are used without sampling to generate a fine position alignment. The two addition signals are then compared to decide whether the finger image corresponds to that of an authorised person.

Digital video encoder

Abstract: A differential pulse code arrangement reduces the bit rate of a composite color video signal by sampling the video signal at a predetermined rate of m times the color sub-carrier frequency, predicting the present video signal sample from reconstructed past samples and forming signal representative of the prediction error in a first predictive loop. The bit rate is further reduced in a second predictive loop embedded in the first predictive loop by generating a signal predictive of the error signal and forming a signal corresponding to the difference between the error signal and the signal predictive thereof. The difference signal is quantized and encoded for transmission. The error signal is reconstructed by summing the quantized difference signal and the predicted error signal and the prediction of the error signal is formed responsive to the sequence of past reconstructed error signals. The m-1th video signal sample is then reconstructed by summing the reconstructed error signal and the signal predictive of the m-1th video sample and a signal predictive of the next occurring video sample is generated responsive to the sequence of past reconstructed video samples.

Real time displacement measurement in sinusoidal phase modulating interferometry

Abstract: A new signal processing system for real time displacement measurement in sinusoidal phase modulating interferometry is described. Although sinusoidal phase modulating interferometry is effective in measuring with high accuracy the displacement of an object, conventional signal processing takes a long time. In this method, detection of the object's displacement is easily achieved by sampling the interference signal at those times that satisfy certain conditions and by processing the sampled signals with electric circuits in real time. The delay time of this signal processing system is <45 μs.

Dilution extractive probe

Abstract: A dilution extractive probe assembly for sampling a gas stream in a stack is provided It includes a hollow tubular dilution probe having a first end for receiving a sample of the gas stream from the stack to be analyzed and a second end through which the sample is discharged after dilution A first filter is provided at the first end of the probe for filtering the sample gas it passes into the probe A critical orifice is located within the probe downstream of the first filter A first heater is provided for heating the first filter to maintain the sample at a temperature above the dew point of the sample gas A partial vacuum is created for drawing the sample through the filter and into the probe An eductor is located adjacent the second end of the probe for mixing the sample with a dilution gas A second heater for heating the eductor to maintain the sample gas at a temperature above its dew point as it passes through the eductor is provided

An algorithm for multirate sampling adaptive control

Abstract: A stable multirate sampling adaptive control algorithm is presented which enables the fast sampling rate to be applied in closed-loop feedback control. The sampling rate is only restricted by the time needed for the control law computation (as in the nonadaptive control case) plus the estimation error computation. The plant input and output are recorded prior to the currently obtained estimate and used to compute the coming estimate and controller coefficients. Thus, the computation is not dependent upon the inputs and outputs appearing during the updating process. The closed-loop system is shown to be stable. >

Baudrate timing recovery technique

Abstract: A digital pulse receiver is disclosed in which the transmitted signal is recovered from the received signal by using a decision feedback equalizer to estimate and then remove the intersymbol interference. A second decision feedback equalizer is used to estimate the timing of the sampling pulse. An optimum timing phase is derived by driving the sampling clock with a phase adjustment signal optimizing the amplitude of the sampling pulse relative to the next preceding pre-cursor pulse. The signal recovery decision feedback equalizer and the timing recovery decision feedback equalizer share the same tapped delay line to provide a fully digital pulse receiver operating at the baud rate to provide an optimum sampling phase.

A CMOS 40 MHz 8 b 105 mW two-step ADC

Abstract: To meet the demand for digital signal processing of wideband video signals, a 40-MHz, 8-b ADC (analog/digital converter) with 105-mW power consumption on a 4.88-mm/sup 2/ chip has been developed using a 1.4- mu m standard-cell CMOS process. To obtain 8-b fast conversion, the ADC uses a sample-and-hold comparator with an averaging feature for differential linearity for high-speed sampling and high-frequency inputs and an expanded fine comparison to increase conversion speed. The block diagram of the converter is shown together with two techniques employed to increase conversion speed. The DC linearity of the converter at a 40-MHz conversion rate is shown. The limit of differential linearity is less than +or-0.5 least significant bit for 8 b. The measured power consumption as a function of sampling frequency and supply voltage is also shown. For 40-MHz sampled at a supply voltage of 5 V, the power consumed is 105 mW. For 14.3-MHz sampling at 3.5 V, the consumption drop to 27 mW. >

Compensating for computational delay in digital equivalent of continuous control systems

Abstract: A computer-aided method to compensate for the computational delay in the digital equivalent of continuous control systems is presented. The objective is to obtain the transfer function of the digital controller so that the performance of the equivalent digital control system is as close to that of the existing continuous system as possible. This is done by matching the frequency response of the digital control system to that of the existing system with a minimum weighted mean-square error. A formula for computing the parameters of the digital controller is obtained as a result. The design method is illustrated with an example. >

Intrapulse radar receiver

Abstract: A microwave frequency detection receiver for receiving an incoming analog radar signal, converting the radar signal into digital form, and performing a table lookup algorithm for detecting frequency and amplitude of the incoming signal with respect to time. The table lookup algorithm is in the form of a three point best-fit sinusoidal approximation of frequency and amplitude for processing successive digital input signal samples processed in groups of three. Digital sampling of the input signal coupled with the novel table lookup algorithm results in detection of frequency and amplitude characteristics on an intrapulse basis.

Subband coding of digital audio signals without loss of quality

Abstract: A subband coding system for high quality digital audio signals is described. To achieve low bit rates at a high quality level, it exploits the simultaneous masking effect of the human ear. It is shown how this effect can be used in an adaptive bit-allocation scheme. The proposed approach has been applied in two coding systems, a complex system in which signal is split into 26 subbands, each approximately one third of an octave wide, and a simpler 20-band system. Both systems have been designed for coding stereophonic 16-bit compact disk signals with a sampling frequency of 44.1 kHz. With the 26-band system high-quality results can be obtained at bit rates of 220 kb/s. With the 20-band system, similar results can be obtained at bit rates of 360 kb/s. >

Apparatus for recording audio signals and video signals on a recording medium

Abstract: In an audio and video recording apparatus, a video signal is separated into a luminance signal and a chrominance signal. The luminance signal is separated into low frequency and high frequency components. The high frequency component signal is subjected to balanced modulation to be thereafter band-compressed by interleaving the lower side band thereof to the low frequency component. The chrominance signal is processed to be a line sequential color difference signal. An audio signal is sampled and encoded. The luminance signal, the color difference signal and the audio signal are subjected to time-axis compression multiplexing in one frame with a synchronizing signal, address signals and control signals. The multiplex signal is recorded on a recording medium.

High resolution measuring device for time difference

Abstract: A high resolution measuring device for measuring a time difference between continuous pulses wherein an averaging effect can be improved sufficiently. The device comprises an approximate measuring means (180) which measures a time difference between pulses, and a precision measuring means (220) which performs a precision measurement of the time difference. A reference signal generating means (100) of the precision measuring means generates a reference signal S having a different synchronism from a measurement signal, and a sampling means (200) samples the reference signal with pulses of the measurement signal. A phase detecting means (300) detects a phase difference of a sampled waveform formed by the sampling means, and a calculating processing means converts the phase difference detected by the phase detecting means into a time difference and calculates a time difference between the pulses from a measured value of the approximate measuring means and another measured value of said precision measuring means.

Apparatus for recording/reproducing digital video signals in both a standard mode and a long playing mode

Abstract: An apparatus for recording an reproducing a digital video signal is disclosed which includes n sampling circuits each for performing a sub-Nyquist sampling operation for the digital video signal in such a manner that the amount of data is reduced to one-n-th of an original amount (where n is a positive integer) and a pixel sampled by the sub-Nyquist sampling operation is not sampled by the remaining sampling circuits, recording/reproducing means for recording and reproducing information at all or part of pixels which are sampled by the n sampling circuits and a device for reconstructing the digital video signal from reproduced information at pixels with the aid of a synthesizing technique or interpolation technique.

Real-time equalization of A/D converter nonlinearities

Abstract: A report is presented on a design, implemented with current technology, of a real-time compensator circuit. The author demonstrates the feasibility of using the phase-plane approach for real-time equalization of analog nonlinearities in the digital domain. It is shown that such compensation schemes have the potential to improve performance by removing slew-rate-dependent errors in the critical sample-hold circuits in sampling A/D converters. Linearity, as measured by the SFDR (spurious-free dynamic range), improved by more than 2 b over most of the Nyquist bandwidth for a 12-b, 5-MSps state-of-the-art A/D converter. >

Spread spectrum communication system

Abstract: The spread spectrum digital communication system includes data input devices for generating digital information signals to be transmitted using radio signals. A chip stream generator converts the data bits into chip streams that are either complemented or not complemented via an exclusive-OR gate, depending on the data bits. A scrambler further randomizes the chip stream for transmission. The receiver includes a descrambler and a correlator or digital matched filter for detecting the data signal. A modified receiver includes a sampler for sampling the scrambled signal at a rate which is the multiple of the chip rate thereby eliminating any need for recovering the chip clock. Another modified version includes a receiver having means for generating multi-level signals indicating the quality of the probable detection.

Active load impedance control system for radio frequency power amplifiers

Abstract: An active load impedance control system for a radio frequency power amplifier comprising an amplification means for amplifying radio frequency signals and providing a forward signal, a control means responsive to the operating conditions of said amplification means, a correction signal means responsive to the control means for providing an amplitude, a sampling means and phase controlled corrective reflective signal and a combining means for combining said forward signal and said corrective reflective signal.

Mass flow gauge for flowing media with devices for determination of the Coriolis force

Abstract: In a Coriolis mass flow gauge, the signal from each sensor is digitized and converted into digital measuring values by one or more analog/digital converters operating with a specific digital sampling frequency. Then, using a microcomputer, each digital measuring value thus obtained is multiplied, on the one hand, with the sine value of the phase angle at the point of sampling of the alternating signal or another scanning signal with the same frequency as the alternating voltage signal, but phase-shifted against that signal and, on the other hand, with the corresponding cosine value. The sine-multiplication values thus obtained are summed over a predetermined time interval to form one Cartesian coordinate of a corresponding sum vector, whereas the cosine multiplication values thus obtained are summed over that time interval to form the other Cartesian coordinate of the sum vector, and from the Cartesian coordinates of the sum vectors of both lateral sensors, the measuring value describing the mass flow through the loop is calculated directly.

Signal processing circuit for a solid-state image pickup device

Abstract: A signal processing circuit of a solid-state imaging device having an image pickup section formed by plural solid-state image sensors (4) including a discrete pixel array is dis­closed. The solid state image sensor (4G) for green-color image pickup is arrayed in the image pickup section with a spatial shift equal to one half the pixel pitch from the solid-state image sensors (4R, 4B) for red-color image pickup and the solid-state image sensors for blue-color image pickup in accordance with the spatial pixel shifting method. An optical low pass filter (2, 3) having a cut-off frequency equal to fs is provided on the front surfaces of these solid-­state image sensors (4). The green-color image pickup output signal, the red-color image pickup output signal and the blue­-color image pickup output signal, produced at the solid-state image sensors (4) of the image pickup section, are subjected to A/D conversion, followed by phase processing with the sampling phases of the respective digital signals matched with one another, to produce high-quality image output signals having satisfactory modulation transfer function (MTF) charac­teristics and containing lesser amounts of aliasing com­ponents.

Videodisc reproducing apparatus

Abstract: A videodisc reproducing apparatus includes a pilot carrier extraction circuit for extracting a pilot carrier from a videodisc reproduced signal and a clock generating circuit. The clock generating circuit includes an analog/digital converter and a phase-locked loop oscillator for generating a sampling clock signal for the analog/digital converter, whereby the videodisc reproduced signal is converted into digital form in synchronism with the pilot carrier. A phase-shift circuit is provided for phase shifting the sampling clock signal and for applying a thus phase-shifted sampling clock signal to the analog/digital converter. A phase detecting circuit is provided for detecting a digital sampling phase of a synchronizing signal included in a MUSE signal of the videodisc reproduced signal which has been converted into digital form according to positional information in the synchronizing signal of the videodisc reproduced signal detected by a synchronizing signal detection circuit. The phase detecting circuit further detects whether the detected digital sampling phase is advanced or retarded with respect to a digital sampling phase of a specified normal MUSE signal. An up/down counter is provided for generating an address signal output according to an output of the phase detecting circuit to control the phase-shift circuit.