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Showing papers on "Serialization published in 1996"


Proceedings ArticleDOI
02 Dec 1996
TL;DR: It is shown that simple microarchitectural enhancements to a modern microprocessor implementation based on the PowerPC 620 that enable value prediction can effectively exploit value locality to collapse true dependences, reduce average result latency and provide performance gains of 4.5%-23% by exceeding the dataflow limit.
Abstract: For decades, the serialization constraints induced by true data dependences have been regarded as an absolute limit--the dataflow limit--on the parallel execution of serial programs. This paper proposes a new technique--value prediction--for exceeding that limit that allows data dependent instructions to issue and execute in parallel without violating program semantics. This technique is built on the concept of value locality, which describes the likelihood of the recurrence of a previously-seen value within a storage location inside a computer system. Value prediction consists of predicting entire 32- and 64-bit register values based on previously-seen values. We find that such register values being written by machine instructions are frequently predictable. Furthermore, we show that simple micro- architectural enhancements to a modern microprocessor implementation based on the PowerPC 620 that enable value prediction can effectively exploit value locality to collapse true dependences, reduce average result latency, and provide performance gains of 4.5%-23% (depending on machine model) by exceeding the dataflow limit.

526 citations


Patent
13 Dec 1996
TL;DR: In this paper, a system and a method for designing and constructing software components and systems by assembling them from independent parts which is compatible with and extends existing object models is described, including a terminal interface and a terminal mechanism for interfacing objects.
Abstract: A system and a method for designing and constructing software components and systems by assembling them from independent parts which is compatible with and extends existing object models. A terminal interface and a terminal mechanism for interfacing objects is included. The mechanism is independent from the actual type of interactions established through it and allows objects to invoke directly services of other objects. All objects in a given system implement and expose a terminal interface. A property interface and mechanism with hierarchical property names and ability to execute queries is also included. The mechanism can be used for parameterization and serialization of objects, as well as to provide structured storage. A new and advantageous type of software object, named parts, is defined. Parts are constructed through an abstract factory and implement a property interface and a terminal interface.

117 citations


Proceedings ArticleDOI
26 Feb 1996
TL;DR: It is shown how the replica control mechanism can be used to provide consistent, although potentially stale, views of data across many machines without expensive per-transaction synchronization.
Abstract: The Mariposa distributed data manager uses an economic model for managing the allocation of both storage objects and queries to servers. We present extensions to the economic model which support replica management, as well as our mechanisms for propagating updates among replicas. We show how our replica control mechanism can be used to provide consistent, although potentially stale, views of data across many machines without expensive per-transaction synchronization. We present a rule-based conflict resolution mechanism, which can be used to enhance traditional time-stamp serialization. We discuss the effects of our replica system on query processing for both read-only and read-write queries. We further demonstrate how the replication model and mechanisms naturally support name service in Mariposa.

102 citations


Journal ArticleDOI
01 Jun 1996
TL;DR: METU INteroperable Database System (MIND) is a multidatabase system that aims at achieving interoperability among heterogeneous, federated DBMSs.
Abstract: METU INteroperable Database System (MIND) is a multidatabase system that aims at achieving interoperability among heterogeneous, federated DBMSs. MIND architecture if based on OMG distributed object management model. It is implemented on top of a CORBA compliant ORB, namely, ObjectBroker. MIND provides users a single ODMG-93 compliant common data model, and a single global query language based on SQL. This makes it possible to incorporate both relational and object oriented databases into the system. Currently Oracle 7, Sybase and METU OODBMS (MOOD) have been incorporated into MIND. The main components of MIND are a global query processor, a global transaction manager, a schema integrator, interfaces to supported database systems and a user graphical interface.In MIND all local databases are encapsulated in a generic database object with a well defined single interface. This approach hides the differences between local databases from the rest of the system. The integration of export schemas is currently performed manually by using an object definition language (ODL) which is based on OMG's interface definition language. The DBA builds the integrated schema as a view over export schemas. the functionalities of ODL allow selection and restructuring of schema elements from existing local schemas.MIND global query optimizer aims at maximizing the parallel execution of the intersite joins of the global subqueries. Through MIND global transaction manager, the serializable execution of the global transactions are provided.

32 citations


Patent
12 Aug 1996
TL;DR: In this paper, the authors present a method and system that permits enhanced instruction dispatch efficiency in a superscalar processor system capable of fetching an application specified ordered sequence of scalar instructions and simultaneously dispatching a group of the instructions to a plurality of execution units on a nonsequential opportunistic basis.
Abstract: The method and system of the present invention permits enhanced instruction dispatch efficiency in a superscalar processor system capable of fetching an application specified ordered sequence of scalar instructions and simultaneously dispatching a group of the scalar instructions to a plurality of execution units on a nonsequential opportunistic basis. A group of scalar instructions fetched in an application specified ordered sequence on a nonsequential opportunistic basis is processed in the present invention. The present invention detects conditions requiring serialization during the processing. In response to a detection of a condition requiring serialization, processing of particular scalar instructions from the group of scalar instructions are selectively controlled, wherein at least a portion of the scalar instructions within the group of scalar instructions are thereafter processed in a serial fashion.

21 citations


Book ChapterDOI
01 Jan 1996
TL;DR: A new real-time optimistic concurrency control protocol, called OCC-DA, is proposed in which the number of transaction restarts is minimized by dynamically adjusting the serialization order of the conflicting transactions.
Abstract: In this paper, a new real-time optimistic concurrency control protocol, called OCC-DA, is proposed in which the number of transaction restarts is minimized by dynamically adjusting the serialization order of the conflicting transactions. Unlike other implementations of dynamic serialization order adjustment for optimistic schemes, it is no need to check and update the serialization orders while a transaction is still in its read phase. All checking is performed at the validation phase. This provides more freedom to adjust their serialization orders. Performance studies of our protocol has been carried out and the results confirm the believe that it is much better than the other real-time OCC protocols.

20 citations


Patent
07 Aug 1996
TL;DR: In this paper, a method and apparatus are disclosed for enabling a constraint without prohibiting updates to the constrained data during the validation portion of the enablement process. But the authors do not specify the constraints themselves.
Abstract: A method and apparatus are disclosed for enabling a constraint without prohibiting updates to the constrained data during the validation portion of the enablement process. A constraint is first enforced. While the constraint is being enforced, the pre-existing data are inspected to determine whether the constraint is valid. Because the constraint is in force for all changes to the data during the validation process, the constraint will be enabled if the pre-existing data conforms with the constraint. A serialization value is stored in the constraint definition. Whenever the constraint definition is changed, the serialization value is changed. The serialization value of a constraint definition is recorded before validating the constraint. After validating the constraint, the serialization value in the constraint definition is compared to the recorded serialization value to determine whether the constraint definition was changed during the validation process.

17 citations


Proceedings ArticleDOI
15 Apr 1996
TL;DR: A new distributed real-time OCC algorithm with DASO, called DOCC-DA, is proposed and its performance has been compared with the distributed OCC protocol without dynamic serialization order adjustment, indicating that the performance of the proposed protocol is better.
Abstract: Although many recent studies have suggested that optimistic concurrency control (OCC) with dynamic adjustment of serialization order (DASO) is more suitable than two phase locking (2PL) for real-time database systems (RTDBS), most of the protocols proposed for DRTDBS are based on 2PL. When OCC with DASO is extended to DRTDBS, a number of issues have to be resolved. These include the heavy overhead for maintaining the dynamic serialization order of transactions in a distributed environment and the resolution of deadlock due to distributed validation. A new distributed real-time OCC algorithm with DASO, called DOCC-DA, is proposed with the above issues taking into consideration. Its performance has been compared with the distributed OCC protocol without dynamic serialization order adjustment. The results indicate that the performance of the proposed protocol is better.

16 citations


Patent
19 Dec 1996
TL;DR: In this article, the authors introduce the concept of a serialization fence instruction, which ensures that after a control register in a computer has been modified, all subsequent instructions will observe the effects of the control register modification.
Abstract: A new instruction that ensures that the effects of a control register write will be observed at a well defined time is introduced. Specifically, the present invention introduces the concept of a serialization fence instruction. The serialization fence instruction ensures that after a control register in a computer has been modified, all subsequent instructions will observe the effects of the control register modification. Two different serialization fence instructions are illustrated: a data memory reference serialization fence instruction (SRLZ.d) and an instruction fetch serialization fence instruction (SRLZ.i). The data memory reference serialization fence instruction ensures that subsequent instruction executions and data memory references will observe the effects of the control register write. The instruction fetch serialization fence instruction ensures that the entire machine pipeline, starting at the initial instruction fetch stage, will observe the effects of the control register write.

15 citations


Journal ArticleDOI
TL;DR: The paper shows how transaction management protocols can be designed using discrete-event system control theory and outlines designs for some well-known protocols: serialization graph testing, two-phase locking, and timestamp ordering.
Abstract: The paper shows how transaction management protocols can be designed using discrete-event system control theory. It outlines designs for some well-known protocols: serialization graph testing, two-phase locking, and timestamp ordering. These protocols can be obtained as solutions (centralized, fully decentralized, or maximal decentralized) of standard control problems. The results serve to unify the problems considered and suggest the possibility of computer-aided design.

8 citations


Journal ArticleDOI
TL;DR: The article shows how many different rule bases may be mapped onto a connectionist architecture for parallel execution, and an example implementation of the Farmer's Dilemma planning problem is given to illustrate the potential.
Abstract: The task of implementing a simple rule-based production system in a connectionist architecture is discussed. To implement a connectionist-based production system, it is essential to be capable of representing explicit rules by means of simple neuronlike computing units. The architecture described here uses a local representation based upon the instance oriented symbolic/connectionist expert system SC net. The problems of variable binding and variable value instantiation are solved in the context of this system. The network is built such that only one value is bound to a variable during each rule firing cycle. Issues regarding serialization and working memory consistency are also solved. An example implementation, the Farmer's Dilemma planning problem, is given to illustrate the potential of this approach. The article shows how many different rule bases may be mapped onto a connectionist architecture for parallel execution.

03 Oct 1996
TL;DR: This dissertation proposes a variation of weighted priority scheduling algorithm called Deadline Access Parameter Ratio (DAPR), that actively considers the I/O requirements and the amount of unprocessed work for "canned" transaction assumption, and shows through simulation that DAPR performs significantly better than existing scheduling algorithms under overloaded situations.
Abstract: Many emerging database applications, such as, automated financial trading, network management and manufacturing process control involve accessing and manipulating large amounts of data under time constraints. This has led to the emergence of active and real-time database as a research area, wherein transactions trigger other transactions and have time deadlines. In this dissertation, three important issues are investigated: the correctness criteria for various classes of transactions; real-time transaction scheduling algorithms for overload situation; and, a concurrency control policy that is sensitive to time deadline and transaction triggering. The first part of the dissertation deals with the issue of consistency of sensor reported data. We formally define sensor data consistency and a new notion of visibility called quasi immediate visibility (QIV) for concurrent execution of write-only and read-only transactions. We propose a protocol for maintaining sensor data consistency that has lower response time and higher throughput. The protocol is validated through simulation. Real-time schedulers must perform well both under underloaded and overloaded situations. In this dissertation, we propose a variation of weighted priority scheduling algorithm called Deadline Access Parameter Ratio (DAPR), that actively considers the I/O requirements and the amount of unprocessed work for "canned" transaction assumption. We show through simulation that DAPR performs significantly better than existing scheduling algorithms under overloaded situations. The limitation of the proposed algorithm is that in underloaded situations DAPR is not an option. The last part of this dissertation proposes a concurrency control (CC), called OCCWB, which is an extension of conventional optimistic CC. OCCWB takes advantage of the "canned" transaction assumption and includes pre-analysis stage, wherein, transactions are selectively blocked from executing if there is a high probability of restarting. The algorithm defines favorable serialization orders considering transaction semantics and tries to achieve such orders through appropriate priority adjustment. OCCWB is shown to perform significantly better than other CC policies under reasonable pre-analysis overhead for underloaded situation, and consistently better in overloaded situations, even with high pre-analysis overhead, for a wide range of workload and resource parameters.



Proceedings ArticleDOI
23 Oct 1996
TL;DR: The authors propose an efficient heuristic to synthesize combined address transformation (NP complete) which applies to arbitrary linear patterns, arbitrary multistage networks, and an arbitrary number of power-of-2 memories.
Abstract: A method for mapping arrays into parallel memories to minimize serialization and network conflicts for lock-step systems is presented. Each array is associated an arbitrary number of data access patterns that can be identified following compiler data-dependence analysis. Conditions for conflict-free access of parallel memories and network are derived for arbitrary power-of-2 data patterns and arbitrary multistage networks. The authors propose an efficient heuristic to synthesize combined address transformation (NP complete) which applies to arbitrary linear patterns, arbitrary multistage networks, and an arbitrary number of power-of-2 memories. The method can be implemented as part of the address transformation (Xor and And) or through compiler emulation. The performance of optimized storage schemes is presented for FFT, arbitrary sets of data patterns, non power-of-2 stride access in vector processors, interleaving, and static row-column storages. Their approach is profitable in all the above cases and provides a systematic method for converting array-memory mapping and network aspects of algorithms from one network topology to another.

Book ChapterDOI
01 Jan 1996
TL;DR: In a shared-disk parallel I/O system, several processes may be accessing the disks concurrently, which can lead to serialization of the processes and poor disk utilization, even when the static load on the disks is balanced.
Abstract: In a shared-disk parallel I/O system, several processes may be accessing the disks concurrently. An important example is concurrent external merging arising in database management systems with multiple independent sort queries. Such a system may exhibit instability, with one of the processes racing ahead of the others and monopolizing I/O resources. This race can lead to serialization of the processes and poor disk utilization, even when the static load on the disks is balanced. The phenomenon can be avoided by proper layout of data on the disks, as well as through other I/O management strategies. This has implications for both data placement in multiple disk systems and task partitioning for parallel processing.



Journal ArticleDOI
TL;DR: MENDELS ZONE has the following unique features from a parallel programming viewpoint: the confluence property of the complete term rewriting system ensures the quality of non-deterministic execution in parallel programs.
Abstract: MENDELS ZONE is a formal specification-based practical parallel program development system on an MIMD machine with 64 processors. It has been applied to the several practical applications: one such application is described in formal specifications totalling 3700 lines, and the corresponding parallel programs generated from these formal specifications totals 6200 lines. MENDELS ZONE has several key aspects. First, an algebraic specification is used for the functional part of parallel programs and a temporal logic specification is used for the synchronization part of the parallel programs. Second, Petri nets and data-flow diagrams are adopted for visualization. Third, MENDELS ZONE has the following unique features from a parallel programming viewpoint. (1) The confluence property of the complete term rewriting system ensures the quality of non-deterministic execution in parallel programs; (2) Serialization in parallel programming is specified using propositional temporal logic; (3) Parallel implementation of theorem provers contributes to practical use.

Patent
13 Dec 1996
TL;DR: In this article, a system and a method for designing and constructing software components and systems by assembling them from independent parts which is compatible with and extends existing object models is described, including a terminal interface and a terminal mechanism for interfacing objects.
Abstract: A system and a method for designing and constructing software components and systems by assembling them from independent parts which is compatible with and extends existing object models. A terminal interface and a terminal mechanism for interfacing objects is included. The mechanism is independent from the actual type of interactions established through it and allows objects to invoke directly services of other objects. All objects in a given system implement and expose a terminal interface. A property interface and mechanism with hierarchical property names and ability to execute queries is also included. The mechanism can be used for parameterization and serialization of objects, as well as to provide structured storage. A new and advantageous type of software object, named parts, is defined. Parts are constructed through an abstract factory and implement a property interface and a terminal interface.

Proceedings ArticleDOI
20 Oct 1996
TL;DR: A new heuristic for synthesizing combined XOR-matrices is proposed and performance of optimized storage schemes is presented for sorting and for combining arbitrary sets of power-of-2 patterns.
Abstract: The serialization of memory accesses and network conflicts are two major limiting factors in lock-step parallel memories. We derive conditions for accessing parallel memories which is free of both network and memory conflicts. This applies to accessing arbitrary sets of linear data patterns. We also combine different access patterns (NP-complete) into one single compiler address transformation. The synthesized storage scheme applies to arbitrary linear patterns, arbitrary multistage networks, and arbitrary number of power-of-2 memories. We propose a new heuristic for synthesizing combined XOR-matrices. Performance of optimized storage schemes is presented for sorting and for combining arbitrary sets of power-of-2 patterns.

Proceedings ArticleDOI
11 Mar 1996
TL;DR: This work considers the problem of generation of embedded software from input system descriptions in a hardware description language (HDL) and presents the conditions based on variable definition and use analysis under which operation linearization is possible.
Abstract: We consider the problem of generation of embedded software from input system descriptions in a hardware description language (HDL). Generation of software for embedded computing requires a total ordering of operations, or linearization, under constraints to ensure timely interaction with other system components. We show by example conditions where no ordering of operations in a HDL can produce the modeled functionality in software. Therefore, the existence condition for software generation, or serializability, must be ensured before attempting any linearization. We present the conditions based on variable definition and use analysis under which operation linearization is possible. We then present our approach to operation serialization under timing constraints to produce efficient schedules for the embedded software.