Showing papers on "Silicon on insulator published in 1981"

Characteristics of MOSFETs fabricated in silicon-on-insulator material formed by high-dose oxygen ion implantation

Abstract: By implanting a dose of 6×1017 cm?2 of 32O at 300 keV into a silicon wafer, a buried oxide layer is formed. Crystallinity of the silicon layer above the buried oxide layer is maintained by applying a high (>200°C) substrate temperature during the ion implantation process. A two-step anneal cycle is found to be adequate to form the insulating buried oxide layer and to repair the implantation damage in the silicon layer on top of the buried oxide. A surface electron mobility as high as 710 cm2/Vs has been measured in n-channel MOSFETs fabricated in a 0.5 ?m-thick epitaxial layer grown on the buried oxide wafer. A minimum subthreshold current of about 10 pA per micron of channel width at VDS=2 V has been measured.

Multiple SOI structure fabricate by high dose oxygen implantation and epitaxial growth

Abstract: A triple SOI (Silicon crystal On Insulator) structure has been fabricated on (100) and (111) Si substrates, utilizing three SIMOX (Separation by IMplanted OXygen) cycles. The SIMOX process consists of high-dose oxygen implantation followed by annealing and epitaxial growth of silicon, and provides good surface morphology. The top Si layer of the present triple SOI is single crystalline, which is confirmed by reflection electron diffraction and Rutherford backscattering measurement.

Fabrication method for high conductivity, void-free polysilicon-silicide integrated circuit electrodes

Abstract: A method of providing self-passivating interconnection electrodes for semiconductor devices which provides low resistivity composite polysiliconsilicide electrodes. In the method the formation of oxidation induced voids in polysilicon underlying the silicide is eliminated by deposition of polysilicon and stoichiometric proportions of silicon and a silicide-forming metal. These steps are followed by deposition of a silicon layer having a thickness determined to provide between 30 and 100 percent of the silicon required to form a silicon dioxide passivation layer. Subsequent thermal oxidation of the layered electrode structure provides a self-passivated structure useful for fabrication of silicon gate MOSFET devices as well as other integrated circuit structures.

Predicting Lower Bounds on Failure Power Distributions of Silicon NPN Transistors

Abstract: Design of electronic circuits which will survive an electrical overstress environment usually requires information on the failure threshold of semiconductor devices. The specification of that failure threshold must consider the fact that there is a distribution in the failure levels for devices having the same part number. This distribution arises from at least two sources. First, manufacturers of devices with the same part number only guarantee that their parts meet the required electrical specifications. Since electrical specifications are usually broad, there are a number of topological designs and processing techniques which will yield devices with those specifications. Thus, a sample of devices with the same part number from different manufacturers is likely to yield devices with significant physical differences. The engineer should suspect that these physical differences will be reflected in a distribution of failure threshold levels.

The Microstructure of Silicon-on-Insulator Structures Formed by High Dose Oxygen Ion Implantation

Abstract: Cross-sectional and plan view transmission electron microscopy and high resolution scanning electron microscopy have been used to characterize the microstructure of silicon-on-insulator formed by high dose oxygen ion implantation. The complete microstructure was observed to be composed of a series of distinct zones. The top silicon layer was {100} single crystal with a very low dislocation density. The second layer was a mixture of fine grained polysilicon and amorphous SiO 2 . The third layer was pure SiO 2 , followed by a second mixed layer. Finally, there was a layer of {100} silicon with an extremely high dislocation density. Some of the dislocations extended as far as 1 μm into the Si substrate. The relative widths of the layers were found to depend on the total ion fluence. The oxide layer did not occur for low doses and the two mixed layers merged into one zone. At high doses, the silicon-silicon dioxide interfaces are abrupt due to internal oxidation.

Silicon-on sapphire monolithic microwave ICs

Abstract: This paper will describe an expandable silicon single 50μ gate MESFET used for switching and a 400μm interdigitated 8-gate device used for low-noise amplification. Also to be discussed will be the design of a 3-stage amplifier with a 20dB gain over a 15% 3dB bandwidth.

Silicon-on-Insulator MOSFETs Fabricated in Zone-Melting-Recrystallized Poly-Si Films on SiO2

Abstract: N- and p-channel enhancement-mode MOSFETs have been fabricated in Si films prepared by zone-melting recrystallization of poly-Si deposited on SiO2-coated Si substrates. The transistors exhibit high surface mobilities, in the range of 560–620 cm2/V−s for electrons and 200–240 cm2/V−s for holes, and low leakage currents of the order of 0.1 pA/µm (channel width). Uniform device performance with a yield exceeding 90% has been measured in tests of more than 100 devices. The interface between the Si film and the SiO2 layer on the substrate is characterized by an oxide charge density of 1–2 × 1011 cm−2 and a high surface carrier mobility. N-channel MOSFETs fabricated in Si films recrystallized on SiO2-coated fused quartz subtrates exhibit surface electron mobilities substantially higher than those of single-crystal Si devices because the films are under a large tensile stress.

Beam Recrystallized Silicon-on-Insulator Devices

Abstract: Beam-recrystallized silicon-on-insulator is an attractive material for VLSI integrated circuit and flat panel display applications. This paper describes the electrical characteristics that are unique to MOSFETs fabricated in this material. The back-interface between the silicon and the insulator significantly affects the leakage current by acting as a possible leakage path, depending on the charge at the back interface and the doping concentration in the silicon close to the back interface. In addition, enhanced arsenic diffusion along grain boundaries can cause short circuits between the source and the drain of an n-channel MOSFET. Evidence of such enhanced diffusion are presented as well as means to reduce the impact of the problem. It is shown that molecular hydrogen can be used to passivate the grain-boundaries in the recrystallized silicon material, thereby increasing the carrier mobility. A profile of the carrier mobility as a function of depth from the surface of the silicon is presented, showing that the carrier mobility is not reduced significantly, even close to or at the back interface.

CMOS-Transistors in Silicon on Sapphire

Abstract: A single-bit complementary random access memory cell, consisting of one flip-flop circuit with feedback through a transmission gate, together with write and read gates, has been constructed in silicon on sapphire. The transistors of the cell have been made by ion-implantation and aluminium-gate techniques, and both the p-channel and the n-channel transistors are of the enhancement type. The channel length is 5 μm and the width 100 μm. The total circuit delay from write command to output sense signal is 9 ns for a 10 V supply voltage. Short-gate p-channel transistors fabricated in silicon on sapphire have also been investigated. For a transistor with a 3 μm gate length a low leakage current could be achieved if a phosphorus dose of 7 × 1011 ions cm-2 was used for the channel doping implantation. Low-leakage transistors with shorter gate length can be obtained by increasing the channel doping.