Showing papers on "State (computer science) published in 1983"

What Good is Temporal Logic

Abstract: This was an invited paper. It describes the state of my views on specification and verification at the time. It is notable for introducing the idea of invariance under stuttering and explaining why it’s a vital attribute of a specification logic. It is also one of my better-written papers.

Modular Verification of Computer Communication Protocols

Abstract: Programs that implement computer communications protocols can exhibit extremely complicated behavior, and neither informal reasoning nor testing is reliable enough to establish their correctness. In this paper we discuss the application of modular program verification techniques to protocols. This approach is more reliable than informal reasoning, but has an advantage over formal reasoning based on finite-state models, the complexity of the proof need not grow unmanageably as the size of the program increases. Certain tools of concurrent program verification that are especially useful for protocols are presented, history variables that record sequences of input and output values, temporal logic for expressing properties that must hold in a future system state such as eventual receipt of a message), and module specification and composition rules. The use of these techniques is illustrated by verifying two data transfer protocols from the literature: the alternating bit protocol and a protocol proposed by Stenning.

A theory of error-based testing

Abstract: Testing is the process of inferring the correctness of a program based on information collected during program execution. This process is called error-based when the information collected is used to infer that certain errors are not in a program. It is assumed here that a program can only be incorrect in a limited fashion specified by associating alternate expressions with program expressions. Substitution of an alternate expression for a program expression yields an alternate program that is potentially correct. The goal of error-based testing is to differentiate the program from each of its alternates. Two types of error-based testing are given. In static error-based testing the code is analyzed to produce two conditions. A creation condition describes when a class of alternate expressions will affect the program state. A propagation condition describes when an alternate program state will affect the output. If the output of the program is correct and both conditions are satisfied, all alternatives are faults detected by the test set. In dynamic error-based testing information is first collected from test executions. It is then proved that certain alternate programs are eliminated. A particular form of dynamic error-based testing based on symbolic execution is presented. In symbolic testing program expressions are replaced by symbolic alternatives that represent classes of alternate expressions. The output from the system is an expression in terms of the input and the symbolic alternative. Equating this with the output from the original program yields a propagation equation whose solutions are those alternatives which are not differentiated by this test. Since an alternative set can be infinite, it is possible that no finite test differentiates the program from all its alternates. Circumstances are described as to when this is decidable. Program faults can interact in such a way that error-based testing declares each correct in the presence of the others. Such interaction is shown to occur rarely for a limited class of programs.

Voltage comparator circuit

Abstract: A voltage comparator which is hardly affected by noise and is operable with a low power consumption is disclosed. The comparator circuit comprises first and second flip-flop circuits coupled in series between different voltage terminals. The first flip-flop circuit operates in response to a pair of differential voltages and a state of the second flip-flop is determined by the first flip-flop circuit.

Virtual machine data processor

Abstract: A data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.

Computer controlled by voice input

Abstract: A computer controlled by a voice input has a speech recognition section for converting a keyword of a program which is entered by the voice input and corresponds to a start number, thereby obtaining a digital code. The digital code data which indicates the keyword selects the start number corresponding to the storage content of a table stored in a program memory. The start number data is used to access a start address of the corresponding program, thereby starting and executing the program. Also disclosed is a system wherein when a chosen key of a key input device is operated while a voice operator guidance is generated, a key-in signal is produced to forcibly stop the ongoing guidance. In particular, when a plurality of voice operator guidances are provided, the computer learns the state of the operation by the operator from the manner of the forcible stop, and automatically stops the generation of the voice guidance on a specific item from the next processing.

Processor for simulating digital structures

Abstract: A hardware simulator for simulating digital structures includes a general purpose computer and an improved simulator processor. The improved processor handles an advanced primitive having four inputs and one output and which is capable of representing a memory cell or similar structure. The architecture of the processor provides highly efficient compilation of the input states of a primitive and the primitive evaluator and resolver logic provide the output state in a minimum number of clock cycles. The simulator is a single, low cost unit capable of simulating 64K cell structures with a speed comparable to prior art simulators.

Operational characteristics of a harware-based pattern matcher

Abstract: The design and operation of a new class of hardware-based pattern matchers, such as would be used in a backended database processor in a full-text or other retrieval system, is presented. This recognizer is based on a unique implementation technique for finite state automata consisting of partitioning the state table among a number of simple digital machines. It avoids the problems generally associated with implementing finite state machines, such as large state table memories, complex control mechanisms, and state encodings. Because it consists primarily of memory, with its high regularity and density, needs only limited static interconnections, and operates at a relatively low speed, it can be easily constructed using integrated circuit techniques.After a brief discussion of other pattern-matching hardware, the structure and operation of the partitioned finite state automaton is given, along with a simplified discussion of how the state tables are partitioned. The expected performance of the resulting system and the state table partitioning programs is then discussed.

Scientists' Understanding of Propositional Logic: An Experimental Investigation

Abstract: Seventy-two scientists (psychologists, biologists, and physicists) from a large US midwestern state university completed a questionnaire designed to assess understanding of the principles of formal

Logic simulator operable on level basis and on logic block basis on each level

Abstract: A logic device, which may be a digital computer, is simulated by dividing the device into logic blocks and classifying the blocks by levels according to flow of signals in the device. A state memory simulates input and output logic states of the respective blocks. A simulator simulates operations of the respective blocks. The blocks on each level are successively simulated in four stages, namely, (1) provision of simulated logic states for the respective output logic states, (2) comparison of the simulated logic states with the respective output logic states, (3) decision of those of the input logic states of higher level blocks which should be changed into the simulated logic states, and (4) renewal of the output logic states and of the decided input logic states in the state memory. Renewal of the output logic states may be carried out during the stage (1). Alternatively, the logic blocks on each level are divided into groups with simulation for the blocks on each level substantially simultaneously carried out by a plurality of logic simulators which are assigned to the respective groups and are connected together for transfer of data and for renewal of the decided input logic states by the transferred data.

Networks of queues in discrete time

Abstract: We study a new class of networks of queues whose nodes operate in round-robin fashion and other ways of interest to computer science. We compute a stationary law of product form for the Markov process describing the state of the network. Moreover, we obtain the conditional expected travel time of a job given the job's requested processing times at particular nodes along its route.

A Multiprocess Network Logic with Temporal and Spatial Modalities

Abstract: We introduce a modal logic which can be used to formally reason about synchronous fixed connection multiprocess networks such as of VLSI. Our logic has both temporal and spatial modal operators. The various temporal modal operators allow us to relate properties of the current state of a given process with properties of succeeding states of the given process. Also, the spatial modal operators allow us to relate properties of the current state of a given process with properties of the current state of neighboring processes. Many interesting properties for multiprocessor networks can be elegantly expressed in our logic. We give examples of the diverse applications of our logic to packet routing, firing squad problems, and systolic algorithms.

Signaling protocol channel unit

Abstract: Disclosed is a channel unit for directly interconnecting a toll office multiplex carrier channel line and a terminal unit line such as that of a private branch exchange (PBX) or a telephone station set, thereby eliminating the normal local end office interconnection. In particular, the channel unit interfaces the different signaling protocols of the two lines and generates call progress controls signals such as dial tone and audible ringing which are normally generated by the local end office. The channel unit comprises a converter for each line for converting the electrical interface signals representative of the busy and idle conditions of the line to logic level signals also representative of the busy and idle conditions of the line. A predetermined series of these logic level signals form a control signal that indicates the state in one signaling protocol of a call on the line. Since the control signal indicative of the state in one signaling protocol of the call on one line is typically not useable by the other line, a microprocessor included in the unit generates a second control signal to advance the state in another signaling protocol of the call on the other line to an equivalent call state. An additional converter then converts the logic level signals of this second control signal to the electrical interface signals of the other line to advance the state in the other signaling protocol of the call to the equivalent call state. The unit further comprises a receiver and transmitter for exchanging dial pulse and dual tone multifrequency address signals between the lines. Also, included are circuits for applying call progress control signals such as dial-tone, audible ringing, and power ringing to the lines.

Data processor version validation

Abstract: A data processor (12) capable of automatically storing in an external memory (20) all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor (12) automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor (12) then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.

Network access device

Abstract: A network access device (NAD) is comprised of a data set for coupling to a data communication trunk, a trunk control unit (TCU) connected with the data set, a trunk control interface (TCI) connecting the TCU to an internal data bus, an internal memory, a microprocessor control and a device interface for connection to a computer or some computer peripheral device. The data set provides for two-way communication from the data trunk to the TCU. Various network access devices connected to the data trunk communicate with one another. Every normal communication between NADs includes a concurrent, predictable state change in both NADs. The response to a message from one NAD to another includes information concerning what occurred upon receipt of the message. Various latches, sequencers, microprocessor logic and registers provide for functions according to various input and output states of response.

Character broadcast receiver

Abstract: PURPOSE:To display effectively the selection state of a designated program, by displaying the number identification mark of the designated program on a display screen and making the display mode different in the case, where the designated program is included in a transmitting character broadcast program, and the case where it is not included CONSTITUTION:A character broadcasting signal inserted in the vertical blanking time of a video signal is separated in a character broadcasting signal separating and clock regenerating part 10 and is supplied to a character broadcasting signal processing part 11 The signal processing part 11 outputs pattern and color data (c) and a display mode indication output and supplies them to a digital memory 12 and a memory controlling part 13 respectively When a program to be received is designated in a program designating part 15, the program selection output is supplied from a program selecting part 16 to a program identification mark display part 18 and the program code of the designated program is compared with program codes in a program index packet; and if a program code coincident with the program code of the designated program is obtained, the display mode of the program identification mark on the display screen is changed

Method and apparatus for transmitting status information between remote locations

Abstract: A system for transmitting status information from a first location to a remote second location includes a monitoring device at the first location for monitoring the state of a plurality of relays or other devices that are capable of being in either an active or inactive state. The monitoring device produces a digital signal representative of the state of the relays. A first memory storage device contains a table of digital codes arranged so that a unique code is associated in a predetermined manner with each relay in each state. A processor is provided for processing the digital signal from the monitoring device and for accessing the table to retrieve the code associated with the present state of each relay. The processor also produces a first signal indicative of a change of state of any relay from the inactive to the active state. A transmitter transmits the codes retrieved from the processor in a predetermined sequence. An interrupt device is included that interrupts the transmission sequence in the presence of the first signal to cause the immediate transmission of the code associated with the relay that has changed from the inactive to the active state. A receiver at the remote second location receives the transmitted codes and verifies their validity by comparing the received codes to a table of expected codes contained in a second memory storage device. If the code received is valid, a decoder determines the relay and state represented and formulates and outputs a control word representative of the state of the monitored relays. If the code is invalid, an alarm signal is generated that inhibits the output of a control word. Once an alarm signal is generated, it is maintained until a valid code is received for each of the monitored relays without the reception of an intervening invalid code. Preferably, the transmission and reception of the codes are accomplished under control of a digital computer operating under program control.

Reachability analysis of protocols with FIFO channels

Abstract: In a complete protocol design process, it is often important to validate the protocol for general correctness properties such as boundedness, deadlock absence, and well-formedness. However, for any general protocol modeled as a number of communicating finite state machines with unbounded FIFO channels, the above properties are known to be undecidable [Brand81a, Brand80a]. In this paper we demonstrate the decidability of those properties for a class of protocols, called well-ordered protocols. We introduce an algorithm for constructing a finite reachability tree for any given protocol with FIFO channels and show that by using this reachability tree, one can decide whether any given protocol is well-ordered, and if it is well-ordered whether it has an unbounded channel, a state deadlock, or an unspecified reception.

Lighting unit with improved control sequence

Abstract: An energy efficient lighting unit is described designed for functional similarity to the incandescent light used in the home. The lighting unit utilizes a metal vapor arc lamp as the main source of light supplemented by a standby filamentary light source. The lighting unit includes means for converting 60 hertz ac to dc, and a dc energized operating network containing a three transistor switch. The transistor switch is used to provide dc and low frequency (120 Hz) energization to the filament, and high frequency energization for both filament and arc lamp. The high frequency energization, which starts and transitions the arc lamp, is discontinued after the arc lamp is started. In the final run state, the arc lamp, which is serially connected with the filament across the dc supply, is ballasted by the filament. The transistor switch is controlled in its operation by control logic provided by an integrated circuit, which provides a complex control sequence, optimized for minimum electromagnetic interference for normal starts, "hot restarts", and a failure state, called "End of Life" in which starting attempts are discontinued.

Virtual memory data processor.

Abstract: A data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.

Microprocessor with branch control

Abstract: A microprocessor data processing system (1700) includes system units (50, 1704) connected to a bus (1702), with a bus arbiter (1712) and a protocol for assigning bus access to the system units (50, 1704). The microprocessor (50) executes both arithmetic operations and floating point operations. A microcontrol store (162) stores common instructions usable in different floating point operations. A PLA (180) supplies addresses to microcontrol store (162) and provides a signal indicating floating point instruction type. The microprocessor (50) includes a pending interrupt register (250) connected to mask and enable logic (268). The mask and enable logic (268) is connected to a priority encoder (278), which is connected to an interrupt latch (282). The latch (282) supplies outputs to generate a current state storage address. Branch control logic (1938) receives branch conditions inputs and branch control information and generates control signals for a next micro address multiplexer (1934) in a pipelined instruction path.

Signal-processing multiprocessor system

Abstract: A multiprocessor digital computation system for performing at least one signal-processing chain which includes a number of processes. Each process is executed by means of executing circuits including memories, computing operators and input-output couplers, which are interconnected by means of a bus system. The system includes a sequencer and an address and connection generator, wherein the sequencer includes plural process modules, one for each process to be executed, and indicates at each computing step the state of occupation or non-occupation of the executing circuits and allocates the executing circuits to execute a process to be executed upon availability of the resources necessary for execution of the process.

Functional command for semiconductor memory

Abstract: A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit The memory circuit typically operates by receiving a plurality of defined operational signals which control data transfer to and from the memory circuit The method for initiating the selected functional mode comprises applying an active state of at least a first of the operational signals to the memory circuit followed by applying an active state of a second of the operational signals to the memory circuit The timing of the second operational signal relative to the first operational signal is not within the defined specification limits of the first and the second operational signals for conventional data transfer to and from the memory The step of applying the active state of the second operational signal, outside the defined limits, serves to initiate the selected functional mode for the memory circuit An example of the selected functional mode is the activation of circuitry (62) which serves to apply a predetermined data state to a redundant column (63) which can be substituted to replace a defective primary column within a memory array After the memory array has previously received a first data state and the circuit (62) is activated to apply a second data state to the redundant column (63) the memory array is read and each column which produces a second data state is determined to be a redundant column With knowledge of the column substitution algorithm, it can then be determined which of the redundant columns have been programmed to replace specific original columns This method can therefore determine the physical configuration of the memory circuit despite the incorporation of redundant elements into the primary memory array

Data processing system

Abstract: PURPOSE:To improve the processing efficiency without interrupting the execution of a software program, by transferring data on a main storage device to a control storage device, through the use of a period only in which a main control section is not accessed the main storage or the control storage. CONSTITUTION:A transfer request detection section (DLF)13 normally monitors an instruction code of a software program, and when the section 13 detects a data transfer instruction from a software program MM1 to a CM2, the section 13 transmits a start signal, number of transferred words and a data address in the MM1 and the CM2 to a data transfer control section (FLF)15. A transfer timing detection section (DCCV)12 monitors a memory access control section (MAC)10 and a main control section (MCC)11 normally, and detects that the MAC10 is at idle state and the MCC11 is in wiring logic control state, then a start signal is given to the FLF15. The FLF15 starts the MAC10 when a start signal is given from both the DLF13 and the DCCV12, and starts the data transfer from the MM1 to the CM2 and informs the end of processing to a transfer end monitor display (EFL)16 when the required number of words is finished for transfer, and the EFL16 stops transfer and display of the DLF13.

Hierarchical dialogue structures in interactive computer systems

Abstract: A powerful yet simple-to-use command dialogue has evolved in the development of an interactive graphics system for the computer-aided design of electronic circuits. This dialogue overcomes many of the problems typically encountered in systems with a strongly hierarchical command structure; the user is kept constantly aware of the current state within the hierarchy and is able to manoeuvre rapidly about this structure. The rules for the use of the dialogue are few and simple; mistakes are not catastrophic. The dialogue is equally suited to both naive and experienced users. The dialogue is described in the context of an interactive graphics environment, but the extension of the principles to any interactive computer system should be obvious.

Atmospheric abnormality detection alarm system

Abstract: An atmospheric abnormality detection system includes a command discriminator and a display/alarm circuit in each sensor terminal. When the command discriminator receives a coincidence signal from an address comparator, the command discriminator causes an A/D converter to convert an analog sensor output to a digital signal as response data. When an abnormal state display command is transmitted from a main unit to the command discriminator, the command discriminator causes the display/alarm circuit to display information indicating the abnormal state and/or generate an audible alarm.

Logic state analyzer with time and event count measurement between states

Abstract: A logic state analyzer monitors the ongoing succession of states occurring in a collection of digital signals, and stores in a memory either all such states or a selected subset thereof meeting certain qualification criteria. The oldest stored states are overwritten as the newest states are stored. Upon recognition of some trigger condition the logic state analyzer will subsequently store a preselected number of additional states, the collectivity of which may be termed the captured trace. The utility of such a trace in a logic state analyzer is enhanced by equipping the analyzer with a counting mechanism selectively responsive to a high speed clock signal or a programmable state detector. In the former case the counter operates as a timer whose value may represent either the elapsed time between consecutive states in the trace or between each state in the trace and an origin along a time axis. In the latter case the user identifies a state or event of interest and the counter records the number of times that state occurs between the stored states of the trace. In both cases the values of the times or event counts are stored as part of the trace and are displayed in correlated relation to the state data therein.

Logic circuit test system

Abstract: A test pattern generator for providing test patterns to a logic circuit under test, wherein the logic circuit to be tested does not have a terminal for being set to an initial state before starting the test patterns. The initial state of the logic circuit is detected while supplying an increment pattern to increment the internal state, and the test patterns are supplied a predetermined number of clock pulses after the initial state is detected. The length of the period of the clock pulses for the test can be varied.