Showing papers on "Stuck-at fault published in 1972"

A Deductive Method for Simulating Faults in Logic Circuits

Abstract: A deductive method of fault simulation is described, which "deduces" the faults defected by a test at the same time that it simulates explicitly only the good behavior of logic circuit. For large logic circuits (at least several thousand gates) it is expected to be faster than "parallel" fault simulators, but uses much more computer memory than do parallel simulators.

A New Representation for Faults in Combinational Digital Circuits

Abstract: A new representation for faults in combinational digital circuits is presented. Faults that are inherently indistinguishable are identified and combined into classes that form a geometric structure that effectively subdivides the original circuit into fan-out-free segments. This fan-out-free characteristic allows a simplified analysis of multiple fault conditions. For certain circuits, including all two-level single-output circuits, it is shown that the detection of all single faults implies the detection of all multiple faults. The behavior of any circuit under fault conditions is represented in terms of the classes of indistinguishable faults. This results in a description of the faulty circuit by means of Boolean equations that are readily manipulated for the purpose of fault simulation or test generation. A connection graph interpretation of this fault representation is discussed. Heuristic methods for the selection of efficient tests without extensive computation are derived from these connection graphs.

Path Sensitization, Partial Boolean Difference, and Automated Fault Diagnosis

Abstract: A tool employed in automated fault diagnosis is emphasized: path sensitization by partial Boolean difference analysis. Motivated by the analogy between a test system and a communication system, a model for fault detection of a logic net is outlined from the standpoint of information theory. The classical ``path sensitizing'' technique is made systematic using the partial Boolean difference. This technique is based on a new theorem on the partial Boolean difference. Finally, a programmable fault detection algorithm is presented along with an example.

Fault isolation via components simulation

Abstract: The problem of deducing the internal component parameters from external measurements of a large-scale system is studied in the context of the fault isolation problem. By assuming an appropriate algebraic connection model matrix, algebraic necessary and sufficient conditions for the exact determination of the internal component parameters are obtained for both the single-test frequency and multiple-test frequency cases. In both cases the linear independence of the rows or columns of certain matrices may be used to determine appropriate test points and test frequencies.

Fault detection and localization in digital systems

Abstract: A method for synthesizing a test function which can detect and isolate a fault to the single input of a multiple input circuit and means for utilizing the resulting function is disclosed. The test circuit is a function only of the number of inputs to the circuit under test and not a function, as is the usual case, of what the circuit under test is performing.

Fault Identification in Electronic Circuits with the Aid of Bilinear Transformations

Abstract: A method has been developed for applying bilinear transformations to the identification of faulty components in linear electronic circuits. Simple magnitude and phase measurements, at a number of test frequencies, are made and plotted on a set of predetermined loci in the complex transfer-function plane. The data for plotting the loci are determined either experimentally or by circuit analysis with a digital computer. The faulty component and the parameter value are then determined from the loci. The method has the advantage that it provides a graphical representation of the circuit behavior with a faulty component and also readily allows experimental error to be taken into account when plotting the measured data. The method is demonstrated with a practical transistor amplifier circuit.

Fault detection and isolation in a data processing system

Abstract: A fault interrupt system is arranged, upon the detection of a fault to cause a processor in which the fault is detected to enter a fault check-out routine. Successive fault conditions detected while performing the fault check-out routine causes re-entry into that routine. A faulty processor is therefore, trapped within the fault check-out routine. Additionally the detection of a fault causes the master capability register of the fault detecting processor to be overwritten with a capability defining a special capability table which is only relevant to the fault check-out programs. By this mechanism the faulty processor cannot, even under fault conditions, gain access to any storage areas outside those of the fault check-out programs. In the multi-processor/multi-storage module system of the PP250 a number of copies of the fault check-out programs and related workspace areas on a one copy per store module basis are provided together with a special capability pointer for each processor of the system and each entry into the check-out program is performed using a different store and therefore entry mechanism into the check-out programs copy so that intermittent processor faults or particular storage module faults will not maintain the processor indefinitely in the check-out program.

Generation of Fault Tests for Linear Logic Networks

Abstract: In this note we study the problem of fault detection in linear logic networks. We introduce the concept of error vectors that indicate how the effect of a fault propagates through a network. These vectors allow one to identify redundancies in the network as well as calculate the output of the network given a fault and an input. Problems related to fault diagnosis and the detection of multiple faults are also considered.

Fault simulation system for determining the testability of a non-linear integrated circuit by an electrical signal test pattern

Abstract: A system involving the use of fault simulation for determining whether a proposed non-linear integrated circuit is testable by a proposed incremental bilevel electrical signal test pattern. The system, which is particularly advantageous in determining the testability of integrated circuits having sequential logic, involves the conversion of the bilevel electrical test pattern into a corresponding three-level test pattern, and the application of said three-level pattern to a three-level "good" circuit simulation of the integrated circuit and to a number of three-level "bad" circuit simulations of said circuit, each of said "bad" circuit simulations being representative of a different stuck fault condition which is to be determined by the test pattern.

Ground fault protective system

Abstract: Highly sensitive ground fault protective system utilizing an operational amplifier, integrator and switching means for interrupting the flow of current in a distribution system when the amplified and integrated signal produced by a fault current reaches a sharply defined threshold value. The system can be built in highly miniaturized, modular form which can be incorporated in small circuit breakers and receptacle outlet boxes.

A Design Procedure for Fault-Locatable Switching Circuits

Abstract: A technique to design fault-locatable combinational switching circuits is given. The networks resulting from the application of the proposed technique have at most three levels of gates.

An Improved Bound on the Length of Checking Experiments for Sequential Machines with Counter Cycles

Abstract: The bound on the length of checking experiments derived by Murakami et al. [1] is improved by using a more efficient output specification in the counter cycle.

Fault insertion techniques and models for digital logic simulation

Abstract: During the past few years it has become increasingly apparent that in order to design and develop highly reliable and maintainable digital logic systems it is necessary to be able to accurately simulate those systems. Not only is it necessary to be able to simulate a logic net as it was intended to behave, but it is also necessary to be able to model or simulate the behavior of the logic net when it contains a physical defect. (The representation of a physical defect is known as a fault.) The behavioral simulation of a digital logic net which contains a physical defect, or fault, is known as digital fault simulation.

Logic simulation and fault analysis of a self-checking switching processor

Abstract: During an exploratory study in the design of a stored program processor for an electronic switching system, the need for logic simulation for design verification was evident [1]. The advantages of using logic simulation concurrent with hardware design are many.This paper will discuss logic simulation and fault analysis work undertaken while designing a self-checking switching processor. The logic simulation and fault analysis were implemented on an IBM/360 model 67 executing a simulator called LAMP (Logic Analyzer for Maintenance Planning) [3]. Section 2 briefly describes the simulator system and the logic simulated. Circuit preparation for simulation and a hierarchical method for simulating large circuits are discussed in Section 3. In Section 4, characteristics and design objectives of self-checking circuits are discussed. Concurrent fault detection methods and self-checkability figures of merit are then considered.

Improved Procedures for Determining Diagnostic Resolution

Abstract: The definition of the generalized fault table [1] is expanded to cover a representation employing more than one fault q cube per fault pattern. On the basis of this expanded definition and simple concepts from a cover algebra, a new procedure is developed for finding first- and second-order diagnostic resolutions.