Journal ArticleDOI
A Deductive Method for Simulating Faults in Logic Circuits
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A deductive method of fault simulation is described, which "deduces" the faults defected by a test at the same time that it simulates explicitly only the good behavior of logic circuit.Abstract:
A deductive method of fault simulation is described, which "deduces" the faults defected by a test at the same time that it simulates explicitly only the good behavior of logic circuit. For large logic circuits (at least several thousand gates) it is expected to be faster than "parallel" fault simulators, but uses much more computer memory than do parallel simulators.read more
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Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
Journal ArticleDOI
Design for Testability—A Survey
TL;DR: The different techniques of design for testability are discussed in detail, including techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.
Journal ArticleDOI
Design for testability—A survey
T.W. Williams,Kenneth P. Parker +1 more
TL;DR: A short review of the basics of testability is given in this paper along with some reasons why one should test and different techniques of design for testability are discussed in detail, including techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.
Book
VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Journal ArticleDOI
PROOFS: a fast, memory-efficient sequential circuit fault simulator
TL;DR: The authors describe PROOFS, a fast fault simulator for synchronous sequential circuits that achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation while minimizing their individual disadvantages.
References
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Journal ArticleDOI
Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits
TL;DR: Two algorithms are presented: one, DALG-II, computes a test to detect a failure in acyclic logic circuits; the other, TEST-DETECT, ascertains all failures detected by a given test.
Journal ArticleDOI
On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets
TL;DR: A procedure is described for finding, by shortcut methods, a near-minimal set of tests for detecting all single faults in a combinational logic net, and it is shown that if a set of Tests can be found which detects an appropriate subset of faults in the enf, this set will detect all faults inThe original net.
Journal ArticleDOI
On an Improved Diagnosis Program
TL;DR: One of the more promising areas of computer use involves the coupling of a man to a computer system for real-time problem-solving where the procedure for solution of the problem is either unknown or involves complex tasks that can best be performed by humans.
Proceedings ArticleDOI
A model and implementation of a universal time delay simulator for large digital nets
TL;DR: A systems study of simulation and diagnosis for large digital computing systems has been performed, and the results have led to the implementation to be described, which permits the user to select the level of detail most appropriate to his requirements, and thus not hamper him with overly restrictive assumptions.
Journal ArticleDOI
Design and Use of Fault Simulation for Saturn Computer Design
Fred H. Hardie,Robert J. Suhocki +1 more
TL;DR: A system of IBM 7090 Data Processing System computer programs was developed for the purpose of normal and/or fault simulation of the Saturn computer and several programming techniques were utilized, including logic block ordering, parallel fault simulation, stimulus bypassing, and functional simulation.