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Showing papers on "Switched capacitor published in 1977"


Journal ArticleDOI
TL;DR: A new technique to analog sampled data filtering is presented which can be fully integrated using MOS technology, and advantages of this new approach are reduced circuit complexity, low sensitivity to coefficient variations, and efficient utilization of silicon area.
Abstract: A new technique to analog sampled data filtering is presented which can be fully integrated using MOS technology. Advantages of this new approach are reduced circuit complexity, low sensitivity to coefficient variations, and efficient utilization of silicon area. Performance of monolithic low Q(Q=1) and high Q(Q=73) filters are presented which were implemented using NMOS technology. In implementing the high Q filter a new operational amplifier design was used which had a 14-V output range, rms noise voltage of 45 /spl mu/V, an open-loop gain of 6000, and a unity-gain bandwidth of 2 MHz.

282 citations


Journal ArticleDOI
TL;DR: The authors have demonstrated the advantages of ratioed capacitors for integrated active filters experimentally, using a specially designed integrated MOS test chip.
Abstract: The equivalence between resistor-capacitor (RC) filtering circuits and circuits containing switches and ratioed capacitors is examined. The authors have demonstrated the advantages of ratioed capacitors for integrated active filters experimentally, using a specially designed integrated MOS test chip. Polysilicon gate technology was used to fabricate the chip, with the capacitors being formed by two levels of polysilicon. For the theoretical description, and as a design aid, attention is drawn to the general equivalence between a resistor and a circuit element consisting of a capacitor and two switches. Nonideal effects, which set limits to the generality, are also discussed.

179 citations


Journal ArticleDOI
TL;DR: A new approach, to the exact analysis of linear circuits containing periodically operated switches is presented, and explicit closed form solutions for both the periodically time-varying transfer function h(f, t) and the impulse response h(t,\tau) are derived.
Abstract: A new approach, to the exact analysis of linear circuits containing periodically operated switches is presented. After reformulation of the state equations conventional Fourier analysis is used to determine the response to arbitrary deterministic or stochastic inputs. The analysis is applicable also to improper circuits and circuits causing discontinuities in the state variables at the switching instants. The switches may operate in an arbitrary fashion with a common switching period. Explicit closed form solutions for both the (Fourier coefficients of the) periodically time-varying transfer function \hat{H}(f, t) and the impulse response h(t,\tau) are derived. These results are most suitable for computer aided design. Applications to switched filters and modulators are given.

145 citations


Proceedings Article
01 Sep 1977
TL;DR: In this paper, large-scale integrated circuits for many analog and combined analog-digital circuit functions are becoming feasible in N-channel and complementary metal-oxide-semiconductor technologies.
Abstract: Large-scale integrated circuits for many analog and combined analog-digital circuit functions are becoming feasible in N-channel and complementary metal-oxide-semiconductor technologies. Experimental results have been reported for analog to digital and digital to analog converters, a pulse-code-modulation voice encoder-decoder, and precision analog sampled-data frequency filters. Some of the key elements in these MOS circuits are precision-ratioed capacitor arrays, transistor analog switches, internally-compensated operational amplifiers, and offset-nulled comparators.

96 citations


Journal ArticleDOI
TL;DR: This paper deals in particular with the test problems of switched-capacitor (or single-transistor) MOS RAMs, and an efficient test flow is recommended for rigorous functional verification as well as design and yield improvements.
Abstract: An approach to dynamic MOS RAM testing has been developed. This paper deals in particular with the test problems of switched-capacitor (or single-transistor) MOS RAMs. Test procedures are developed from an understanding of the technology with which the memory circuits are built. The associated design weaknesses and failure modes are first reviewed, and four simple pattern-sensitivity programs are generated. Finally, an efficient test flow is recommended for rigorous functional verification as well as design and yield improvements.

21 citations


Patent
Hartmut Seiler1
10 Mar 1977
TL;DR: In this article, the authors propose an integrated circuit with at least two charge resistors and two discharge resistors, each connected to the timing capacitor, and selectively controllable switches connected to both the timing and the external switches.
Abstract: To provide for multiple timing intervals in an entirely integrated circuit structure without replacement of external circuit components, the integrated circuit includes at least two charge resistors and two discharge resistors, each connected to the timing capacitor, and selectively controllable switches connected to the timing capacitor and to the charge and discharge resistors to interconnect the timing capacitor with respective charge and discharge resistors and the input terminals to the timing circuit, as commanded by the respective switch setting. The switches, preferably, are transistor switches which are externally controllable by enabling respective inputs to the integrated circuit structure.

9 citations



Proceedings ArticleDOI
01 Jan 1977

2 citations