Showing papers on "System bus published in 2012"

Generalized Steady-State VSC MTDC Model for Sequential AC/DC Power Flow Algorithms

Abstract: In this paper, a steady-state multi-terminal voltage source converter high voltage direct current (VSC MTDC) model is introduced. The proposed approach is extended to include multiple AC and DC grids with arbitrary topologies. The DC grids can thereby interconnect arbitrary buses in one or more non-synchronized AC systems. The converter equations are derived in their most general format and correctly define all set-points with respect to the system bus instead of the converter or filter bus, which is often done to simplify calculations. The paper introduces a mathematical model to include the converter limits and discusses how the equations change when a transformerless operation is considered or when the converter filter is omitted. An AC/VSC MTDC power flow is implemented using MATPOWER to show the validity of the generalized power flow model.

System and method of detecting and locating intermittent and other faults

Abstract: Data associated with at least one building condition or status is sensed by one or more sensors. The data from these sensors may be sent over a data bus and received by the central computer. In addition, a modulated signal may be transmitted by one or both of the transmitters across the data bus. The modulated signal is received at the receiver, which analyzes the received modulated signal, and determines whether an intermittent fault has occurred on the data bus based upon the analyzing. For example, the receiver may compare the received signal to an expected pattern and when a discrepancy exists, an intermittent fault is determined to exist. The receiver may also determine the location of the fault based upon the analysis.

Intelligent microclimate monitoring system of transmission lines

Abstract: The invention discloses an intelligent microclimate monitoring system of transmission lines, wherein a background monitoring system is mainly composed of a monitoring server and a wireless communication gateway which are connected with each other; the intelligent microclimate monitoring system further comprises data collecting terminals installed on poles and towers of a transmission line, the data collecting terminal comprises a microclimate sensor, a microprocessor, a power supply and a wireless communication unit; one end of the microclimate sensor is connected with the transmission line, and the other end of the microclimate sensor is connected with the microprocessor through an address bus and a data bus; the wireless communication unit and the microprocessor are connected through the address bus and the data bus and are in wireless connection with the wireless communication gateway; and the power supply is electrically connected with the microprocessor, the microclimate sensor and the wireless communication unit respectively. The system enables a line technician to master the weather change rule of the line operation environment through microclimate data in real time so as to take corresponding measures to prevent power failure accidents of the line, for example, mounting a zinc oxide lightning arrester in a thunder region and adjustably climbing a dirty region, etc.

Runtime reconfigurable dataflow processor

Abstract: A processor includes a plurality of processing tiles, wherein each tile is configured at runtime to perform a configurable operation. A first subset of tiles are configured to perform in a pipeline a first plurality of configurable operations in parallel. A second subset of tiles are configured to perform a second plurality of configurable operations in parallel with the first plurality of configurable operations. The process also includes a multi-port memory access module operably connected to the plurality of tiles via a data bus configured to control access to a memory and to provide data to two or more processing tiles simultaneously. The processor also includes a controller operably connected to the plurality of tiles and the multi-port memory access module via a runtime bus. The processor configures the tiles and the multi-port memory access module to execute a computation.

Infrared automobile interior environment monitoring system based on controller area network (CAN) /local interconnect network (LIN) bus

Abstract: The invention relates to an infrared vehicle interior environmental monitoring system based on a controlled area network (CAN)/ local interconnect network (LIN) bus. The infrared vehicle interior environmental monitoring system based on the CAN / LIN bus comprises a senor, a signal processing module, an analog/ digital (A/ D) conversion circuit, an electronic control unit (ECU) system, a vehicle-mounted computer, a CAN/ LIN data bus, an alarming circuit, a liquid crystal display (LCD) module, a wireless communication module and a power source. Signals obtained by the sensor are processed through the signal processing module at first, and then are converted through the A/ D conversion circuit to be input to the ECU system to be processed. The ECU system carries out synthetic judgment by combining sensor information and vehicle state information obtained through the CAN/ LIN bus from the vehicle-mounted computer. When the ECU system finds that an environment is poor or a person / life is left and vehicle doors are locked inside a vehicle, the ECU system starts the alarming circuit to give an alarm, a message prompt is sent through the wireless communication module and an instruction is sent to the vehicle-mounted computer through the CAN/ LIN bus, and the vehicle-mounted computer adjusts vehicle windows or controls starting of an air conditioner and outer circulation of the air conditioner. The power source supplies power for parts. According to the infrared vehicle interior environmental monitoring system based on the CAN / LIN bus, a safety guarantee is provided for the person who does not want to stay in the vehicle, and accidents are avoided.

Battery management system of vehicle-mounted lithium power battery

Abstract: The invention discloses a battery management system of a vehicle-mounted lithium power battery. The system includes a master control unit and slave control units. The master control unit is in communication connection with the multiple slave control units through a data bus. The master control unit is in connection with battery groups, the total voltage and total current of which are acquired. The master control unit is also connected to a DC power supply, and is in connection with a charger through an external CAN bus. The master control unit mainly includes: a master microcontroller module, a total voltage detection module, a total current detection module, a battery system insulation detection module, a battery operating environment temperature detection module, a relay driving module, a data storage module, a bus communication module, an isolated power supply module, and a physical interface module of power supplies, data, signals, etc. The system provided in the invention has the advantages of simple structure, strong expansibility, and adaptability to different numbers of batteries. Being fully functional, the system has the functions of temperature control, equalization processing, battery performance evaluation, and battery self-protection, etc.

Two-wire communication system for high-speed data and power distribution

Abstract: Various embodiments of the present invention provide a two-wire (e.g., unshielded twisted pair) bus system that is simple (e.g., no microcontroller required in slave devices), synchronous with embedded clock information, inexpensive, automotive EMC compliant, and has sufficient speed and bandwidth for a large number of slave devices/peripherals, and also provides various protocols that can be used in various communication systems such as a two-wire bus system. The two-wire bus optionally may be self-powered, i.e., the master device may provide power to the slave devices over the two-wire bus. Various embodiments of the present invention methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system. Exemplary embodiments are described with reference to a two-wire point-to-point bus system, although the method can be used in other communication systems. Provisions are included for controlling the sequential powering of the bus and slave devices.

System for providing a reminder to remove a mobile electronic device from a vehicle

Abstract: A vehicle system for determining that at least one mobile electronic device is generally stationary and is potentially forgotten is provided. The system includes a vehicle data bus and a control module. The vehicle data bus transmits a signal indicating at least one trigger event. The trigger event indicates a vehicle exit condition. The control module is in communication with the mobile electronic device and the vehicle bus. The control module is in communication with the mobile device through a data connection to receive information. The control module includes control logic for receiving the trigger signal from the vehicle data bus. The control module includes control logic for determining if the mobile electronic device has moved based on information received from the data connection. The control module includes control logic for determining if the mobile electronic device is generally stationary if the trigger signal is received.

Bus pin reduction and power management

Abstract: A reduced-pin bus system includes a bus having one or more signal lines that are coupled to a bus power supply through a current limiting device. A master unit is coupled to the bus and is arranged to transmit communications across the bus during an active period of the bus and to initiate communications during (and/or at the end of) a quiescent period of the bus. A slave unit is coupled to the bus and is arranged to couple power from the one or more signal lines to a capacitor during the quiescent period of the bus and to consume power from the capacitor during the active period of the bus.

Content addressable memory

Abstract: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods

Abstract: Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods are disclosed. In one embodiment, the bus interconnect comprises an interconnect network configurable to connect a master port(s) to a slave port(s). A bus interconnect clock signal clocks the interconnect network. The controller is configured to receive bandwidth information related to traffic communicated over the master port(s) and the slave port(s). The controller is further configured to scale (e.g., increase or decrease) the frequency of the bus interconnect clock signal if the bandwidth of the master port(s) and/or the slave port(s) meets respective bandwidth condition(s), and/or if the latency of the master port(s) meets a respective latency condition(s) for the master port(s). The master port(s) and/or slave port(s) can also be reconfigured in response to a change in frequency of the bus interconnect clock signal to optimize performance and conserve power.

Embedded bus emulation

Abstract: A bus emulation device in accordance with one aspect of the present description includes an embedded microcontroller and a nonvolatile memory carried on a body. The memory contains firmware which includes boot code adapted to boot the microcontroller to operate in one of a plurality of dedicated operating modes in response to a mode switch. These dedicated operating modes include a learning mode in which bus signals generated by other bus devices are recorded in the nonvolatile memory, and an emulation mode in which recorded bus signals are retransmitted over the bus in response to received signals, to emulate a bus device. Other aspects are described and claimed.

Optimizing power usage by processor cores based on architectural events

Abstract: A method and apparatus to monitor architecture events is disclosed The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot There is at least one branch of the push bus in each core Each branch of the push bus may monitor one core with all the architectural events All the data collected from the events by the push bus is then sent to a power control unit

Real Time Bus Monitoring System Using GPS

Abstract: The Real Time Bus Monitoring and Passenger Information bus tracking device will serve as a viable notification system that will effectively assist pedestrians in making the decision of whether to wait for the bus or walk. This device is a standalone system designed to display the real-time location(s) of the buses in Mumbai city. The system will consist of a transmitter module installed on the buses, receiver boards installed on the bus stops, LED embedded map of the BEST bus transportation routes at the centralized controller. It will also have passenger information system software installed at the bus stops and which will provide user the relevant information regarding all the bus numbers going for his source to destination along with the route details and the cost. Assembly of these modules will enable the tracking device to obtain GPS data of the bus locations, which will then transfer it to centralized control unit and depict it by activating LEDs in the approximate geographic positions of the buses on the route map. It will also transmit its bus numbers and route names continuously as soon as the bus comes within the range of the receiver at the bus stop. In addition, the device will be portable and sustainable; it will not require an external power source, which will eliminate long-term energy costs.

Method and devices for selective RAM scrambling

Abstract: A method for selectively scrambling data within a memory associated with a computing device based on data tagging. The computing device may define security domains that are protected. Data generated by an application may be packaged as a data bus transaction having tagging information describing the application and/or the data. The data bus transaction may be transmitted over a bus of the computing device to a memory, such as internal memory, where the computing device may compare the tagging information to stored information describing security domains. When the data is determined to be protected based on the tagging information, the computing device may perform scrambling operations on the data. In an aspect, the tagging information may describe a virtual machine used to execute various applications on a processor. In another aspect, the tagging information may define destination memory addresses or content protection bit values.

Reconfigurable high speed memory chip module and electronics system device

Abstract: A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.

Remote intelligent update device for lightening detection and realization method thereof

Abstract: The invention relates to a remote intelligent update device for lightening detection and a realization method thereof. The device consists of a host computer, a DSP, a FPGA, a CPLD, a FLASH, a static storage and a data communication interface, wherein the data communication interface is connected with the DSP; the static storage is connected with the DSP through a bus, the DSP is connected with chip selection pins of the static storage through a chip selection signal port respectively, and the CPLD is provided with input and output pins of a plurality of users; and the DSP and the CPLD are connected through an address bus and a data bus. The realization method comprises the following steps of: adopting the host computer, adopting an update system to perform on-line remote update on a lightening signal identification model, and establishing a man-machine conversion window for system update; utilizing a passive configuration mode of the FPGA to establish a lightning identification modelwith configurable update; utilizing the DSP to realize the global administration to the update system and the man-machine conversion window; and utilizing a complex programmable logic device to realize the fast and stable update to the FPGA.

Configurable Mesh Data Bus In An Island-Based Network Flow Processor

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. A configurable mesh data bus includes a command mesh, a pull-id mesh, and two data meshes. The configurable mesh data bus extends through all the islands. For each mesh, each island includes a centrally located crossbar switch and eight half links. Two half links extend to ports on the top edge of the island, a half link extends to a port on a right edge of the island, two half links extend to ports on the bottom edge of the island, and a half link extents to a port on the left edge of the island. Two additional links extend to functional circuitry of the island. The configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit.

Method for switching hybrid storage modes, device and system

Abstract: An embodiment of the invention provides a method for switching hybrid storage modes, a device and a system The method includes acquiring IO (input and output) access feature data on a system bus within a current acquisition cycle; determining IO access features according to the IO access feature data; and switching to a hybrid storage mode corresponding to the IO access features when the hybrid storage mode corresponding to the IO access features is inconsistent to a hybrid storage mode used by the system The IO access features include a reading operation oriented mode or a writing operation oriented mode Accordingly, the problem that an existing system only supports one hybrid storage mode during running is avoided, and hybrid storage performances are improved

Communication method, communication system, and energy storage system including the same

Abstract: There is provided a battery system including a system bus, a system controller coupled to the system bus and configured to transmit one or more first system frames on the system bus, and one or more battery subsystems coupled to the system bus and configured to transmit one or more second system frames on the system bus, wherein at least one of the one or more battery subsystems including a storage system for storing power, and a storage system controller for controlling charging and discharging of the storage system, for receiving storage system data, and for transmitting the one or more second system frames including the storage system data on the system bus, wherein at least one of the system controller or the storage system controller is configured to apply a system frame division signal on the system bus between the system frames.

New method for monitoring voltage stability condition of a bus of an interconnected power system using measurements of the bus variables

Abstract: The study presents a new method for monitoring the voltage stability condition of a bus using measurements of the bus variables. For this purpose, bus real power, bus reactive power and bus voltage of a target/selected bus have to be measured (sampled) for two consecutive time frames. These measured values are used to monitor the voltage stability condition of a bus using the mathematical basis developed in this study. The validity and applicability of the proposed method has been established through simulation on IEEE 30 and IEEE 118 bus system.

Method and controller for an electric motor with switch testing

Abstract: For each phase of a controller, a pair of semiconductor switches comprises a high side switch and a low side switch. A direct current voltage bus provides electrical energy to the semiconductor switches at a test voltage level less than a full operational voltage level. A measuring circuit is adapted to measure the direct current bus voltage. A data processor determines that a deficiency in a tested, related semiconductor switch is present if the measured direct current bus voltage decreases or collapses upon activation of a particular semiconductor switch in the same phase of the controller, or if other sequential test results indicate a deficiency. If the deficiency in the related semiconductor switch is present the processor may prevent the voltage supply from providing the full operational voltage to the direct current data bus to prevent damage to the motor or the controller, for example.

Microprocessor protected against stack overflow

Abstract: A microprocessor includes a central processing unit, at least one call stack, a stack pointer, an address bus, and a data bus. The microprocessor further includes a hardware monitor configured to supply protection codes, insert the protection codes in the stack or let the central processing unit insert them, and then generate an error signal in response to an attempt to modify a protection code present in the stack.

Engine idle protection system

Abstract: An automated vehicle shutdown and user notification method and device for shutting down an engine in a vehicle having a passive keyless entry and start ignition system where the engine has unintentionally been left running by the user is disclosed. In one aftermarket embodiment, the method is implemented in an aftermarket remote start interface module. The module comprises a micro-controller, a memory, a vehicle data bus connector that provides for interface through the vehicles onboard diagnostic (OBDII) port to the vehicle data bus. The system includes a remote start module having a radio frequency transceiver and a cellular telephone transceiver, and provides audible, visual and electronic notifications that the vehicle has been left running and that the engine will be shut off unless the shutdown sequence is deactivated. If the shutdown fails by any malfunction, the system will go into an alternative notice mode.

Hierarchical buffer system enabling precise data delivery through an asynchronous boundary

Abstract: The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device with a memory core, a high speed upstream data bus, and a plurality of 1st tier buffers that receive data from the memory. The system further includes a 2 nd tier transfer buffer spanning a plurality of asynchronous timing domains that delivers the data onto the upstream data bus to minimize gaps in a data transfer. The method includes managing the buffers to allow data to flow from a plurality of 1st tier buffers through a 2nd tier transfer buffer, and delivering the data onto a high speed data bus with pre-determined timing in a manner which minimizes latency to the extent that the returning read data beats are always transmitted contiguously with no intervening gaps.

Heterogeneous multi-channel: fine-grained DRAM control for both system performance and power efficiency

Abstract: We propose a novel architecture of memory controller, called HMC (Heterogeneous Multi-Channel), as an improvement to the previous homogeneous multi-channel memory controller. HMC groups physical DRAM devices into logical sub-ranks with different data bus width, and controls them simultaneously. Employing new proposed memory access algorithm, HMC manages the number of devices involved in a single memory access flexibly, and achieves the best performance/power efficiency. Using four-core multiprogramming workloads, our experimental results show that HMC improves system performance by 27.6% with 24.2% reduction in DRAM power consumption on average.

Controlled intermediate bus architecture optimization

Abstract: An intermediate bus architecture power system includes a bus converter that converts an input voltage into a bus voltage on an intermediate bus and a point-of-load converter that supplies an output voltage from the bus voltage on the intermediate bus Additionally, the intermediate bus architecture power system includes a decision engine optimizing controller that controls a system variable to improve an overall system performance based on a monitored system variable or a system constraint In another aspect, a method of operating an intermediate bus architecture power system includes converting an input voltage into a bus voltage on an intermediate bus and converting the bus voltage on the intermediate bus into an output voltage The method also includes controlling a system variable to improve overall system performance based on a monitored system variable or a system constraint

Interface board for compact peripheral component interconnect (CPCI) architecture based on aircraft internal time division command/response multiplex data bus (MIL-STD-1553B)

Abstract: The utility model discloses an interface board for compact peripheral component interconnect (CPCI) architecture based on an aircraft internal time division command/response multiplex data bus (MIL-STD-1553B), in particular an MIL-STD-1553B protocol standard bus interface module, namely an aircraft internal time division command/response multiplex data bus interface module. The interface board comprises a digital signal processor (DSP) and a peripheral circuit thereof, a coding and decoding circuit and a bus drive circuit; the interface board is designed to be a plug-in signal processing board which has the performance of 33 MHz-peripheral component interconnect (PCI) and supports 32-bit data transmission; and the MIL-STD-1553B communication function is realized by the interface board through a CPCI bus-based interface. The interface board is widely applied to an aircraft integrated avionics system and an external store management and integration system, and is extended to the systems such as flight control and the fields such as tanks, ships and warships, and spaceflight gradually. According to the interface board, the PCI architecture is realized by the bus drive circuit; and the interface board can be interconnected with an onboard computer conveniently, so that space is saved, and the anti-interference capacity is high.

Calibration of current sensors in parallel power converters

Abstract: An uninterruptible power supply (UPS) system (100) comprises a plurality of UPS units (UPS-1, UPS-2) connected in parallel. The controllers (130) of the units are programmed to implement a voltage calibration procedure and a current calibration procedure, in order that measurements of voltage and current made by sensors within the different units will agree. In the current calibration procedure, the load is disconnected (302) while one of the units is selected as a master and operates in a voltage control mode (VCM) (Steps 304-308). Each other unit is selected in turn and operated in a current control mode (310, 312). Current measurements made in the master unit are communicated (314) via a data bus to the selected unit and compared (316) with measurements made in the unit itself. The unit adapts its current sensing gains to match the master unit.

Wishbone bus architecture - a survey and comparison

Abstract: The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license.