Showing papers on "System on a chip published in 1981"

Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection

Abstract: Design rules and test structure are used to implement machine designs to thereby obviate during testing the need for mechanical probing of the chip, multichip module, card or board at a higher level of package. The design rules and test structure also provide a means of restricting the size of logic partitions on large logical structures to facilitate test pattern generation. A test mechanism is available on every chip to be packaged to drive test data on all chip outputs and observe test data on all chip inputs, independent of the logic function performed by the chip. A control mechanism is also provided to allow a chip to either perform its intended function or to act as a testing mechanism during package test. It is intended that the test mechanism built into every chip will be used in place of mechanical probes to perform a chip-in-place test and interchip wiring test of the package. The intent of the design rules is to design chips such that each chip can be "isolated" for testing purposes through the pins (or other contacts) of a higher level package containing such chips. It is also required that the "Level Sensitive Scan Design" (LSSD) discipline, or rules, be followed for each chip and for the package clock distribution network. Further, the LSSD Rules which ensures the capability of scanning data into and out of the package SRLs (shift register latches) must be satisfied for the total package.

Testing embedded arrays in large scale integrated circuits

Abstract: An integrated circuit chip having an embedded array (10) which is not directly accessible from the primary input/ output chip pins is manufactured with additional test circuitry directly on the chip, such that the performance of the array may be physically tested from the input/output pins by an external chip tester while the array remains embedded. Because of the added test circuitry (12, 14, 16, 18, 22, 24, 26), tests are not limited to the original chip architecture, and a variety of array tests may be made by an external tester without redesigning the chip architecture.

Terminal and Cooling Requirements for LSI Packages

Abstract: As the level of digital circuit integration on integrated circuit (IC) chips increases, more input-output (I/0) terminals are required on the chip package. More terminals mean a larger conventional package. This can frustrate achievement of higher overall gate density on the printed circuit (PC) board assembly. Chip packages providing terminals as a function of package area or at reduced terminal pitch offer some relief. Gate density may also be thermally limited. Coefficient and exponent values are empirically derived for the Rent equation to predict terminal requirements. A graphical means is developed which can help the designer visualize the trade-offs between package type, terminal pitch, and cooling requirements. Some practical examples are described.

Low Cost Chip Carriers for the 1980's

Abstract: Most industry people are projecting an accelerated market penetration in the 1980's for the various forms of chip carriers as laid out by the Joint Electron Device Engineering Council (JEDEC) JCII-3 committee. Many papers have been written promoting its advantages over the old reliable dual in-line package (DIP)-advantages like size, weight, thermal, electrical, and reliability. A novel approach for low cost leaded chip carriers, centered within the JEDEC standards, in both hermetic and plastic versions is outlined. By careful utilization of precious metals, hardware commonality, and process simplification, savings of up to 50 percent can be achieved over present-day chip carrier costs. After a review of chip carrier parameters, both necessary and desirable, an outline of Bell Northern Research's (BNR's) solution highlighting hardware design, flow charts, test results, and comparative material costs curves is pre- sented.

"Monomax"-An Approach to the One-Chip TV

Abstract: Monochrome TV receivers, like portable AM radios, have remained impenetrable to the skills of the linear IC designer - mainly because of very stringent cost requirements and relatively low demands on performance. There is, however, a market demand for a more sophisticated breed of receiver for portable use which is relatively complex when built with discrete components.

Chip Carrier Applications

Abstract: The chip carrier package is gaining acceptance as a largescale integration (LSI) and very large-scale integration (VLSI) circuit package which can be integrated with medium-scale integration (MSI), small-scale integration (SSI), and passive components onto conventional printed wiring boards. In addition, the chip carrier package is being used to manufacture high density small modules which can be used as stand-alone functions or interfaced with conventional printed circuit boards as modular building blocks. In manufacturing high density small ceramic modules with devices in chip carriers, a soft assembly and test approach has been found to be useful during the start-up phase of a new product.