Showing papers on "Timer published in 1987"

Microcomputer which enters sleep mode for a predetermined period of time on response to an activity of an input/output device

Abstract: When information from input/output devices is requested by application software, a timer sets a predetermined sleep time period, and when the sleep time period expires, it is checked whether the information has been obtained. The sleep time period is suitably set in consideration of the response speed of the input/output devices and the influence of the delay on the processing. Accordingly, the sleep mode is entered while waiting for an input/output response, thus reducing electric power consumption.

Method of maintaining a topology database

Abstract: Each network node in a communications network maintains its own copy of the network topology database defining network resources. Each resource record contains a "timer" field which is initially set to a maximum value but which may be decremented on a daily basis. If the timer field is decremented to zero without being reset, the node unilaterally removes the resource record from its copy of the database. The timer field will normally reach zero only for obsolete resource records since each network node responsible for a resource broadcasts a timer-resetting message for the resource (1) each time the resource status changes, (2) when the node first joins or rejoins the network, and (3) on a periodic (weekly) basis regardless of whether conditions (1) or (2) have occurred.

Hashed and hierarchical timing wheels: data structures for the efficient implementation of a timer facility

Abstract: Conventional algorithms to implement an Operating System timer module take O(n) time to start or maintain a timer, where n is the number of outstanding timers: this is expensive for large n. This paper begins by exploring the relationship between timer algorithms, time flow mechanisms used in discrete event simulations, and sorting techniques. Next a timer algorithm for small timer intervals is presented that is similar to the timing wheel technique used in logic simulators. By using a circular buffer or timing wheel, it takes O(1) time to start, stop, and maintain timers within the range of the wheel.Two extensions for larger values of the interval are described. In the first, the timer interval is hashed into a slot on the timing wheel. In the second, a hierarchy of timing wheels with different granularities is used to span a greater range of intervals. The performance of these two schemes and various implementation trade-offs are discussed.

System with a timer screen, for reserving the recording of TV programs

Abstract: A timer reservation display controller outputs data to be displayed on a display screen. The data includes a predetermined number of guidances, menus, and items associated with timer reservation for the recording of several weeks of TV programs. The data is displayed in complete week intervals beginning with the current day. In conjunction with the displayed data, a pointing device allows the user to point to and select the displayed data to choose desired timer reservation periods for TV programs recording.

Millisecond interval timer and auditory reaction time programs for the IBM PC

Abstract: Many types of behavioral research require the determination of elapsed time, for example to establish interstimulus intervals and to measure reaction time. The use of an IBM PC for on-line control of such applications is limited by the poor timing resolution ordinarily available. The IBM BIOS time information that is used for the BASIC TIMER function can result in interval timing errors as great as 110 msec. A machine language subroutine is described that can provide 1-msec accuracy. A BASIC program is also described that employs this subroutine to measure auditory reaction time.

Communications management system having multiple power control modes

Abstract: A communications management system for use in conjunction with a host computer includes independently powered processing circuitry which automatically powers up the host computer upon receipt of an incoming message or initiation of an outgoing message, thereby avoiding the need for the computer to be continuously powered. The computer is also powered-up by user-actuation of a panel switch, or by an internal timer which establishes a predetermined powered-up monitoring period. A mode selection circuit prevents conflicts between the various power control factors when powering down the computer.

Microcomputer system with watchdog timer

Abstract: A microcomputer executes a certain system program with a microprocessor according to a certain system clock. The microcomputer includes a watchdog timer circuit provided external to the microcomputer which counts a certain time interval by counting a certain timer clock which is separate from the system clock with a counter for a certain count and, upon completion of the counting, forcibly resets the microprocessor of the microcomputer. The system program of the microprocessor has a step of producing a reset output to the counter before a predetermined time only when the system action is normal. There is provided a timer circuit which counts the system clock of the microcomputer with a certain counter for a certain number of counts, counting a time interval which is slightly longer than the normal period of the timer clock of the watchdog timer circuit, and upon completion of the counting interrupts the microprocessor of the microcomputer. The system program of the microcomputer has a step in which reset output is supplied to the counter of the timer circuit in a repeated manner according to the monitoring result of the timer clock of the watchdog timer so as to respond to either the rise or the fall of the timer clock, and a step in which an abnormal output is produced to the outside in response to the interruption from the timer circuit. Thereby, the operation of the microcomputer and of the watchdog timer can be effectively checked and monitored.

Multiple time delay power controller apparatus with time delay turn-on and turn-off

Abstract: Multi-time delay power controller apparatus for providing time delayed power-up and power-down for associated electrical equipment, such as computer systems, comprises a power stage configured for connecting to a conventional power outlet, a D.C. power supply connected to an internal D.C. voltage bus, an output stage having a plurality of time delayed outputs and a plurality of time delay turn-on timing stages connected in electrical series with one another between the D.C. bus and ground. Each such stage comprises an R-C circuit and a type 555 integrated circuit which together function as a timer. Included in each stage is a control relay. The energizing coils of the relays in odd numbered stages are connected to ground and of even numbered stages to the D.C. bus. The timing stages are connected so that the timing out of one stage starts the timing of the next-in-sequence stage, the timing of the first-in-sequence stage being started when the apparatus is turned on. The control relays, which provide voltage to the time delayed output stages are energized, in sequence, when each stage times out. Timed delay turn-off means are provided for sequentially removing the voltages to the outputs in the reverse order in which voltage is applied by operation of the control relays. The time delay turn-off means include relays through which the time delay turn-on relays are energized and which cause deenergizing of the control relays in the turn-off sequence.

Paging receiver having audible and vibrator annunciating means

Abstract: A paging receiver which includes a conventional receiver circuit for receiving a paging signal, having a page number that identifies the intended recipient, a memory for storing a unique page number which is assigned to that particular receiver and a decorder for comparing the page number included in the received paging signal with the page number which is stored in the memory. If the stored and received page numbers coincide, detection pulse is produced that starts a first and a second timer. The first timer produces a mode switch pulse following the lapse of a first predetermined period of time. The second timer which has a period longer than first period of time, generates an auto-reset pulse upon lapse of its period. The mode switch pulse and the auto-reset pulse are sent to an annunciation mode switch having an output for driving both a tactile annunciator and an audible annunciator. The detection pulse causes the annunciator mode switch to energize one of the tactile and audible annunciators. When the mode switch pulse is generated by the first timer, the annunciator mode switch will drive the other of the two annunciators and turn the first annunciator off. Finally, the auto-reset pulse will cause the annunciation mode switch to turn off the second annunciator. A manual reset switch also provides a reset pulse input to the annunciation mode switch when can stop the activation of either the tactile or audible annunciator at anytime.

Control and display system

Abstract: A control system comprises a liquid crystal display panel; a light source; and a light detector. Light from the source is directed through at least a portion of the liquid crystal display panel to the light detector. A control circuit is provided for holding the liquid crystal display in generally opaque condition while preferably sequentially momentarily clarifying segments of the portion, whereby momentary, sequential, transversely spaced light beams are generated between the light source and the light detector. A timer and logic circuit is provided for correlating signals received from the light detector with generated, individual, spaced light beams that create the signals. Accordingly, occlusion of at least one of the individual light beams with an opaque member causes a specific characteristic response by the timer and logic circuit. In other words, when one of the individual light beams is occluded, the timer and logic circuit emits a characteristic signal which might activate a relay, send an instruction to a microprocessor, or cause some other action.

Electric food mixer

Abstract: An electric food mixer includes an electronic control for operating the mixer in one of a plurality of three modes as selected by a user. In a normal mixing mode, the user selects the speed of the motor and starts and stops the motor by manually actuating a switch. In a timed mixing mode, the user selects the desired running time of the motor as well as the speed of the motor. The motor is started in this mode in response to the manual actuation of a switch, but automatically stops upon the expiration of the selected running time. In a utility timer mode, the mixer is controlled to operate as a utility count-down timer. Upon starting the mixer in the normal mixing mode or in the timed mixing mode, the motor is controlled to start at a slow start-up speed that is less than any of the selectable mixing speeds.

Parking meters capable of being operated without monetary coins

Abstract: A parking meter capable of being operated without the use of a monetary coin. The parking meter is intended to be used with an account card incorporating a read/write memory (e.g. a magnetic strip) pre-recorded with a monetary value. The parking meter has a body with a slot or the like for receiving the account card, means for reading the memory on the card, a comparator for comparing information from the memory with stored information, a timer for measuring a predetermined time period, an indicator for indicating the elapse of the time period, a start mechanism for the timer having an enabling or disabling control governed by the comparator and an amending device for amending the memory on the account card to deduct the value of the parking period bought by the user.

Dim-down electric light time switch method and apparatus

Abstract: An electrical timer which controls the ON-time of a light bulb circuit hooked up to a power source by way of an ordinary power switch. Usual operation of the timer is such that, when the power switch (which is initially OFF) is turned ON by a person, the light bulb which is connected to the switch by way of the timer will first turn-on FULL brightness for a period of time, after which it will DIM-down to about 30 to 50 percent brightness. In a fundamental version of the timer, the light bulb will remain in the dimmed-down mode until a person turns the light switch OFF. Another version allows that after a period of time in the dimmed-down mode, the light bulb will be fully shut OFF by the timer. The dimmed-down mode may also be arranged to occur in two or more level steps, i.e. part-DIM and full-DIM for example, with each step having a finite and substantial duration. A touch-strip may also be provided in which, when "touched" by a person, body capacitance serves to reset a dimmed-down light to full-brightness. The solid state modular timer may work in conjunction with any ordinary " two-terminal" wall-type electrical switch, such as commonly used in building construction.

Photoelectric vehicle position indicating device for use in parking and otherwise positioning vehicles

Abstract: The position indicating device is employed to assist in parking and otherwise positioning a vehicle on a supporting surface. A photoelectric control unit is mounted on an overhead structure spaced above the supporting surface and has a beam emitting device for directing a light beam downwardly for interception by the vehicle, while minimizing the likelihood of interception by pedestrians, pet animals and other moving things. The light beam is initially reflected back to a photoelectric transducer on the control unit by a reflective device or mirror. The light beam is pulsed so that the transducer supplies electrical pulses to an amplifier which is correspondingly gated. When the light beam is interrupted by the vehicle, the amplifier produces a beam interruption output signal which causes a one-shot timer to energize an alarm device, through an output relay. The operator then stops the vehicle in the desired position. The one-shot timer de-energizes the alarm device after a brief interval. Alternatively, the mirror is not employed, and the light beam is not significantly reflected back to the transducer until the light beam is intercepted by the vehicle, whereupon reflection from the vehicle produces a reflected light beam to the transducer. The corresponding pulsed signals from the transducer operate the amplifier, which is modified so that it actuates the timer, whereby it energizes the alarm device for a timed interval.

Method and apparatus for detecting standing heat in cattle

Abstract: A membrane switch (24) is connected to an electronic timer module (31) which includes a digital timer display (13), a mounting counter display (16), a flashing clock signal (14) to indicate activation of the module, as well as audible (28) and visible indicators. An oval-­shaped sleeve (32) includes a transparent pocket (36) containing the timer module (31) and membrane switch (24), and the sleeve is adapted to be adhered to the base of the tail of a cow. The membrane switch (24) is adapted to be actuated by the weight of other cows attempting to mount the cow when in heat. The switch (24) actuates the timer, the mounting counter, and the flashing clock display (14), and also actuates the audible and visible signals to warn the cattle owner that the cow is in heat, to indicate how long the cow has been in heat, and also how many times the cow has been mounted.

Programmable sequence generator

Abstract: A programmable sequence generator comprises a combinatorial logic matrix (10,12) and an on-chip timer (24) having count lines (26) coupled as inputs to the logic matrix (10). Combinatorial logic functions may be programmed into the matrix having as variables external inputs (14), a count number represented by the count lines (26) and internal inputs (48) fed back from outputs of he logic matrix (12). In a preferred embodiment, state registers (46) are provided, such that the programmable sequence generator can operate in any one of a plurality of different states. The programmable sequence generator can be configured as a waveform generator (92), a refresh timer (94) or a dynamic memory timing controller (96), among other programmable logic applications.

Auxiliary heater controller

Abstract: An auxiliary heater controller (100) is provided for use with a liquid cooled engine (22) which includes two fluid circuits. The first fluid circuit includes the engine (22), a heat exchanger (12) with an air flow creating fan (16), a heater and a pump unit (18), while the second fluid circuit shunts the engine (22) and includes only the heat exchanger (12), heater and pump unit (18). A single two-way valve (20) operates to direct fluid to either the first or the second fluid circuit, and a timer unit (70) is provided which operates automatically at a preset time to cause a fluid to flow in the first fluid circuit for a predetermined time period. The air flow creating fan (16) is operated by a thermostat (116) at low speed when the engine (22) is not operating and is operated by a manually controlled variable speed control unit (114) when the engine (22) is operating.

Automatic power bus transfer equipment

Abstract: A circuit for protecting the power contacts (18, 20) of automatic bus transfer equipment, including high speed solid state switches (30, 32) connected across the respective contacts. A timing and steering circuit (36) is responsive to the electrical energization of a solenoid (22) for firing the solid state switch (32) connected across the closed contact (18). A timer (48) is responsive to the opening of the contacts (18). At the elapse of a time period, the firing circuit (34) is caused to operate the solid state switch (30) before the closing of the contacts (20). The solid state switch (30) is maintained operated for a predetermined period of time by a timer (90).

Timer/counter using a register block

Abstract: A timer/counter comprising an operation controller coupled to receive a control information for generating control signals for a selected operation, and a register block coupled to a bus and including a plurality of count registers, a corresponding number of timer registers storing various set values and a buffer circuit controlled by the operation controller to sequentially read data from one of the count registers to the bus and then write the data on the bus to the same count register. An incrementer is coupled to the bus and controlled by the operation controller to increment the data on the bus and to ouput an incremented data to the bus. A coincidence flag coupled to the register block is set when the incremented data in a count register of the timer block has coincided with a value stored in a corresponding timer register. A clear controller coupled to the coincidence flag clears the count register having the count value in coincidence with the value of the corresponding timer register.

IC card identification system including pin-check time means

Abstract: An IC (integrated circuit) card identification system includes a comparator for comparing a first identification number entered by a cardholder with a second identification number, a storage memory for storing at least the second identification number, a timer for measuring a time lapse during a card-identifying operation, and a central controller for controlling the timer to set a first processing time period to be substantially equal to a second processing time period. During the first processing time period, the comparator determines that the first identification number is coincident with the second identification number since the first identification number has been entered. During the second processing time period, the comparator determines that the first identification number is incoincident with the second identification number since the first identification number has been entered.

High velocity hot air sterilization device with controller

Abstract: An automatically controlled recirculating high velocity hot air sterilization device includes a housing having a sterilization chamber with a temperature sensor mounted therein, a hot air plenum including a blower in fluid communication with a heating element and sterilization chamber for inputting hor air into and receiving hot air from the sterilization chamber for recirculation, and a control chamber having a temperature sensing circuit connected to the temperature circuit for producing electrical inputs representative of the sterilization chamber temperature, power circuits connected to the heating element and blower, a controller connected to the temperature sensing circuit for monitoring the temperature, and to the heating element and blower circuits for controlling their operation, and a control panel including cycle selection switches for operation, an on/off switch, and temperature and timer/error displays. The controller is designed for monitoring the cycle selection switches and on/off switch, for controlling operation of the heating element, blower and timer for the cycle selected, for monitoring the temperature, for starting the timer when the temperature rises to the required temperature, for restarting the timer should the temperature fall below the required temperature during a cycle, for shutting down the device when a catastrophic failure occurs and for outputting an error signal together with problem information for display.

Colour graphics control system

Abstract: A color graphics control system for generating red, blue and green analog signals to a raster scan display at a pixel frequency comprises a RAM storing a pluraltiy of digital color values, digital to analog converters for converting the digital color values into analog signals, an interface to permit an external controller to write digital color values into the RAM locations, a timer including a pixel clock and RAM accessing means controlled by the timer to pipeline RAM accessing with a cycle time of more than one pixel period.

Watchdog circuit for monitoring programs and detecting infinite loops using a changing multibit word for timer reset

Abstract: A data processing system includes a microcomputer (1) provided with an address latch (5). The microcomputer is provided with a watch-dog arrangement which comprises the usual clocked counter (17) an output (Qn) of which is coupled to a reset input (RST) of the microcomputer. In order to increase the number of malfunctions to which the watch-dog responds the microcomputer is arranged to repeatedly generate reset signals each in the form of a complete byte X or Y which alternate. These are applied to an input (30) of a comparator (10) which compares them with identical bytes fed to a further input 31 via a switched multiplexer (13), the comparator output (37) being connected to a reset input (RS) of the counter. Each time this occurs the microcomputer strobes the watch-dog by applying its address to a further input (46, 22). If the byte applied to the comparator input (30) is incorrect and/or if this application does not occur within a time window defined by a period during which a further output (Qn-1) of the counter is logic " 1" the resulting level at the comparator output (37), stored in a flip-flop (15), resets the microcomputer. The state of the signal at the further output (Qn-1) of the counter is periodically ascertained via a buffer (18). Each of the bytes X and Y is obtained by complementing the previous such byte, stored in RAM, further program steps being carried out between each such complementing operation and the preceding and succeeding generation of a reset signal.

Reliable fuzzy fault tolerant controller

Abstract: The invention is a controller which provides continuous regulation of the output of a process or a plant as well as performing discrete control functions. The REFFTAC includes an adaptive direct digital controller (ADDC) as a primary expert controller and a fuzzy expert controller (FECD) as a backup controller. In case of an error or failure of the primary ADDC the control function is transferred via an interface system (INF) to the FEC, thus preventing any fault in the REFFTAC mission. The INF system is a simple fuzzy controller which includes means to verify the control action and a timer to assure proper control action. It also includes a simulator that performs a self diagnosis on both the ADDC and the FEC to assure fault tolerance. Also, the REFFTAC comprises learning expert units which stores correct control actions for direct application to save time and to provide a reference for the INF system.

Asymmetrical duplex error-controlled modem

Abstract: A modem for connecting data terminal equipment (DTE) to a remote DTE via a general switched telephone network or leased lines at data rates of 300, 1200 and 2400 bps using standard modulation techniques, and additonally providing virtual full duplex transmission capability at 9600 bps using trellis code modulation (TCM). The high-speed 9600 bps path is implemented by asymmetrical frequency division of the available bandwidth into a high speed, wideband forward channel (9600 bps) and a low speed, narrowband backchannel (300 bps). The high speed transmitting channel is assigned to that modem having the greatest data demand and the direction is dynamically reversed whenever the amount of data awaiting transmission over the low speed channel exceeds a predetermined maximum backlog, provided that a direction reversal has not taken place for at least a specified minimum interval during which use of the forward channel is guaranteed. To improve the efficiency of the backchannel, extended data formats are added to the MNP link protocol for use in backchannel transmission and to control direction reversals on the line. The modem is implemented with three available general purpose microprocessors with interprocessor communications being synchronized by a timer driven interrupt mechanism. A hardware timer/counter built into one of these processors is used to monitor the signals on the telephone line to detect and distinguish answer tones, voice signals, busy signals, ringback signals and dial tones. A hardware counter/timer is also used to measure the width of the start bit from the serial port to form the basis for a calculation of the baud rate being used by the DTE.

Cardiac pacer with patient-controlled exercise rate and method

Abstract: A cardiac pacemaker pulse generator is adapted to .generate electrical stimuli at a first pacing rate, and to selectively increase the rate to a second higher pacing rate. A timer triggers the rate increase to establish the higher rate as an exercise rate folloing the passage of a preset period of time after the timer is enabled. An external magnet controlled by the patient activates a reed switch to enable the timer to commence timing. The pulse generator is further adapted to respond to a second pass of the magnet over the reed switch after enabling of the timer to thereupon disable the timer before the preset period of time has expired. If the second pass of the magnet occurs after the exercise rate has begun, the element for increasing the rate is disabled to return the pulse generator to the lower pacing rate. The change in pacing rates is made in steps.

Circuit breaker current monitoring

Abstract: A circuit breaker monitoring system for monitoring three-phase circuit breakers includes three channels that convert a respective phase current through a respective set of circuit breaker contacts into a sequence of digital signals each representative of an instantaneous value of current through the contacts. Each channel includes a transformer having a primary winding that receives current corresponding to that through the breaker contacts. A resistor across the secondary winding develops a voltage proportional to the current. An input buffer voltage follower couples this voltage to the input of a high-speed 12-bit bipolar analog-to-digital converter that provides the digital signals. A microprocessor coupled to a 12K RAM working memory, a 4K EPROM that may store breaker monitor software and a 2K E 2 PROM that may store programmable operating parameters and digital signals representative of accumulated fault current, processes the digital signals to provide a digital RMS current signal representative of the RMS value of the current through breaker contacts immediately after opening each time a source of a nonmaskable CPU interrupt signal provides that signal in response to the occurrence of auxiliary breaker contacts changing state. The microprocessor is coupled through a parallel input output interface to a 20-character LCD alphanumeric display and to relays for indicating an alarm condition when breaker contacts need servicing, including extinguishing a green light and illuminating a red light. Another parallel input/output interface intercouples the microprocessor and a keyboard. A serial input output interface may couple a computer or printer with the microprocessor and both are coupled to a counter timer clock. A real time clock with battery backup provides date and time information.

Self-contained disposable timer for use with medication

Abstract: A highly portable, disposable, self-contained timer provides a user-perceptible signal at automatically-successive, fixed time intervals to alert the user as to the times for taking medications. The time intervals are not variably programmable, and different timers having different fixed time intervals are provided for use with different medications. Preferably, the time intervals are nonuniform, comprising multiple shorter intervals combined with a longer interval corresponding to a normal sleeping period so that, when the timer is initialized in accordance with the user's sleeping cycle, no signal is emitted while the user is asleep. The device is powered by a nonreplaceable battery for economy and disposability, and a deactivator circuit is included which permanently disables the unit after a predetermined length of time well within the life of the battery. A signal emitted by one of a number of timers is easily distinguished, without requiring an audible signal of excessive duration, by a visual signal of substantially longer duration than the audible signal.

Battery charging and cycling devices

Abstract: A cycling device for conditioning battery cells of different types. A selor allows an operator to select the type of the cells to be conditioned. The amplitudes of trickle, discharge and charging currents are automatically selected in response to an output signal from the cell type selector. A control circuit determines the sequence of occurence of the trickle, discharge and charging currents and produces discharge and charge logic conditions, which control circuit includes a timer which delivers a clock signal and which interrupts the charging current after the same has been supplied to the battery cells during a predetermined period of time. Proper discharge operation of the cycling device is indicated only when both the discharge logic conditions are present and the discharge current is detected, while proper charge operation is indicated only when, simultaneously, the charge logic conditions are present, the charging current is detected, and the clock signal is produced by the timer. A detector indicates opening of the circuit through which flow the trickle, discharge and charging currents. The battery cells are so conditioned that at least some of the problems associated with their general use with lack of care, for example crystal growth, lost of internal contact with the sintered plates, etc. are cancelled. The original characteristics of the cycling device can also be applied to a battery cell charger.

Automatic power turn-off apparatus for an electronic apparatus

Abstract: In an automatic power turn-off apparatus, a signal for turning off power supply is outputted from a timer IC when time set by a power-off time setting key arrives, whereby the power supply of an associated copying apparatus is turned off. In the turn-off period, if an MPU determines that the copying apparatus is in trouble, the turn-off of the power supply is cancelled and the occurrence of the trouble in the copying apparatus is displayed in a display device to notify the user of the trouble.