Showing papers by "Alessandro Trifiletti published in 2018"

Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks

Abstract: Power analysis attacks (PAAs), a class of side-channel attacks based on power consumption measurements, are a major concern in the protection of secret data stored in cryptographic devices. In this paper, we introduce the secure double rate registers (SDRRs) as a register-transfer level (RTL) countermeasure to increase the security of cryptographic devices against PAAs. We exploit the SDRR in a conventional advanced encryption standard (AES)-128 architecture, improving the immunity of the cryptographic hardware to the state-of-the-art PAAs. In the AES-128 exploiting SDRR, the combinational path evaluates random data throughout the entire clock cycle, and the interleaved processing of random and real data ensures the protection of both combinational and sequential logics. Our technique does not require the duplication of the combinational path to process the random data, thus limiting area overhead, unlike previous RTL countermeasures. The proposed approach is validated by means of PAAs based on real measurements on a field-programmable gate array implementation and on a 65-nm CMOS prototype chip. The protected implementation shows a strongly reduced correlation coefficient for the correct key, and more than three orders of magnitude increase in the measurements to disclosure with respect to the unprotected AES-128.

Low power DDA-based instrumentation amplifier for neural recording applications in 65 nm CMOS

Abstract: The low power instrumentation amplifier (IA) presented in this paper has been designed to be the front-end of an integrated neural recording system, in which common-mode rejection ratio (CMRR), input referred noise and power consumption are critical requirements. The proposed IA topology exploits a differential-difference amplifier (DDA) whose differential output current drives a fully differential, high-resistance, transimpedance stage, with an embedded common-mode feedback loop to increase the CMRR. This stage is followed by a differential-to-single-ended output amplifier. Low-power operation has been achieved by exploiting sub-threshold operation of MOS transistors and adopting a supply voltage of 1 V. Simulation results in a commercial 65 nm CMOS technology show a 1 Hz to 5 kHz bandwidth, a CMRR higher than 120 dB, an input referred noise of 8.1 μVrms and a power consumption of 1.12 μW.

A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR

Abstract: An improvement of a standard fully differential class-AB symmetrical operational transconductance amplifier (OTA) topology is proposed in this brief to enhance the common-mode behavior. Common-mode behavior could be critical in fully differential class-AB OTAs, where the total current is not fixed and differential to common-mode conversion could therefore be present. A signal proportional to the input common-mode component is generated through a simple low-current auxiliary amplifier and used to modulate a bias voltage, achieving cancellation of the output common-mode component. Simulations in 40-nm CMOS technology show a net improvement of common-mode rejection ratio without affecting differential-mode behavior; the increase in area and power consumption is minimal, with a tradeoff between power and settling time. Simulations of a sample-and-hold exploiting the proposed OTA are presented.

TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results

Abstract: This paper presents experimental results on a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions. The proposed logic family is based on the time enclosed logic (TEL) encoding and can be viewed as an improvement of the delay based dual rail pre-charge logic (DDPL) logic style. The DDPL logic gates have been redesigned to avoid the early evaluation effect and to reduce area and power consumption. A library of TEL secure gates and flip-flops has been implemented in a 65 nm CMOS process. The developed library allows adopting a semi-custom design flow (automatic place and route) without any constraint on the routing of the complementary wires. A four bit lightweight crypto core has been implemented on a 65 nm CMOS testchip by using the developed TEL library and compared against a SABL implementation of the same crypto core on the same chip. Comparisons have been carried out by means of extensive transistor level simulations and measurements on the 65 nm testchip which allowed to evaluate a wide set of security metrics. Experimental results have shown a strong reduction of the information leakage with respect to the sense amplifier based logic logic style under mismatched load conditions with an improvement in the measurements to disclosure of more than three orders of magnitude.

New Models for the Calibration of Four-Channel Time-Interleaved ADCs Using Filter Banks

Abstract: New linear models to calibrate four-channel time-interleaved analog-to-digital converters are proposed and investigated. The ideal four-periodic correction filters, which cancel distortions, are computed as a function of the error filters that model the analog transfer function of each channel, including the sampling time. These correction filters are then approximated as a linear combination of base filters and new accurate models with a limited number of free parameters are proposed. Calibration is performed using the recursive least squares algorithm to estimate the coefficients of the linear combination (and the offset term). The resulting algorithms are tested for accuracy, convergence speed, and stability in a fixed-point implementation, and are compared with previously published linear background calibration techniques. The proposed filter bank significantly improves the accuracy/complexity tradeoff with respect to previously published techniques.

A 0.6 V class-AB rail-to-rail CMOS OTA exploiting threshold lowering

Abstract: A class-AB OTA (operational transconductance amplifier) topology with rail-to-rail input common-mode range is proposed for application in very low-voltage applications. High efficiency is achieved by reusing transistors both for class-AB operation and for mirroring the output currents, and a threshold lowering technique is applied to allow supply voltages less than two threshold voltages. Simulations in 40 nm CMOS technology show 41 dB gain at ±0.3 V supply voltage, a unity-gain frequency of 8.8 MHz on a 5 pF load, class-AB behaviour and full rail-to-rail operation when closed in unity-gain buffer configuration.

A Directly Modulated Multiwavelength Transmitter Monolithically Integrated on InP

Abstract: This paper presents an integrated multiwavelength transmitter with eight channels realized on a generic InP integration platform. The photonic integrated circuit (PIC) comprises eight tunable directly modulated distributed feedback lasers emitting in the C-band, eight monitoring photodetectors, and MMI couplers. The PIC has been mounted on a printed circuit board for easier operation and wavelength control. The directly modulated lasers, designed with a 100 GHz spacing between 1541.4 and 1547 nm, show a 3-dB bandwidth up to 12 GHz and a tunability range of about 4 nm. Transmission experiments demonstrate error-free operation in back-to-back and open eye-diagrams up to 20 Gb/s per channel, while short-range communications (along a 2.1 km fiber span) up to 15 Gb/s per channel incur in a limited power penalty (4.5 dB at a bit error rate = 10 −9).

A Novel Very Low Voltage Topology to implement MCML XOR Gates

Abstract: A new very low-voltage topology to implement MOS current mode logic (MCML) XOR gates is proposed in this paper. Instead of stacking several level oftransistors to implement a two inputs XOR gate, a p-type differential pair is used to steer the current in n-type differential pairs through current mirrors. The proposed topology allows to reduce the minimum supply voltage of MCML XOR gates while guaranteeing a fully current mode behavior as in the conventional XOR gate. The proposed topology has been compared against the conventional and triple tail MCML XOR gates. Simulation results referring to a $40\mathrm {n}\mathrm {m}$ CMOS technology for $V_{DD}=1\mathrm {V}$ confirm that the XOR gate presented in this work exhibits a lower propagation delay than the previously published low voltage MCML XOR gate. Furthermore both theoretical analysis and simulation results in a $40\mathrm {n}\mathrm {m}$ process show that the proposed topology is able to work with a VDD as low as $0.~65\mathrm {V}$ whereas state of the art topologies are not usable below $0.~8\mathrm {V}.$

Machine learning techniques for frequency sharing in a cognitive radar

Abstract: A Cognitive Radar, working in a frequency dense environment, has to perform effective wideband operations, spanning several frequency channels, by working in parallel with other radar and/or communication systems. The cognitive operation is possible by modeling the channel behavior and predicting future channel occupancy. The model of the electromagnetic environment is based on the observation of the spectrum occupancy during a number of time slots and on suitable machine learning to acquire the characteristics of the channel occupancy. The learning operation is paramount, as the prediction about channel occupancy is possible only after understanding the behavior of the concurrent emitters present in the scenario. This paper describes the concept of machine learning techniques, based on emitter pattern classification and matching. implemented on a number of real cases of emitter behavior. In particular, we are defining these techniques by considering four real cases of emitter behavior, namely fixed, sequential, periodical and random channel acquisition. We show that, in the above examined cases, our machine learning techniques can provide good emitter matching, even in presence of a consistent number of concurrent transmitters.

A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering

Abstract: This paper presents a novel topology to implement CML D-Latches in deeply scaled CMOS technologies under very low supply voltage requirements. The proposed modified Folded MCML D-Latch topology exploits a dynamic body bias approach to achieve a reduction of the threshold voltage of about 100mV thus allowing proper operation with a minimum supply voltage as low as 0.6V. Simulation results in a commercial 40nm CMOS process are provided to show the advantages of the proposed approach with respect to the state of the art. At the best of our knowledge, no other CML D-Latch topologies are able to operate at such a low supply voltage. The triple-tail D-Latch, also known as low voltage CML D-Latch allows a minimum supply voltage of 0.8V in the same reference 40nm CMOS process.

A 2-channel digitizer based on MFP strategy

Abstract: A 2-channel digitizer based on a mixing-filtering-processing (MFP) strategy capable of granting ultra-high bandwidth and sampling rate is presented. The digitizer requires suitable digital signal processing resources, which consist of several dedicated integrated circuits (ICs), to produce a digital representation of the input signal. Processing is also in charge of streamline calibration, that involves eliminating the artefacts due to mismatches between individual channels and equalizing the frequency response of the system. The design issues related to the implementation of calibration and signal reconstruction are presented. Tests needed to assess the system configuration at the manufacturing stage are also discussed.

Secure Implementation of TEL-compatible Flip-Flops using a Standard-Cell Approach

Abstract: The Time Enclosed Logic (TEL) is a dual-rail signaling protocol used in the context of cryptographic circuits in order to maintain the time enclosing of information leakage also in the presence of capacitive mismatch. The capacitive mismatch, due to non-perfectly balanced differential routing, provides additional data-dependent leakage that a malicious adversary could use to recover secret information from a hardware implementation. In this work, a novel TEL-compatible standard-cell based flip-flop for cryptographic application is presented. The new flip-flop is intended to be compatible also for FPGA applications. The novel standard-cell architecture has been tested with energy-defined metrics adopting a 4-bit register as case study, implemented in 40nm CMOS process. It has been found that it is able to reduce the data-dependence of the power consumption up to ×0.05 also in the presence of strong mismatch if compared to unprotected CMOS. A comparison with WDDL and MDPL has shown that NED and NSD are remarkably reduced (up to ×30 and ×40 respectively), and their values are independent from the capacitive mismatch in the novel flip-flop architecture.