다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Information Theory and Reliable Communication

Random number generators in digital information systems make use of physical entropy sources such as electronic and photonic noise to add unpredictability to deterministically generated pseudo-random sequences1,2. However, there is a large gap between the generation rates achieved with existing physical sources and the high data rates of many computation and communication systems; this is a fundamental weakness of these systems. Here we show that good quality random bit sequences can be generated at very fast bit rates using physical chaos in semiconductor lasers. Streams of bits that pass standard statistical tests for randomness have been generated at rates of up to 1.7 Gbps by sampling the fluctuating optical output of two chaotic lasers. This rate is an order of magnitude faster than that of previously reported devices for physical random bit generators with verified randomness. This means that the performance of random number generators can be greatly improved by using chaotic laser devices as physical entropy sources. Random-number generators are important in digital information systems. However, the speed at which current sources operate is much slower than the typical data rates used in communication and computing. Chaos in semiconductor lasers might help to bridge the gap.

Fast physical random bit generation with chaotic semiconductor lasers

The power consumed by a circuit varies according to the activity of its individual transistors and other components As a result, measurements of the power used by actual computers or microchips contain information about the operations being performed and the data being processed Cryptographic designs have traditionally assumed that secrets are manipulated in environments that expose no information beyond the specified inputs and outputs This paper examines how information leaked through power consumption and other side channels can be analyzed to extract secret keys from a wide range of devices The attacks are practical, non-invasive, and highly effective—even against complex and noisy systems where cryptographic computations account for only a small fraction of the overall power consumption We also introduce approaches for preventing DPA attacks and for building cryptosystems that remain secure even when implemented in hardware that leaks

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Introduction to differential power analysis

Analogue IC Design: the Current Mode Approach

In CMOS smart sensors and microsystems it can be very convenient to integrate both analog and digital circuits in the same chip; since the supply voltage for high-accuracy, high- precision interfaces should be as immune from disturbances as possible, low drop out regulators are often necessary. Here we show a CMOS, dual op amp, fast, low drop out regulator which allows to diminish the power supply gain by orders of magnitude up to very high frequencies.

Dual op amp, LDO regulator with power supply gain suppression for CMOS smart sensors and microsystems

We propose a variant for a published second-order power analysis attack [1] on a software masked implementation of AES-128 [2]. Our approach can, with reduced complexity, produce the same result as the original one, without requiring any additional tool. The validity of the proposed variant is confirmed by experiments, whose results allow for a comparison between the two approaches.

/pdf/on-practical-second-order-power-analysis-attacks-for-block-q2kdklk6hz.pdf

On practical second-order power analysis attacks for block ciphers

A novel topology for the offset-compensation and input-matching network of high gain differential amplifiers, tolerant with respect to parasitic effects of bonding wires, is presented. An IC for an optical receiver featuring this network has been designed, and simulations and measurements show high offset suppression (20 dB) and good input matching (1/spl Gamma/inl<-10 dB) over a wide bandwidth (100 kHz-3 GHz) when considering bonding wires some millimeters long.

Input-matching and offset-compensation network for limiting amplifiers in optical communication systems

We propose an inverting closed-loop amplifier architecture providing high input impedance and a theoretically zero gain error, without requiring infinitely large loop gain. The architecture is based on two nested amplifiers closed in feedback through a resistive network. A straightforward CMOS implementation is also given. Simulations using a 0.35-/spl mu/m CMOS process are found in agreement with expected results. Monte Carlo simulations have also shown the robustness of the proposed approach against process tolerances.

Inverting closed-loop amplifier architecture with reduced gain error and high input impedance

An analytical model to evaluate the hybrid architecture of a wide bandwidth high-speed digitizer is proposed. The model is based on the robust approach of multi-rate signal processing theory and allows analyzing the effects of the impairments that can affect the digitizer, and consequently evaluating achievable performance. The proposed model can also be used at design stage to identify viable solutions for counteracting the effects of the impairments. More specifically, it can be used to identify the correction filters that provide a digital representation of the input signal that minimizes spurious terms and distortions.

Alessandro Trifiletti

Papers

Dual op amp, LDO regulator with power supply gain suppression for CMOS smart sensors and microsystems

On practical second-order power analysis attacks for block ciphers

Input-matching and offset-compensation network for limiting amplifiers in optical communication systems

Inverting closed-loop amplifier architecture with reduced gain error and high input impedance

Multi-rate signal processing based model for high-speed digitizers