Alessandro Trifiletti

TL;DR: The paper describes an innovative technique to implement a low-power high-speed CMOS interface circuit for differential capacitive sensors that exploits an autotuning feedback loop to control the common-mode current, thereby ensuring virtually the same maximum sensitivity and measure accuracy irrespectively of the input parasitic capacitance.

TL;DR: A novel approach to optimize digital integrated circuits yield referring to speed, dynamic power and leakage power constraints is presented, based on process parameter estimation circuits and active control of body bias performed by an on-chip digital controller.

TL;DR: The proposed calibration technique employs wideband differentiators, thus enabling digital background calibration of timing skews even with wide band input signals, and it is shown that the technique is capable of calibrating undersampling converters by estimating the derivative of wideband input signals even outside the first Nyquist band.

TL;DR: The proposed integrated solution, having both low-voltage (LV) and low-power (LP) characteristics, can be applied with success in suitable IC applications such as floating capacitance multipliers and floating inductance simulators, utilizing a minimum number of active components.

TL;DR: Transistor-level simulations show that total harmonic distortion in the voltage-to-current conversion is decreased by 10 dB, and this THD improvement is achieved with a negligible increase in power consumption.