다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Information Theory and Reliable Communication

Random number generators in digital information systems make use of physical entropy sources such as electronic and photonic noise to add unpredictability to deterministically generated pseudo-random sequences1,2. However, there is a large gap between the generation rates achieved with existing physical sources and the high data rates of many computation and communication systems; this is a fundamental weakness of these systems. Here we show that good quality random bit sequences can be generated at very fast bit rates using physical chaos in semiconductor lasers. Streams of bits that pass standard statistical tests for randomness have been generated at rates of up to 1.7 Gbps by sampling the fluctuating optical output of two chaotic lasers. This rate is an order of magnitude faster than that of previously reported devices for physical random bit generators with verified randomness. This means that the performance of random number generators can be greatly improved by using chaotic laser devices as physical entropy sources. Random-number generators are important in digital information systems. However, the speed at which current sources operate is much slower than the typical data rates used in communication and computing. Chaos in semiconductor lasers might help to bridge the gap.

Fast physical random bit generation with chaotic semiconductor lasers

The power consumed by a circuit varies according to the activity of its individual transistors and other components As a result, measurements of the power used by actual computers or microchips contain information about the operations being performed and the data being processed Cryptographic designs have traditionally assumed that secrets are manipulated in environments that expose no information beyond the specified inputs and outputs This paper examines how information leaked through power consumption and other side channels can be analyzed to extract secret keys from a wide range of devices The attacks are practical, non-invasive, and highly effective—even against complex and noisy systems where cryptographic computations account for only a small fraction of the overall power consumption We also introduce approaches for preventing DPA attacks and for building cryptosystems that remain secure even when implemented in hardware that leaks

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Introduction to differential power analysis

Analogue IC Design: the Current Mode Approach

This paper presents novel CCII-based circuit solutions for the implementation of grounded and floating inductance simulators for integrable low frequency applications. The circuits, implementing a minimum number of active components, allow the reduction and, in theory, the zeroing of the undesired inductance series resistance, with consequent increase of operating range towards the low frequencies. A novel idea to increase the value of the equivalent inductance achievable with CCII based topologies is presented. Simulation results, confirming the theoretical expectations, are also included.

CCII-based high-valued inductance simulators with minumum number of active elements

The Voltage Conveyor (VCII) is the dual of the second generation Current Conveyor (CCII), and has received only a cursory attention in the literature, probably for lack of interesting applications. The VCII has a current buffer between Y and X terminals, and a voltage buffer between X and Z terminals. In this way, it makes it easier to sum (current) signals at the Y node, whereas CCIIs make it easier to sum (current) signals at the X node. Exploiting this difference between the two dual circuits, a very simple N-port synthesizer can be obtained using only N VCIIs. A mixed-signal Y-matrix synthesizer using VCIIs is also proposed, which is the dual of a similar one using CCIIs, and can also be used as an N-port analyzer, with an advantage with respect to the CCII-based version related to the possibility of sensing low-impedance (voltage) inputs. An inductor emulator and a lowpass / bandpass biquad filter are also simulated, showing the versatility of the VCII.

On the use of voltage conveyors for the synthesis of biquad filters and arbitrary networks

A novel current measuring technique is introduced which promises to substantially enhance power analysis attacks against cryptographic co-processors. The proposed technique exploits an active circuit to measure the instantaneous current consumption of a device under attack while supplying, at the same time, the device with a stable voltage. Higher gain-bandwidth product, higher sensitivity and lower insertion error are the main advantages with respect to a resistor-based measurement. Experimental results when the proposed circuit is used to measure the current consumption of an FPGA are reported and the achievable advantage in terms of sensitivity is discussed too.

Enhancing power analysis attacks against cryptographic devices

We propose a novel recursive least squares (RLS) algorithm that exploits the Frisch–Waugh–Lovell theorem to reduce digital complexity and improve convergence speed and algorithmic stability in fixed-point arithmetic. We tested the new algorithm in the digital background calibration section of a four-channel time-interleaved analog-to-digital converter, obtaining better stability and faster convergence. The digital complexity of the new algorithm in terms of multiplications and divisions is 33% lower asymptotically than that of the conventional Bierman algorithm if the model parameters need not be computed at each update; otherwise, it is the same. Memory requirements are also the same. Because, in calibration, the distance between the ideal and calibrated outputs of the system is to be minimized, the actual value of the model parameters is usually not of interest. Convergence time can be up to 10 or 20 times better in fixed-point arithmetic, and stability for large models is also better in our simulations. In our simulations, when the conventional Bierman RLS algorithm is stable, the steady-state accuracy of the new algorithm is either comparable or better, depending on the simulation setup.

Faster, Stabler, and Simpler—A Recursive-Least-Squares Algorithm Exploiting the Frisch–Waugh–Lovell Theorem

The three-state phase-frequency detector (PFD) is commonly used to improve the pull-in range of phase-locked loops, due to its ability to operate also in a frequency discriminator mode. However the delay of the feedback path, needed to eliminate the dead zone problem, limits the speed performance of the circuit and its linear input range, and can lead to average differential outputs with the wrong polarity, which disturb the acquisition process of the PLL. In this paper we present an alternative implementation of a three-state PFD, that with simple hardware modifications solves the problem of output polarity reversal, achieving much better frequency acquisition capabilities. The architecture does not rely on any assumption on the underlying VLSI technology.

Alessandro Trifiletti

Papers

CCII-based high-valued inductance simulators with minumum number of active elements

On the use of voltage conveyors for the synthesis of biquad filters and arbitrary networks

Enhancing power analysis attacks against cryptographic devices

Faster, Stabler, and Simpler—A Recursive-Least-Squares Algorithm Exploiting the Frisch–Waugh–Lovell Theorem

Robust three-state PFD architecture with enhanced frequency acquisition capabilities